// SPDX-License-Identifier: GPL-2.0
#ifndef __FSL_FTM_H__
#define __FSL_FTM_H__
#define FTM_SC
0 x0
/* Status And Control */
#define FTM_CNT
0 x4
/* Counter */
#define FTM_MOD
0 x8
/* Modulo */
#define FTM_CNTIN
0 x4C
/* Counter Initial Value */
#define FTM_STATUS
0 x50
/* Capture And Compare Status */
#define FTM_MODE
0 x54
/* Features Mode Selection */
#define FTM_SYNC
0 x58
/* Synchronization */
#define FTM_OUTINIT
0 x5C
/* Initial State For Channels Output */
#define FTM_OUTMASK
0 x60
/* Output Mask */
#define FTM_COMBINE
0 x64
/* Function For Linked Channels */
#define FTM_DEADTIME
0 x68
/* Deadtime Insertion Control */
#define FTM_EXTTRIG
0 x6C
/* FTM External Trigger */
#define FTM_POL
0 x70
/* Channels Polarity */
#define FTM_FMS
0 x74
/* Fault Mode Status */
#define FTM_FILTER
0 x78
/* Input Capture Filter Control */
#define FTM_FLTCTRL
0 x7C
/* Fault Control */
#define FTM_QDCTRL
0 x80
/* Quadrature Decoder Control And Status */
#define FTM_CONF
0 x84
/* Configuration */
#define FTM_FLTPOL
0 x88
/* FTM Fault Input Polarity */
#define FTM_SYNCONF
0 x8C
/* Synchronization Configuration */
#define FTM_INVCTRL
0 x90
/* FTM Inverting Control */
#define FTM_SWOCTRL
0 x94
/* FTM Software Output Control */
#define FTM_PWMLOAD
0 x98
/* FTM PWM Load */
#define FTM_SC_CLK_MASK_SHIFT
3
#define FTM_SC_CLK_MASK (
3 << FTM_SC_CLK_MASK_SHIFT)
#define FTM_SC_TOF
0 x80
#define FTM_SC_TOIE
0 x40
#define FTM_SC_CPWMS
0 x20
#define FTM_SC_CLKS
0 x18
#define FTM_SC_PS_1
0 x0
#define FTM_SC_PS_2
0 x1
#define FTM_SC_PS_4
0 x2
#define FTM_SC_PS_8
0 x3
#define FTM_SC_PS_16
0 x4
#define FTM_SC_PS_32
0 x5
#define FTM_SC_PS_64
0 x6
#define FTM_SC_PS_128
0 x7
#define FTM_SC_PS_MASK
0 x7
#define FTM_MODE_FAULTIE
0 x80
#define FTM_MODE_FAULTM
0 x60
#define FTM_MODE_CAPTEST
0 x10
#define FTM_MODE_PWMSYNC
0 x8
#define FTM_MODE_WPDIS
0 x4
#define FTM_MODE_INIT
0 x2
#define FTM_MODE_FTMEN
0 x1
/* NXP Errata: The PHAFLTREN and PHBFLTREN bits are tide to zero internally
* and these bits cannot be set. Flextimer cannot use Filter in
* Quadrature Decoder Mode.
* https://community.nxp.com/thread/467648#comment-1010319
*/
#define FTM_QDCTRL_PHAFLTREN
0 x80
#define FTM_QDCTRL_PHBFLTREN
0 x40
#define FTM_QDCTRL_PHAPOL
0 x20
#define FTM_QDCTRL_PHBPOL
0 x10
#define FTM_QDCTRL_QUADMODE
0 x8
#define FTM_QDCTRL_QUADDIR
0 x4
#define FTM_QDCTRL_TOFDIR
0 x2
#define FTM_QDCTRL_QUADEN
0 x1
#define FTM_FMS_FAULTF
0 x80
#define FTM_FMS_WPEN
0 x40
#define FTM_FMS_FAULTIN
0 x10
#define FTM_FMS_FAULTF3
0 x8
#define FTM_FMS_FAULTF2
0 x4
#define FTM_FMS_FAULTF1
0 x2
#define FTM_FMS_FAULTF0
0 x1
#define FTM_CSC_BASE
0 xC
#define FTM_CSC_MSB
0 x20
#define FTM_CSC_MSA
0 x10
#define FTM_CSC_ELSB
0 x8
#define FTM_CSC_ELSA
0 x4
#define FTM_CSC(_channel) (FTM_CSC_BASE + ((_channel) *
8 ))
#define FTM_CV_BASE
0 x10
#define FTM_CV(_channel) (FTM_CV_BASE + ((_channel) *
8 ))
#define FTM_PS_MAX
7
#endif
Messung V0.5 in Prozent C=95 H=96 G=95
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(vorverarbeitet am 2026-06-07)
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