| Quellcodebibliothek Statistik Leitseite products/Sources/formale Sprachen/C/Linux/drivers/media/dvb-frontends/drx39xyj/ (Open Source Betriebssystem Version 6.17.9©) Datei vom 24.10.2025 mit Größe 989 kB |
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Quelle drxj_map.h Sprache: C |
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/* Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name of Trident Microsystems nor Hauppauge Computer Works nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* ******************************************************************************** * WARNING - THIS FILE HAS BEEN GENERATED - DO NOT CHANGE * * Filename: drxj_map.h * Generated on: Mon Jan 18 12:09:24 2010 * Generated by: IDF:x 1.3.0 * Generated from: reg_map * Output start: [entry point] * * filename last modified re-use * ----------------------------------------------------- * reg_map.1.tmp Mon Jan 18 12:09:24 2010 - * */ #ifndef __DRXJ_MAP__H__ #define __DRXJ_MAP__H__ INCLUDED #ifdef _REGISTERTABLE_ #include <registertable.h> extern register_table_t drxj_map[]; extern register_table_info_t drxj_map_info[]; #endif #define ATV_COMM_EXEC__A 0xC00000 #define ATV_COMM_EXEC__W 2 #define ATV_COMM_EXEC__M 0x3 #define ATV_COMM_EXEC__PRE 0x0 #define ATV_COMM_EXEC_STOP 0x0 #define ATV_COMM_EXEC_ACTIVE 0x1 #define ATV_COMM_EXEC_HOLD 0x2 #define ATV_COMM_STATE__A 0xC00001 #define ATV_COMM_STATE__W 16 #define ATV_COMM_STATE__M 0xFFFF #define ATV_COMM_STATE__PRE 0x0 #define ATV_COMM_MB__A 0xC00002 #define ATV_COMM_MB__W 16 #define ATV_COMM_MB__M 0xFFFF #define ATV_COMM_MB__PRE 0x0 #define ATV_COMM_INT_REQ__A 0xC00003 #define ATV_COMM_INT_REQ__W 16 #define ATV_COMM_INT_REQ__M 0xFFFF #define ATV_COMM_INT_REQ__PRE 0x0 #define ATV_COMM_INT_REQ_COMM_INT_REQ__B 0 #define ATV_COMM_INT_REQ_COMM_INT_REQ__W 1 #define ATV_COMM_INT_REQ_COMM_INT_REQ__M 0x1 #define ATV_COMM_INT_REQ_COMM_INT_REQ__PRE 0x0 #define ATV_COMM_INT_STA__A 0xC00005 #define ATV_COMM_INT_STA__W 16 #define ATV_COMM_INT_STA__M 0xFFFF #define ATV_COMM_INT_STA__PRE 0x0 #define ATV_COMM_INT_MSK__A 0xC00006 #define ATV_COMM_INT_MSK__W 16 #define ATV_COMM_INT_MSK__M 0xFFFF #define ATV_COMM_INT_MSK__PRE 0x0 #define ATV_COMM_INT_STM__A 0xC00007 #define ATV_COMM_INT_STM__W 16 #define ATV_COMM_INT_STM__M 0xFFFF #define ATV_COMM_INT_STM__PRE 0x0 #define ATV_COMM_KEY__A 0xC0000F #define ATV_COMM_KEY__W 16 #define ATV_COMM_KEY__M 0xFFFF #define ATV_COMM_KEY__PRE 0x0 #define ATV_COMM_KEY_KEY 0xFABA #define ATV_COMM_KEY_MIN 0x0 #define ATV_COMM_KEY_MAX 0xFFFF #define ATV_TOP_COMM_EXEC__A 0xC10000 #define ATV_TOP_COMM_EXEC__W 2 #define ATV_TOP_COMM_EXEC__M 0x3 #define ATV_TOP_COMM_EXEC__PRE 0x0 #define ATV_TOP_COMM_EXEC_STOP 0x0 #define ATV_TOP_COMM_EXEC_ACTIVE 0x1 #define ATV_TOP_COMM_EXEC_HOLD 0x2 #define ATV_TOP_COMM_STATE__A 0xC10001 #define ATV_TOP_COMM_STATE__W 16 #define ATV_TOP_COMM_STATE__M 0xFFFF #define ATV_TOP_COMM_STATE__PRE 0x0 #define ATV_TOP_COMM_STATE_STATE__B 0 #define ATV_TOP_COMM_STATE_STATE__W 16 #define ATV_TOP_COMM_STATE_STATE__M 0xFFFF #define ATV_TOP_COMM_STATE_STATE__PRE 0x0 #define ATV_TOP_COMM_MB__A 0xC10002 #define ATV_TOP_COMM_MB__W 16 #define ATV_TOP_COMM_MB__M 0xFFFF #define ATV_TOP_COMM_MB__PRE 0x0 #define ATV_TOP_COMM_MB_CTL__B 0 #define ATV_TOP_COMM_MB_CTL__W 1 #define ATV_TOP_COMM_MB_CTL__M 0x1 #define ATV_TOP_COMM_MB_CTL__PRE 0x0 #define ATV_TOP_COMM_MB_OBS__B 1 #define ATV_TOP_COMM_MB_OBS__W 1 #define ATV_TOP_COMM_MB_OBS__M 0x2 #define ATV_TOP_COMM_MB_OBS__PRE 0x0 #define ATV_TOP_COMM_MB_MUX_CTRL__B 2 #define ATV_TOP_COMM_MB_MUX_CTRL__W 4 #define ATV_TOP_COMM_MB_MUX_CTRL__M 0x3C #define ATV_TOP_COMM_MB_MUX_CTRL__PRE 0x0 #define ATV_TOP_COMM_MB_MUX_CTRL_PEAK_S 0x0 #define ATV_TOP_COMM_MB_MUX_CTRL_VID_GAIN 0x4 #define ATV_TOP_COMM_MB_MUX_CTRL_CORR_O 0x8 #define ATV_TOP_COMM_MB_MUX_CTRL_CR_ROT_O 0xC #define ATV_TOP_COMM_MB_MUX_CTRL_CR_IIR_IQ 0x10 #define ATV_TOP_COMM_MB_MUX_CTRL_VIDEO_O 0x14 #define ATV_TOP_COMM_MB_MUX_CTRL_SIF_O 0x18 #define ATV_TOP_COMM_MB_MUX_CTRL_SIF2025_O 0x1C #define ATV_TOP_COMM_MB_MUX_CTRL_POST_S 0x20 #define ATV_TOP_COMM_MB_MUX_OBS__B 6 #define ATV_TOP_COMM_MB_MUX_OBS__W 4 #define ATV_TOP_COMM_MB_MUX_OBS__M 0x3C0 #define ATV_TOP_COMM_MB_MUX_OBS__PRE 0x0 #define ATV_TOP_COMM_MB_MUX_OBS_PEAK_S 0x0 #define ATV_TOP_COMM_MB_MUX_OBS_VID_GAIN 0x40 #define ATV_TOP_COMM_MB_MUX_OBS_CORR_O 0x80 #define ATV_TOP_COMM_MB_MUX_OBS_CR_ROT_O 0xC0 #define ATV_TOP_COMM_MB_MUX_OBS_CR_IIR_IQ 0x100 #define ATV_TOP_COMM_MB_MUX_OBS_VIDEO_O 0x140 #define ATV_TOP_COMM_MB_MUX_OBS_SIF_O 0x180 #define ATV_TOP_COMM_MB_MUX_OBS_SIF2025_O 0x1C0 #define ATV_TOP_COMM_MB_MUX_OBS_POST_S 0x200 #define ATV_TOP_COMM_INT_REQ__A 0xC10003 #define ATV_TOP_COMM_INT_REQ__W 16 #define ATV_TOP_COMM_INT_REQ__M 0xFFFF #define ATV_TOP_COMM_INT_REQ__PRE 0x0 #define ATV_TOP_COMM_INT_STA__A 0xC10005 #define ATV_TOP_COMM_INT_STA__W 16 #define ATV_TOP_COMM_INT_STA__M 0xFFFF #define ATV_TOP_COMM_INT_STA__PRE 0x0 #define ATV_TOP_COMM_INT_STA_FAGC_STA__B 0 #define ATV_TOP_COMM_INT_STA_FAGC_STA__W 1 #define ATV_TOP_COMM_INT_STA_FAGC_STA__M 0x1 #define ATV_TOP_COMM_INT_STA_FAGC_STA__PRE 0x0 #define ATV_TOP_COMM_INT_STA_OVM_STA__B 1 #define ATV_TOP_COMM_INT_STA_OVM_STA__W 1 #define ATV_TOP_COMM_INT_STA_OVM_STA__M 0x2 #define ATV_TOP_COMM_INT_STA_OVM_STA__PRE 0x0 #define ATV_TOP_COMM_INT_STA_AMPTH_STA__B 2 #define ATV_TOP_COMM_INT_STA_AMPTH_STA__W 1 #define ATV_TOP_COMM_INT_STA_AMPTH_STA__M 0x4 #define ATV_TOP_COMM_INT_STA_AMPTH_STA__PRE 0x0 #define ATV_TOP_COMM_INT_MSK__A 0xC10006 #define ATV_TOP_COMM_INT_MSK__W 16 #define ATV_TOP_COMM_INT_MSK__M 0xFFFF #define ATV_TOP_COMM_INT_MSK__PRE 0x0 #define ATV_TOP_COMM_INT_MSK_FAGC_MSK__B 0 #define ATV_TOP_COMM_INT_MSK_FAGC_MSK__W 1 #define ATV_TOP_COMM_INT_MSK_FAGC_MSK__M 0x1 #define ATV_TOP_COMM_INT_MSK_FAGC_MSK__PRE 0x0 #define ATV_TOP_COMM_INT_MSK_OVM_MSK__B 1 #define ATV_TOP_COMM_INT_MSK_OVM_MSK__W 1 #define ATV_TOP_COMM_INT_MSK_OVM_MSK__M 0x2 #define ATV_TOP_COMM_INT_MSK_OVM_MSK__PRE 0x0 #define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__B 2 #define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__W 1 #define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__M 0x4 #define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__PRE 0x0 #define ATV_TOP_COMM_INT_STM__A 0xC10007 #define ATV_TOP_COMM_INT_STM__W 16 #define ATV_TOP_COMM_INT_STM__M 0xFFFF #define ATV_TOP_COMM_INT_STM__PRE 0x0 #define ATV_TOP_COMM_INT_STM_FAGC_STM__B 0 #define ATV_TOP_COMM_INT_STM_FAGC_STM__W 1 #define ATV_TOP_COMM_INT_STM_FAGC_STM__M 0x1 #define ATV_TOP_COMM_INT_STM_FAGC_STM__PRE 0x0 #define ATV_TOP_COMM_INT_STM_OVM_STM__B 1 #define ATV_TOP_COMM_INT_STM_OVM_STM__W 1 #define ATV_TOP_COMM_INT_STM_OVM_STM__M 0x2 #define ATV_TOP_COMM_INT_STM_OVM_STM__PRE 0x0 #define ATV_TOP_COMM_INT_STM_AMPTH_STM__B 2 #define ATV_TOP_COMM_INT_STM_AMPTH_STM__W 1 #define ATV_TOP_COMM_INT_STM_AMPTH_STM__M 0x4 #define ATV_TOP_COMM_INT_STM_AMPTH_STM__PRE 0x0 #define ATV_TOP_COMM_KEY__A 0xC1000F #define ATV_TOP_COMM_KEY__W 16 #define ATV_TOP_COMM_KEY__M 0xFFFF #define ATV_TOP_COMM_KEY__PRE 0x0 #define ATV_TOP_COMM_KEY_KEY__B 0 #define ATV_TOP_COMM_KEY_KEY__W 16 #define ATV_TOP_COMM_KEY_KEY__M 0xFFFF #define ATV_TOP_COMM_KEY_KEY__PRE 0x0 #define ATV_TOP_COMM_KEY_KEY_KEY 0xFABA #define ATV_TOP_COMM_KEY_KEY_MIN 0x0 #define ATV_TOP_COMM_KEY_KEY_MAX 0xFFFF #define ATV_TOP_CR_AMP_TH__A 0xC10010 #define ATV_TOP_CR_AMP_TH__W 8 #define ATV_TOP_CR_AMP_TH__M 0xFF #define ATV_TOP_CR_AMP_TH__PRE 0x8 #define ATV_TOP_CR_AMP_TH_MN 0x8 #define ATV_TOP_CR_CONT__A 0xC10011 #define ATV_TOP_CR_CONT__W 9 #define ATV_TOP_CR_CONT__M 0x1FF #define ATV_TOP_CR_CONT__PRE 0x9C #define ATV_TOP_CR_CONT_CR_P__B 0 #define ATV_TOP_CR_CONT_CR_P__W 3 #define ATV_TOP_CR_CONT_CR_P__M 0x7 #define ATV_TOP_CR_CONT_CR_P__PRE 0x4 #define ATV_TOP_CR_CONT_CR_P_MN 0x4 #define ATV_TOP_CR_CONT_CR_P_FM 0x0 #define ATV_TOP_CR_CONT_CR_D__B 3 #define ATV_TOP_CR_CONT_CR_D__W 3 #define ATV_TOP_CR_CONT_CR_D__M 0x38 #define ATV_TOP_CR_CONT_CR_D__PRE 0x18 #define ATV_TOP_CR_CONT_CR_D_MN 0x18 #define ATV_TOP_CR_CONT_CR_D_FM 0x0 #define ATV_TOP_CR_CONT_CR_I__B 6 #define ATV_TOP_CR_CONT_CR_I__W 3 #define ATV_TOP_CR_CONT_CR_I__M 0x1C0 #define ATV_TOP_CR_CONT_CR_I__PRE 0x80 #define ATV_TOP_CR_CONT_CR_I_MN 0x80 #define ATV_TOP_CR_CONT_CR_I_FM 0x0 #define ATV_TOP_CR_OVM_TH__A 0xC10012 #define ATV_TOP_CR_OVM_TH__W 8 #define ATV_TOP_CR_OVM_TH__M 0xFF #define ATV_TOP_CR_OVM_TH__PRE 0xA0 #define ATV_TOP_CR_OVM_TH_MN 0xA0 #define ATV_TOP_CR_OVM_TH_FM 0x0 #define ATV_TOP_NOISE_TH__A 0xC10013 #define ATV_TOP_NOISE_TH__W 4 #define ATV_TOP_NOISE_TH__M 0xF #define ATV_TOP_NOISE_TH__PRE 0x8 #define ATV_TOP_NOISE_TH_MN 0x8 #define ATV_TOP_EQU0__A 0xC10014 #define ATV_TOP_EQU0__W 9 #define ATV_TOP_EQU0__M 0x1FF #define ATV_TOP_EQU0__PRE 0x1FB #define ATV_TOP_EQU0_EQU_C0__B 0 #define ATV_TOP_EQU0_EQU_C0__W 9 #define ATV_TOP_EQU0_EQU_C0__M 0x1FF #define ATV_TOP_EQU0_EQU_C0__PRE 0x1FB #define ATV_TOP_EQU0_EQU_C0_MN 0xFB #define ATV_TOP_EQU1__A 0xC10015 #define ATV_TOP_EQU1__W 9 #define ATV_TOP_EQU1__M 0x1FF #define ATV_TOP_EQU1__PRE 0x1CE #define ATV_TOP_EQU1_EQU_C1__B 0 #define ATV_TOP_EQU1_EQU_C1__W 9 #define ATV_TOP_EQU1_EQU_C1__M 0x1FF #define ATV_TOP_EQU1_EQU_C1__PRE 0x1CE #define ATV_TOP_EQU1_EQU_C1_MN 0xCE #define ATV_TOP_EQU2__A 0xC10016 #define ATV_TOP_EQU2__W 9 #define ATV_TOP_EQU2__M 0x1FF #define ATV_TOP_EQU2__PRE 0xD2 #define ATV_TOP_EQU2_EQU_C2__B 0 #define ATV_TOP_EQU2_EQU_C2__W 9 #define ATV_TOP_EQU2_EQU_C2__M 0x1FF #define ATV_TOP_EQU2_EQU_C2__PRE 0xD2 #define ATV_TOP_EQU2_EQU_C2_MN 0xD2 #define ATV_TOP_EQU3__A 0xC10017 #define ATV_TOP_EQU3__W 9 #define ATV_TOP_EQU3__M 0x1FF #define ATV_TOP_EQU3__PRE 0x160 #define ATV_TOP_EQU3_EQU_C3__B 0 #define ATV_TOP_EQU3_EQU_C3__W 9 #define ATV_TOP_EQU3_EQU_C3__M 0x1FF #define ATV_TOP_EQU3_EQU_C3__PRE 0x160 #define ATV_TOP_EQU3_EQU_C3_MN 0x60 #define ATV_TOP_ROT_MODE__A 0xC10018 #define ATV_TOP_ROT_MODE__W 1 #define ATV_TOP_ROT_MODE__M 0x1 #define ATV_TOP_ROT_MODE__PRE 0x0 #define ATV_TOP_ROT_MODE_AMPTH_DEPEND 0x0 #define ATV_TOP_ROT_MODE_ALWAYS 0x1 #define ATV_TOP_MOD_CONTROL__A 0xC10019 #define ATV_TOP_MOD_CONTROL__W 12 #define ATV_TOP_MOD_CONTROL__M 0xFFF #define ATV_TOP_MOD_CONTROL__PRE 0x5B1 #define ATV_TOP_MOD_CONTROL_MOD_IR__B 0 #define ATV_TOP_MOD_CONTROL_MOD_IR__W 3 #define ATV_TOP_MOD_CONTROL_MOD_IR__M 0x7 #define ATV_TOP_MOD_CONTROL_MOD_IR__PRE 0x1 #define ATV_TOP_MOD_CONTROL_MOD_IR_MN 0x1 #define ATV_TOP_MOD_CONTROL_MOD_IR_FM 0x0 #define ATV_TOP_MOD_CONTROL_MOD_IF__B 3 #define ATV_TOP_MOD_CONTROL_MOD_IF__W 4 #define ATV_TOP_MOD_CONTROL_MOD_IF__M 0x78 #define ATV_TOP_MOD_CONTROL_MOD_IF__PRE 0x30 #define ATV_TOP_MOD_CONTROL_MOD_IF_MN 0x30 #define ATV_TOP_MOD_CONTROL_MOD_IF_FM 0x0 #define ATV_TOP_MOD_CONTROL_MOD_MODE__B 7 #define ATV_TOP_MOD_CONTROL_MOD_MODE__W 1 #define ATV_TOP_MOD_CONTROL_MOD_MODE__M 0x80 #define ATV_TOP_MOD_CONTROL_MOD_MODE__PRE 0x80 #define ATV_TOP_MOD_CONTROL_MOD_MODE_RISE 0x0 #define ATV_TOP_MOD_CONTROL_MOD_MODE_RISE_FALL 0x80 #define ATV_TOP_MOD_CONTROL_MOD_TH__B 8 #define ATV_TOP_MOD_CONTROL_MOD_TH__W 4 #define ATV_TOP_MOD_CONTROL_MOD_TH__M 0xF00 #define ATV_TOP_MOD_CONTROL_MOD_TH__PRE 0x500 #define ATV_TOP_MOD_CONTROL_MOD_TH_MN 0x500 #define ATV_TOP_MOD_CONTROL_MOD_TH_FM 0x0 #define ATV_TOP_STD__A 0xC1001A #define ATV_TOP_STD__W 2 #define ATV_TOP_STD__M 0x3 #define ATV_TOP_STD__PRE 0x0 #define ATV_TOP_STD_MODE__B 0 #define ATV_TOP_STD_MODE__W 1 #define ATV_TOP_STD_MODE__M 0x1 #define ATV_TOP_STD_MODE__PRE 0x0 #define ATV_TOP_STD_MODE_MN 0x0 #define ATV_TOP_STD_MODE_FM 0x1 #define ATV_TOP_STD_VID_POL__B 1 #define ATV_TOP_STD_VID_POL__W 1 #define ATV_TOP_STD_VID_POL__M 0x2 #define ATV_TOP_STD_VID_POL__PRE 0x0 #define ATV_TOP_STD_VID_POL_NEG 0x0 #define ATV_TOP_STD_VID_POL_POS 0x2 #define ATV_TOP_VID_AMP__A 0xC1001B #define ATV_TOP_VID_AMP__W 12 #define ATV_TOP_VID_AMP__M 0xFFF #define ATV_TOP_VID_AMP__PRE 0x380 #define ATV_TOP_VID_AMP_MN 0x380 #define ATV_TOP_VID_AMP_FM 0x0 #define ATV_TOP_VID_PEAK__A 0xC1001C #define ATV_TOP_VID_PEAK__W 5 #define ATV_TOP_VID_PEAK__M 0x1F #define ATV_TOP_VID_PEAK__PRE 0x1 #define ATV_TOP_FAGC_TH__A 0xC1001D #define ATV_TOP_FAGC_TH__W 11 #define ATV_TOP_FAGC_TH__M 0x7FF #define ATV_TOP_FAGC_TH__PRE 0x2B2 #define ATV_TOP_FAGC_TH_MN 0x2B2 #define ATV_TOP_SYNC_SLICE__A 0xC1001E #define ATV_TOP_SYNC_SLICE__W 11 #define ATV_TOP_SYNC_SLICE__M 0x7FF #define ATV_TOP_SYNC_SLICE__PRE 0x243 #define ATV_TOP_SYNC_SLICE_MN 0x243 #define ATV_TOP_SIF_GAIN__A 0xC1001F #define ATV_TOP_SIF_GAIN__W 11 #define ATV_TOP_SIF_GAIN__M 0x7FF #define ATV_TOP_SIF_GAIN__PRE 0x0 #define ATV_TOP_SIF_TP__A 0xC10020 #define ATV_TOP_SIF_TP__W 6 #define ATV_TOP_SIF_TP__M 0x3F #define ATV_TOP_SIF_TP__PRE 0x0 #define ATV_TOP_MOD_ACCU__A 0xC10021 #define ATV_TOP_MOD_ACCU__W 10 #define ATV_TOP_MOD_ACCU__M 0x3FF #define ATV_TOP_MOD_ACCU__PRE 0x0 #define ATV_TOP_CR_FREQ__A 0xC10022 #define ATV_TOP_CR_FREQ__W 8 #define ATV_TOP_CR_FREQ__M 0xFF #define ATV_TOP_CR_FREQ__PRE 0x0 #define ATV_TOP_CR_PHAD__A 0xC10023 #define ATV_TOP_CR_PHAD__W 12 #define ATV_TOP_CR_PHAD__M 0xFFF #define ATV_TOP_CR_PHAD__PRE 0x0 #define ATV_TOP_AF_SIF_ATT__A 0xC10024 #define ATV_TOP_AF_SIF_ATT__W 2 #define ATV_TOP_AF_SIF_ATT__M 0x3 #define ATV_TOP_AF_SIF_ATT__PRE 0x0 #define ATV_TOP_AF_SIF_ATT_0DB 0x0 #define ATV_TOP_AF_SIF_ATT_M3DB 0x1 #define ATV_TOP_AF_SIF_ATT_M6DB 0x2 #define ATV_TOP_AF_SIF_ATT_M9DB 0x3 #define ATV_TOP_STDBY__A 0xC10025 #define ATV_TOP_STDBY__W 2 #define ATV_TOP_STDBY__M 0x3 #define ATV_TOP_STDBY__PRE 0x1 #define ATV_TOP_STDBY_SIF_STDBY__B 0 #define ATV_TOP_STDBY_SIF_STDBY__W 1 #define ATV_TOP_STDBY_SIF_STDBY__M 0x1 #define ATV_TOP_STDBY_SIF_STDBY__PRE 0x1 #define ATV_TOP_STDBY_SIF_STDBY_ACTIVE 0x0 #define ATV_TOP_STDBY_SIF_STDBY_STANDBY 0x1 #define ATV_TOP_STDBY_CVBS_STDBY__B 1 #define ATV_TOP_STDBY_CVBS_STDBY__W 1 #define ATV_TOP_STDBY_CVBS_STDBY__M 0x2 #define ATV_TOP_STDBY_CVBS_STDBY__PRE 0x0 #define ATV_TOP_STDBY_CVBS_STDBY_A1_ACTIVE 0x0 #define ATV_TOP_STDBY_CVBS_STDBY_A1_STANDBY 0x2 #define ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE 0x2 #define ATV_TOP_STDBY_CVBS_STDBY_A2_STANDBY 0x0 #define ATV_TOP_OVERRIDE_SFR__A 0xC10026 #define ATV_TOP_OVERRIDE_SFR__W 1 #define ATV_TOP_OVERRIDE_SFR__M 0x1 #define ATV_TOP_OVERRIDE_SFR__PRE 0x0 #define ATV_TOP_OVERRIDE_SFR_ACTIVE 0x0 #define ATV_TOP_OVERRIDE_SFR_OVERRIDE 0x1 #define ATV_TOP_SFR_VID_GAIN__A 0xC10027 #define ATV_TOP_SFR_VID_GAIN__W 16 #define ATV_TOP_SFR_VID_GAIN__M 0xFFFF #define ATV_TOP_SFR_VID_GAIN__PRE 0x0 #define ATV_TOP_SFR_AGC_RES__A 0xC10028 #define ATV_TOP_SFR_AGC_RES__W 5 #define ATV_TOP_SFR_AGC_RES__M 0x1F #define ATV_TOP_SFR_AGC_RES__PRE 0x0 #define ATV_TOP_OVM_COMP__A 0xC10029 #define ATV_TOP_OVM_COMP__W 12 #define ATV_TOP_OVM_COMP__M 0xFFF #define ATV_TOP_OVM_COMP__PRE 0x0 #define ATV_TOP_OUT_CONF__A 0xC1002A #define ATV_TOP_OUT_CONF__W 5 #define ATV_TOP_OUT_CONF__M 0x1F #define ATV_TOP_OUT_CONF__PRE 0x0 #define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__B 0 #define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__W 1 #define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__M 0x1 #define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__PRE 0x0 #define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_UNSIGNED 0x0 #define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_SIGNED 0x1 #define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__B 1 #define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__W 1 #define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__M 0x2 #define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__PRE 0x0 #define ATV_TOP_OUT_CONF_SIF_DAC_SIGN_UNSIGNED 0x0 #define ATV_TOP_OUT_CONF_SIF_DAC_SIGN_SIGNED 0x2 #define ATV_TOP_OUT_CONF_SIF20_SIGN__B 2 #define ATV_TOP_OUT_CONF_SIF20_SIGN__W 1 #define ATV_TOP_OUT_CONF_SIF20_SIGN__M 0x4 #define ATV_TOP_OUT_CONF_SIF20_SIGN__PRE 0x0 #define ATV_TOP_OUT_CONF_SIF20_SIGN_UNSIGNED 0x0 #define ATV_TOP_OUT_CONF_SIF20_SIGN_SIGNED 0x4 #define ATV_TOP_OUT_CONF_CVBS_DAC_BR__B 3 #define ATV_TOP_OUT_CONF_CVBS_DAC_BR__W 1 #define ATV_TOP_OUT_CONF_CVBS_DAC_BR__M 0x8 #define ATV_TOP_OUT_CONF_CVBS_DAC_BR__PRE 0x0 #define ATV_TOP_OUT_CONF_CVBS_DAC_BR_NORMAL 0x0 #define ATV_TOP_OUT_CONF_CVBS_DAC_BR_BITREVERSED 0x8 #define ATV_TOP_OUT_CONF_SIF_DAC_BR__B 4 #define ATV_TOP_OUT_CONF_SIF_DAC_BR__W 1 #define ATV_TOP_OUT_CONF_SIF_DAC_BR__M 0x10 #define ATV_TOP_OUT_CONF_SIF_DAC_BR__PRE 0x0 #define ATV_TOP_OUT_CONF_SIF_DAC_BR_NORMAL 0x0 #define ATV_TOP_OUT_CONF_SIF_DAC_BR_BITREVERSED 0x10 #define ATV_AFT_COMM_EXEC__A 0xFF0000 #define ATV_AFT_COMM_EXEC__W 2 #define ATV_AFT_COMM_EXEC__M 0x3 #define ATV_AFT_COMM_EXEC__PRE 0x0 #define ATV_AFT_COMM_EXEC_STOP 0x0 #define ATV_AFT_COMM_EXEC_ACTIVE 0x1 #define ATV_AFT_COMM_EXEC_HOLD 0x2 #define ATV_AFT_TST__A 0xFF0010 #define ATV_AFT_TST__W 4 #define ATV_AFT_TST__M 0xF #define ATV_AFT_TST__PRE 0x0 #define AUD_COMM_EXEC__A 0x1000000 #define AUD_COMM_EXEC__W 2 #define AUD_COMM_EXEC__M 0x3 #define AUD_COMM_EXEC__PRE 0x0 #define AUD_COMM_EXEC_STOP 0x0 #define AUD_COMM_EXEC_ACTIVE 0x1 #define AUD_COMM_MB__A 0x1000002 #define AUD_COMM_MB__W 16 #define AUD_COMM_MB__M 0xFFFF #define AUD_COMM_MB__PRE 0x0 #define AUD_TOP_COMM_EXEC__A 0x1010000 #define AUD_TOP_COMM_EXEC__W 2 #define AUD_TOP_COMM_EXEC__M 0x3 #define AUD_TOP_COMM_EXEC__PRE 0x0 #define AUD_TOP_COMM_EXEC_STOP 0x0 #define AUD_TOP_COMM_EXEC_ACTIVE 0x1 #define AUD_TOP_COMM_MB__A 0x1010002 #define AUD_TOP_COMM_MB__W 16 #define AUD_TOP_COMM_MB__M 0xFFFF #define AUD_TOP_COMM_MB__PRE 0x0 #define AUD_TOP_COMM_MB_CTL__B 0 #define AUD_TOP_COMM_MB_CTL__W 1 #define AUD_TOP_COMM_MB_CTL__M 0x1 #define AUD_TOP_COMM_MB_CTL__PRE 0x0 #define AUD_TOP_COMM_MB_CTL_CTR_OFF 0x0 #define AUD_TOP_COMM_MB_CTL_CTR_ON 0x1 #define AUD_TOP_COMM_MB_OBS__B 1 #define AUD_TOP_COMM_MB_OBS__W 1 #define AUD_TOP_COMM_MB_OBS__M 0x2 #define AUD_TOP_COMM_MB_OBS__PRE 0x0 #define AUD_TOP_COMM_MB_OBS_OBS_OFF 0x0 #define AUD_TOP_COMM_MB_OBS_OBS_ON 0x2 #define AUD_TOP_COMM_MB_MUX_CTRL__B 2 #define AUD_TOP_COMM_MB_MUX_CTRL__W 4 #define AUD_TOP_COMM_MB_MUX_CTRL__M 0x3C #define AUD_TOP_COMM_MB_MUX_CTRL__PRE 0x0 #define AUD_TOP_COMM_MB_MUX_CTRL_DEMOD_TBO 0x0 #define AUD_TOP_COMM_MB_MUX_CTRL_XDFP_IRQS 0x4 #define AUD_TOP_COMM_MB_MUX_CTRL_OBSERVEPC 0x8 #define AUD_TOP_COMM_MB_MUX_CTRL_SAOUT 0xC #define AUD_TOP_COMM_MB_MUX_CTRL_XDFP_SCHEQ 0x10 #define AUD_TOP_COMM_MB_MUX_OBS__B 6 #define AUD_TOP_COMM_MB_MUX_OBS__W 4 #define AUD_TOP_COMM_MB_MUX_OBS__M 0x3C0 #define AUD_TOP_COMM_MB_MUX_OBS__PRE 0x0 #define AUD_TOP_COMM_MB_MUX_OBS_DEMOD_TBO 0x0 #define AUD_TOP_COMM_MB_MUX_OBS_XDFP_IRQS 0x40 #define AUD_TOP_COMM_MB_MUX_OBS_OBSERVEPC 0x80 #define AUD_TOP_COMM_MB_MUX_OBS_SAOUT 0xC0 #define AUD_TOP_COMM_MB_MUX_OBS_XDFP_SCHEQ 0x100 #define AUD_TOP_TR_MDE__A 0x1010010 #define AUD_TOP_TR_MDE__W 5 #define AUD_TOP_TR_MDE__M 0x1F #define AUD_TOP_TR_MDE__PRE 0x18 #define AUD_TOP_TR_MDE_FIFO_SIZE__B 0 #define AUD_TOP_TR_MDE_FIFO_SIZE__W 4 #define AUD_TOP_TR_MDE_FIFO_SIZE__M 0xF #define AUD_TOP_TR_MDE_FIFO_SIZE__PRE 0x8 #define AUD_TOP_TR_MDE_RD_LOCK__B 4 #define AUD_TOP_TR_MDE_RD_LOCK__W 1 #define AUD_TOP_TR_MDE_RD_LOCK__M 0x10 #define AUD_TOP_TR_MDE_RD_LOCK__PRE 0x10 #define AUD_TOP_TR_MDE_RD_LOCK_NORMAL 0x0 #define AUD_TOP_TR_MDE_RD_LOCK_LOCK 0x10 #define AUD_TOP_TR_CTR__A 0x1010011 #define AUD_TOP_TR_CTR__W 4 #define AUD_TOP_TR_CTR__M 0xF #define AUD_TOP_TR_CTR__PRE 0x0 #define AUD_TOP_TR_CTR_FIFO_RD_RDY__B 0 #define AUD_TOP_TR_CTR_FIFO_RD_RDY__W 1 #define AUD_TOP_TR_CTR_FIFO_RD_RDY__M 0x1 #define AUD_TOP_TR_CTR_FIFO_RD_RDY__PRE 0x0 #define AUD_TOP_TR_CTR_FIFO_RD_RDY_NOT_READY 0x0 #define AUD_TOP_TR_CTR_FIFO_RD_RDY_READY 0x1 #define AUD_TOP_TR_CTR_FIFO_EMPTY__B 1 #define AUD_TOP_TR_CTR_FIFO_EMPTY__W 1 #define AUD_TOP_TR_CTR_FIFO_EMPTY__M 0x2 #define AUD_TOP_TR_CTR_FIFO_EMPTY__PRE 0x0 #define AUD_TOP_TR_CTR_FIFO_EMPTY_NOT_EMPTY 0x0 #define AUD_TOP_TR_CTR_FIFO_EMPTY_EMPTY 0x2 #define AUD_TOP_TR_CTR_FIFO_LOCK__B 2 #define AUD_TOP_TR_CTR_FIFO_LOCK__W 1 #define AUD_TOP_TR_CTR_FIFO_LOCK__M 0x4 #define AUD_TOP_TR_CTR_FIFO_LOCK__PRE 0x0 #define AUD_TOP_TR_CTR_FIFO_LOCK_UNLOCKED 0x0 #define AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED 0x4 #define AUD_TOP_TR_CTR_FIFO_FULL__B 3 #define AUD_TOP_TR_CTR_FIFO_FULL__W 1 #define AUD_TOP_TR_CTR_FIFO_FULL__M 0x8 #define AUD_TOP_TR_CTR_FIFO_FULL__PRE 0x0 #define AUD_TOP_TR_CTR_FIFO_FULL_EMPTY 0x0 #define AUD_TOP_TR_CTR_FIFO_FULL_FULL 0x8 #define AUD_TOP_TR_RD_REG__A 0x1010012 #define AUD_TOP_TR_RD_REG__W 16 #define AUD_TOP_TR_RD_REG__M 0xFFFF #define AUD_TOP_TR_RD_REG__PRE 0x0 #define AUD_TOP_TR_RD_REG_RESULT__B 0 #define AUD_TOP_TR_RD_REG_RESULT__W 16 #define AUD_TOP_TR_RD_REG_RESULT__M 0xFFFF #define AUD_TOP_TR_RD_REG_RESULT__PRE 0x0 #define AUD_TOP_TR_TIMER__A 0x1010013 #define AUD_TOP_TR_TIMER__W 16 #define AUD_TOP_TR_TIMER__M 0xFFFF #define AUD_TOP_TR_TIMER__PRE 0x0 #define AUD_TOP_TR_TIMER_CYCLES__B 0 #define AUD_TOP_TR_TIMER_CYCLES__W 16 #define AUD_TOP_TR_TIMER_CYCLES__M 0xFFFF #define AUD_TOP_TR_TIMER_CYCLES__PRE 0x0 #define AUD_TOP_DEMOD_TBO_SEL__A 0x1010014 #define AUD_TOP_DEMOD_TBO_SEL__W 5 #define AUD_TOP_DEMOD_TBO_SEL__M 0x1F #define AUD_TOP_DEMOD_TBO_SEL__PRE 0x0 #define AUD_DEM_WR_MODUS__A 0x1030030 #define AUD_DEM_WR_MODUS__W 16 #define AUD_DEM_WR_MODUS__M 0xFFFF #define AUD_DEM_WR_MODUS__PRE 0x0 #define AUD_DEM_WR_MODUS_MOD_ASS__B 0 #define AUD_DEM_WR_MODUS_MOD_ASS__W 1 #define AUD_DEM_WR_MODUS_MOD_ASS__M 0x1 #define AUD_DEM_WR_MODUS_MOD_ASS__PRE 0x0 #define AUD_DEM_WR_MODUS_MOD_ASS_OFF 0x0 #define AUD_DEM_WR_MODUS_MOD_ASS_ON 0x1 #define AUD_DEM_WR_MODUS_MOD_STATINTERR__B 1 #define AUD_DEM_WR_MODUS_MOD_STATINTERR__W 1 #define AUD_DEM_WR_MODUS_MOD_STATINTERR__M 0x2 #define AUD_DEM_WR_MODUS_MOD_STATINTERR__PRE 0x0 #define AUD_DEM_WR_MODUS_MOD_STATINTERR_DISABLE 0x0 #define AUD_DEM_WR_MODUS_MOD_STATINTERR_ENABLE 0x2 #define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__B 2 #define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__W 1 #define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M 0x4 #define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__PRE 0x0 #define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED 0x0 #define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED 0x4 #define AUD_DEM_WR_MODUS_MOD_HDEV_A__B 8 #define AUD_DEM_WR_MODUS_MOD_HDEV_A__W 1 #define AUD_DEM_WR_MODUS_MOD_HDEV_A__M 0x100 #define AUD_DEM_WR_MODUS_MOD_HDEV_A__PRE 0x0 #define AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL 0x0 #define AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION 0x100 #define AUD_DEM_WR_MODUS_MOD_CM_A__B 9 #define AUD_DEM_WR_MODUS_MOD_CM_A__W 1 #define AUD_DEM_WR_MODUS_MOD_CM_A__M 0x200 #define AUD_DEM_WR_MODUS_MOD_CM_A__PRE 0x0 #define AUD_DEM_WR_MODUS_MOD_CM_A_MUTE 0x0 #define AUD_DEM_WR_MODUS_MOD_CM_A_NOISE 0x200 #define AUD_DEM_WR_MODUS_MOD_CM_B__B 10 #define AUD_DEM_WR_MODUS_MOD_CM_B__W 1 #define AUD_DEM_WR_MODUS_MOD_CM_B__M 0x400 #define AUD_DEM_WR_MODUS_MOD_CM_B__PRE 0x0 #define AUD_DEM_WR_MODUS_MOD_CM_B_MUTE 0x0 #define AUD_DEM_WR_MODUS_MOD_CM_B_NOISE 0x400 #define AUD_DEM_WR_MODUS_MOD_FMRADIO__B 11 #define AUD_DEM_WR_MODUS_MOD_FMRADIO__W 1 #define AUD_DEM_WR_MODUS_MOD_FMRADIO__M 0x800 #define AUD_DEM_WR_MODUS_MOD_FMRADIO__PRE 0x0 #define AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U 0x0 #define AUD_DEM_WR_MODUS_MOD_FMRADIO_EU_50U 0x800 #define AUD_DEM_WR_MODUS_MOD_6_5MHZ__B 12 #define AUD_DEM_WR_MODUS_MOD_6_5MHZ__W 1 #define AUD_DEM_WR_MODUS_MOD_6_5MHZ__M 0x1000 #define AUD_DEM_WR_MODUS_MOD_6_5MHZ__PRE 0x0 #define AUD_DEM_WR_MODUS_MOD_6_5MHZ_SECAM 0x0 #define AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K 0x1000 #define AUD_DEM_WR_MODUS_MOD_4_5MHZ__B 13 #define AUD_DEM_WR_MODUS_MOD_4_5MHZ__W 2 #define AUD_DEM_WR_MODUS_MOD_4_5MHZ__M 0x6000 #define AUD_DEM_WR_MODUS_MOD_4_5MHZ__PRE 0x0 #define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_KOREA 0x0 #define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC 0x2000 #define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_EIAJ 0x4000 #define AUD_DEM_WR_MODUS_MOD_4_5MHZ_CHROMA 0x6000 #define AUD_DEM_WR_MODUS_MOD_BTSC__B 15 #define AUD_DEM_WR_MODUS_MOD_BTSC__W 1 #define AUD_DEM_WR_MODUS_MOD_BTSC__M 0x8000 #define AUD_DEM_WR_MODUS_MOD_BTSC__PRE 0x0 #define AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO 0x0 #define AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP 0x8000 #define AUD_DEM_WR_STANDARD_SEL__A 0x1030020 #define AUD_DEM_WR_STANDARD_SEL__W 16 #define AUD_DEM_WR_STANDARD_SEL__M 0xFFFF #define AUD_DEM_WR_STANDARD_SEL__PRE 0x0 #define AUD_DEM_WR_STANDARD_SEL_STD_SEL__B 0 #define AUD_DEM_WR_STANDARD_SEL_STD_SEL__W 12 #define AUD_DEM_WR_STANDARD_SEL_STD_SEL__M 0xFFF #define AUD_DEM_WR_STANDARD_SEL_STD_SEL__PRE 0x0 #define AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO 0x1 #define AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA 0x2 #define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_FM 0x3 #define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K1 0x4 #define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K2 0x5 #define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K3 0x7 #define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_NICAM_FM 0x8 #define AUD_DEM_WR_STANDARD_SEL_STD_SEL_L_NICAM_AM 0x9 #define AUD_DEM_WR_STANDARD_SEL_STD_SEL_I_NICAM_FM 0xA #define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K_NICAM_FM 0xB #define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_STEREO 0x20 #define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_SAP 0x21 #define AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J 0x30 #define AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO 0x40 #define AUD_DEM_RD_STANDARD_RES__A 0x102007E #define AUD_DEM_RD_STANDARD_RES__W 16 #define AUD_DEM_RD_STANDARD_RES__M 0xFFFF #define AUD_DEM_RD_STANDARD_RES__PRE 0x0 #define AUD_DEM_RD_STANDARD_RES_STD_RESULT__B 0 #define AUD_DEM_RD_STANDARD_RES_STD_RESULT__W 16 #define AUD_DEM_RD_STANDARD_RES_STD_RESULT__M 0xFFFF #define AUD_DEM_RD_STANDARD_RES_STD_RESULT__PRE 0x0 #define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NO_SOUND_STANDARD 0x0 #define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_M_DUAL_CARRIER_FM 0x2 #define AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_DUAL_CARRIER_FM 0x3 #define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K1_DUAL_CARRIER_FM 0x4 #define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K2_DUAL_CARRIER_FM 0x5 #define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K3_DUAL_CARRIER_FM 0x7 #define AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_NICAM_FM 0x8 #define AUD_DEM_RD_STANDARD_RES_STD_RESULT_L_NICAM_AM 0x9 #define AUD_DEM_RD_STANDARD_RES_STD_RESULT_I_NICAM_FM 0xA #define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K_NICAM_FM 0xB #define AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_STEREO 0x20 #define AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_MONO_SAP 0x21 #define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_EIA_J 0x30 #define AUD_DEM_RD_STANDARD_RES_STD_RESULT_FM_RADIO 0x40 #define AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE 0x7FF #define AUD_DEM_RD_STATUS__A 0x1020200 #define AUD_DEM_RD_STATUS__W 16 #define AUD_DEM_RD_STATUS__M 0xFFFF #define AUD_DEM_RD_STATUS__PRE 0x0 #define AUD_DEM_RD_STATUS_STAT_NEW_RDS__B 0 #define AUD_DEM_RD_STATUS_STAT_NEW_RDS__W 1 #define AUD_DEM_RD_STATUS_STAT_NEW_RDS__M 0x1 #define AUD_DEM_RD_STATUS_STAT_NEW_RDS__PRE 0x0 #define AUD_DEM_RD_STATUS_STAT_NEW_RDS_NO_RDS_DATA 0x0 #define AUD_DEM_RD_STATUS_STAT_NEW_RDS_NEW_RDS_DATA 0x1 #define AUD_DEM_RD_STATUS_STAT_CARR_A__B 1 #define AUD_DEM_RD_STATUS_STAT_CARR_A__W 1 #define AUD_DEM_RD_STATUS_STAT_CARR_A__M 0x2 #define AUD_DEM_RD_STATUS_STAT_CARR_A__PRE 0x0 #define AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED 0x0 #define AUD_DEM_RD_STATUS_STAT_CARR_A_NOT_DETECTED 0x2 #define AUD_DEM_RD_STATUS_STAT_CARR_B__B 2 #define AUD_DEM_RD_STATUS_STAT_CARR_B__W 1 #define AUD_DEM_RD_STATUS_STAT_CARR_B__M 0x4 #define AUD_DEM_RD_STATUS_STAT_CARR_B__PRE 0x0 #define AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED 0x0 #define AUD_DEM_RD_STATUS_STAT_CARR_B_NOT_DETECTED 0x4 #define AUD_DEM_RD_STATUS_STAT_NICAM__B 5 #define AUD_DEM_RD_STATUS_STAT_NICAM__W 1 #define AUD_DEM_RD_STATUS_STAT_NICAM__M 0x20 #define AUD_DEM_RD_STATUS_STAT_NICAM__PRE 0x0 #define AUD_DEM_RD_STATUS_STAT_NICAM_NO_NICAM 0x0 #define AUD_DEM_RD_STATUS_STAT_NICAM_NICAM_DETECTED 0x20 #define AUD_DEM_RD_STATUS_STAT_STEREO__B 6 #define AUD_DEM_RD_STATUS_STAT_STEREO__W 1 #define AUD_DEM_RD_STATUS_STAT_STEREO__M 0x40 #define AUD_DEM_RD_STATUS_STAT_STEREO__PRE 0x0 #define AUD_DEM_RD_STATUS_STAT_STEREO_NO_STEREO 0x0 #define AUD_DEM_RD_STATUS_STAT_STEREO_STEREO 0x40 #define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__B 7 #define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__W 1 #define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__M 0x80 #define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__PRE 0x0 #define AUD_DEM_RD_STATUS_STAT_INDEP_MONO_DEPENDENT_FM_MONO_PROGRAM 0x0 #define AUD_DEM_RD_STATUS_STAT_INDEP_MONO_INDEPENDENT_FM_MONO_PROGRAM 0x80 #define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__B 8 #define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__W 1 #define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M 0x100 #define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__PRE 0x0 #define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_NO_SAP 0x0 #define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP 0x100 #define AUD_DEM_RD_STATUS_BAD_NICAM__B 9 #define AUD_DEM_RD_STATUS_BAD_NICAM__W 1 #define AUD_DEM_RD_STATUS_BAD_NICAM__M 0x200 #define AUD_DEM_RD_STATUS_BAD_NICAM__PRE 0x0 #define AUD_DEM_RD_STATUS_BAD_NICAM_OK 0x0 #define AUD_DEM_RD_STATUS_BAD_NICAM_BAD 0x200 #define AUD_DEM_RD_RDS_ARRAY_CNT__A 0x102020F #define AUD_DEM_RD_RDS_ARRAY_CNT__W 12 #define AUD_DEM_RD_RDS_ARRAY_CNT__M 0xFFF #define AUD_DEM_RD_RDS_ARRAY_CNT__PRE 0x0 #define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__B 0 #define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__W 12 #define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__M 0xFFF #define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__PRE 0x0 #define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID 0xFFF #define AUD_DEM_RD_RDS_DATA__A 0x1020210 #define AUD_DEM_RD_RDS_DATA__W 12 #define AUD_DEM_RD_RDS_DATA__M 0xFFF #define AUD_DEM_RD_RDS_DATA__PRE 0x0 #define AUD_DSP_WR_FM_PRESC__A 0x105000E #define AUD_DSP_WR_FM_PRESC__W 16 #define AUD_DSP_WR_FM_PRESC__M 0xFFFF #define AUD_DSP_WR_FM_PRESC__PRE 0x0 #define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B 8 #define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__W 8 #define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__M 0xFF00 #define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__PRE 0x0 #define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION 0x7F00 #define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_50_KHZ_FM_DEVIATION 0x4800 #define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_75_KHZ_FM_DEVIATION 0x3000 #define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_100_KHZ_FM_DEVIATION 0x2400 #define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_150_KHZ_FM_DEVIATION 0x1800 #define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_180_KHZ_FM_DEVIATION 0x1300 #define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_380_KHZ_FM_DEVIATION 0x900 #define AUD_DSP_WR_NICAM_PRESC__A 0x1050010 #define AUD_DSP_WR_NICAM_PRESC__W 16 #define AUD_DSP_WR_NICAM_PRESC__M 0xFFFF #define AUD_DSP_WR_NICAM_PRESC__PRE 0x0 #define AUD_DSP_WR_VOLUME__A 0x1050000 #define AUD_DSP_WR_VOLUME__W 16 #define AUD_DSP_WR_VOLUME__M 0xFFFF #define AUD_DSP_WR_VOLUME__PRE 0x0 #define AUD_DSP_WR_VOLUME_VOL_MAIN__B 8 #define AUD_DSP_WR_VOLUME_VOL_MAIN__W 8 #define AUD_DSP_WR_VOLUME_VOL_MAIN__M 0xFF00 #define AUD_DSP_WR_VOLUME_VOL_MAIN__PRE 0x0 #define AUD_DSP_WR_SRC_I2S_MATR__A 0x1050038 #define AUD_DSP_WR_SRC_I2S_MATR__W 16 #define AUD_DSP_WR_SRC_I2S_MATR__M 0xFFFF #define AUD_DSP_WR_SRC_I2S_MATR__PRE 0x0 #define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__B 8 #define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__W 8 #define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M 0xFF00 #define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__PRE 0x0 #define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO 0x0 #define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB 0x100 #define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A 0x300 #define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B 0x400 #define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__B 0 #define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__W 8 #define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M 0xFF #define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__PRE 0x0 #define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A 0x0 #define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B 0x10 #define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO 0x20 #define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO 0x30 #define AUD_DSP_WR_AVC__A 0x1050029 #define AUD_DSP_WR_AVC__W 16 #define AUD_DSP_WR_AVC__M 0xFFFF #define AUD_DSP_WR_AVC__PRE 0x0 #define AUD_DSP_WR_AVC_AVC_ON__B 14 #define AUD_DSP_WR_AVC_AVC_ON__W 2 #define AUD_DSP_WR_AVC_AVC_ON__M 0xC000 #define AUD_DSP_WR_AVC_AVC_ON__PRE 0x0 #define AUD_DSP_WR_AVC_AVC_ON_OFF 0x0 #define AUD_DSP_WR_AVC_AVC_ON_ON 0xC000 #define AUD_DSP_WR_AVC_AVC_DECAY__B 8 #define AUD_DSP_WR_AVC_AVC_DECAY__W 4 #define AUD_DSP_WR_AVC_AVC_DECAY__M 0xF00 #define AUD_DSP_WR_AVC_AVC_DECAY__PRE 0x0 #define AUD_DSP_WR_AVC_AVC_DECAY_8_SEC 0x800 #define AUD_DSP_WR_AVC_AVC_DECAY_4_SEC 0x400 #define AUD_DSP_WR_AVC_AVC_DECAY_2_SEC 0x200 #define AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC 0x100 #define AUD_DSP_WR_AVC_AVC_REF_LEV__B 4 #define AUD_DSP_WR_AVC_AVC_REF_LEV__W 4 #define AUD_DSP_WR_AVC_AVC_REF_LEV__M 0xF0 #define AUD_DSP_WR_AVC_AVC_REF_LEV__PRE 0x0 #define AUD_DSP_WR_AVC_AVC_MAX_ATT__B 2 #define AUD_DSP_WR_AVC_AVC_MAX_ATT__W 2 #define AUD_DSP_WR_AVC_AVC_MAX_ATT__M 0xC #define AUD_DSP_WR_AVC_AVC_MAX_ATT__PRE 0x0 #define AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB 0x0 #define AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB 0x4 #define AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB 0x8 #define AUD_DSP_WR_AVC_AVC_MAX_GAIN__B 0 #define AUD_DSP_WR_AVC_AVC_MAX_GAIN__W 2 #define AUD_DSP_WR_AVC_AVC_MAX_GAIN__M 0x3 #define AUD_DSP_WR_AVC_AVC_MAX_GAIN__PRE 0x0 #define AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB 0x0 #define AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB 0x1 #define AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB 0x3 #define AUD_DSP_WR_QPEAK__A 0x105000C #define AUD_DSP_WR_QPEAK__W 16 --> -------------------- --> maximum size reached --> --------------------
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2026-04-07