/* * The aspeed chip provides a single hardware interrupt for all of the I2C * busses, so we use a dummy interrupt chip to translate this single interrupt * into multiple interrupts, each associated with a single I2C bus.
*/ staticvoid aspeed_i2c_ic_irq_handler(struct irq_desc *desc)
{ struct aspeed_i2c_ic *i2c_ic = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); unsignedlong bit, status;
chained_irq_enter(chip, desc);
status = readl(i2c_ic->base);
for_each_set_bit(bit, &status, ASPEED_I2C_IC_NUM_BUS)
generic_handle_domain_irq(i2c_ic->irq_domain, bit);
chained_irq_exit(chip, desc);
}
/* * Set simple handler and mark IRQ as valid. Nothing interesting to do here * since we are using a dummy interrupt chip.
*/ staticint aspeed_i2c_ic_map_irq_domain(struct irq_domain *domain, unsignedint irq, irq_hw_number_t hwirq)
{
irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
irq_set_chip_data(irq, domain->host_data);
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