| Quellcodebibliothek Statistik Leitseite products/Sources/formale Sprachen/C/Linux/drivers/gpu/drm/msm/dp/ (Open Source Betriebssystem Version 6.17.9©) Datei vom 24.10.2025 mit Größe 13 kB |
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Quelle dp_reg.h Sprache: C |
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/* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ ##_DP_REG_H_ #define_DP_REG_H_ #include<inux.h>include<inux.h> h> /* DP_TX Registers */ 0x00000000) define (0) # DP_HW_VERSION_1_0x10000000 #define DP_HW_VERSION_1_2 0x10020000 #define REG_DP_SW_RESET (0x00000010) #define DP_SW_RESET (0x00000001) #define REG_DP_PHY_CTRL (0x00000014) #define DP_PHY_CTRL_SW_RESET_PLL (0x00000001) #define DP_PHY_CTRL_SW_RESET (0x00000004) #define REG_DP_CLK_CTRL (0x00000018) #define REG_DP_CLK_ACTIVE (0x0000001C) #define REG_DP_INTR_STATUS (0x00000020) #define DP_INTR_HPD BIT(0) #define DP_INTR_AUX_XFER_DONE BIT(3) #define DP_INTR_WRONG_ADDR BIT(6) #define DP_INTR_TIMEOUT BIT(9) #define DP_INTR_NACK_DEFER BIT(12) #define DP_INTR_WRONG_DATA_CNT BIT(15) #define DP_INTR_I2C_NACK BIT(18) #define DP_INTR_I2C_DEFER BIT(21) #define DP_INTR_PLL_UNLOCKED BIT(24) #define DP_INTR_AUX_ERROR BIT(27) #define REG_DP_INTR_STATUS2 (0x00000024) #define DP_INTR_READY_FOR_VIDEO BIT(0) #define DP_INTR_IDLE_PATTERN_SENT BIT(3) #define DP_INTR_FRAME_END BIT(6) #define DP_INTR_CRC_UPDATED BIT(9) #define REG_DP_INTR_STATUS3 (0x00000028) #define REG_DP_INTR_STATUS4 (0x0000002C) #define PSR_UPDATE_INT (0x00000001) #define PSR_CAPTURE_INT (0x00000004) #define PSR_EXIT_INT (0x00000010) #define #define PSR_UPDATE_ERROR_INT () # DP_PHY_CTRL_SW_RESET (x00000004 define (0) #define PSR_UPDATE_MASK (0x00000001) #define PSR_CAPTURE_MASK (0x00000002) #define PSR_EXIT_MASK (0x00000004) #define PSR_UPDATE_ERROR_MASK (0x00000008) java.lang.NullPointerException define (x00000000java.lang.StringIndexOutOfBoundsException: Index 41 out of bound #definedefine BIT() #define REG_DP_DP_HPD_INT_STATUS (0x00000004) #define REG_DP_DP_HPD_INT_ACK (0x00000008) #define DP_DP_HPD_PLUG_INT_ACK (0x00000001) #define DP_DP_IRQ_HPD_INT_ACK (0x00000002) java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 # REG_DP_INTR_STATUS4 00002java.lang.StringIndexOutOfBoundsException: Index 42 out define 0) #define# PSR_WAKE_ERROR_INT (x00000100 #define REG_DP_DP_HPD_INT_MASK# PSR_UPDATE_MASK (x00000001 #define DP_DP_HPD_PLUG_INT_MASK 0) #define DP_DP_IRQ_HPD_INT_MASKdefine (x00000004) #defineDP_DP_HPD_REPLUG_INT_MASK (0x00000004 #definedefinePSR_WAKE_ERROR_MASK (0) #define DP_DP_HPD_INT_MASK (P_DP_HPD_PLUG_INT_MASK|\ define (0) DP_DP_HPD_REPLUG_INT_MASK | DP_DP_HPD_UNPLUG_INT_MASK java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 #define DP_DP_HPD_STATE_STATUS_PENDINGDP_DP_HPD_PLUG_INT_ACK (0x00000001) ##define DP_DP_IRQ_HPD_INT_ACK 0) #define DP_DP_HPD_STATE_STATUS_MASK (xE0000000 DP_DP_HPD_UNPLUG_INT_ACK (x00000008 #defineDP_DP_HPD_STATE_STATUS_BITS_MASK000000) #defineREG_DP_DP_HPD_EVENT_TIME_0 0) #define java.lang.StringIndexOutOfBoundsException: Index 15 out of bounds for len # DP_DP_HPD_EVENT_TIME_0_VAL (0) ## DP_DP_IRQ_HPD_INT_MASK (x00000002 #define REG_DP_AUX_CTRL (0x00000030) #define DP_AUX_CTRL_ENABLE (0x00000001) #define DP_AUX_CTRL_RESET (0x00000002) #define REG_DP_AUX_DATA (0x00000034) DP_AUX_DATA_READ (x00000001 ## ( | java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length #define P_DP_HPD_UNPLUG_INT_MASK) #define (0x00000010) #define DP_AUX_DATA_MASKdefineDP_DP_HPD_STATE_STATUS_PENDING 0x20000000) #defineDP_AUX_DATA_INDEX_WRITE (0x80000000) #define REG_DP_AUX_TRANS_CTRL (0x00000038) #define DP_AUX_TRANS_CTRL_I2C (0x00000100) #definedefine 0x00000018) #definedefineDP_DP_HPD_REFTIMER_ENABLE 1 < 6) #defineDP_AUX_TRANS_CTRL_NO_SEND_STOP (0x00000800) #define defineDP_DP_HPD_EVENT_TIME_0_VAL (x3E800FA #defineDP_DP_HPD_EVENT_TIME_1_VAL(x1F407D0 #definedefineREG_DP_AUX_CTRL (x00000030 #define DP_DPCD_CP_IRQ (0x201) #define DP_DPCD_RXSTATUSdefine ((x00000002) ## REG_DP_AUX_DATA 0) # REG_DP_MAINLINK_CTRL (0x00000000 #define DP_MAINLINK_CTRL_ENABLE(x00000001 #define DP_MAINLINK_CTRL_RESET (0x00000002) #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER (0x00000010) #define DP_MAINLINK_CTRL_FLUSH_MODE_MASK GENMASK(24,defineDP_AUX_DATA_OFFSET (x0000 #define FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK 1) #define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE FIELD_PREP(DP_MAINLINK_CTRL_FLUSH #define #define DP_MAINLINK_FB_BOUNDARY_SEL) #defineREG_DP_STATE_CTRL 0x00000004) #define #define (0x00000002) #define (0x00000100 #define# DP_AUX_TRANS_CTRL_GO(x00000200) #defineDP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE 0x00000010) #define DP_STATE_CTRL_LINK_PRBS7 (defineDP_AUX_TRANS_CTRL_NO_SEND_STOP (x00000800 #define DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN (define (0) # DP_STATE_CTRL_SEND_VIDEO (x00000080 java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 #define REG_DP_CONFIGURATION_CTRL#definedefine DP_DPCD_RXSTATUS 0) # DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK (0x00000001java.lang.StringIndexOutOfBounds #define DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN#defineDP_MAINLINK_CTRL_ENABLE (0) #define DP_CONFIGURATION_CTRL_P_INTERLACED0x00000004) #define DP_CONFIGURATION_CTRL_INTERLACED_BTF#defineDP_MAINLINK_CTRL_SW_BYPASS_SCR ##define DP_MAINLINK_CTRL_FLUSH_MODE_MASK GENMASK(24 3java.lang.StringIndexOutOfBou #defineDP_CONFIGURATION_CTRL_ENHANCED_FRAMING(x00000040 #define DP_CONFIGURATION_CTRL_SEND_VSC (0x00000080defineDP_MAINLINK_FLUSH_MODE_SDE # DP_CONFIGURATION_CTRL_BPC 0x00000100) #defineDP_CONFIGURATION_CTRL_ASSR 0x00000400) #defineDP_CONFIGURATION_CTRL_RGB_YUV 0x00000800) #defineDP_CONFIGURATION_CTRL_LSCLK_DIV (x00002000 # DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT(x04 #defineDP_CONFIGURATION_CTRL_BPC_SHIFT 0x08) #define DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFTdefineDP_STATE_CTRL_LINK_SYMBOL_ERR_ #define REG_DP_SOFTWARE_MVIDdefineDP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN0x0000004 #define REG_DP_SOFTWARE_NVID (0x00000018) #define REG_DP_TOTAL_HOR_VER 0) #define REG_DP_START_HOR_VER_FROM_SYNC (0x00000020) # REG_DP_HSYNC_VSYNC_WIDTH_POLARITY (x00000024 #define REG_DP_ACTIVE_HOR_VER (x00000028 #define REG_DP_MISC1_MISC0 (0x0000002CdefineDP_CONFIGURATION_CTRL_P_INTERLACED(x00 define DP_MISC0_SYNCHRONOUS_CLK (000000001) #define #define DP_CONFIGURATION_CTRL_NUM_OF_LANES (0x00000010) # DP_MISC0_TEST_BITS_DEPTH_SHIFT (0x00000005) # DP_MISC1_VSC_SDP (x00004000 #define DP_MISC0_COLORIMERY_CFG_LEGACY_RGB (0) #define DP_MISC0_COLORIMERY_CFG_CEA_RGB (0x04) #define REG_DP_VALID_BOUNDARY (0x00000030) #define REG_DP_VALID_BOUNDARY_2 (0x00000034) #define REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING (0x00000038) #define LANE0_MAPPING_SHIFT (0x00000000) #define LANE1_MAPPING_SHIFT RGB_YUV (0x00000800) #define LANE2_MAPPING_SHIFT (0x00000004) #define LANE3_MAPPING_SHIFT (x00000006) #define define DP_CONFIGURATION_CTRL_BPC_SHIFT) # DP_MAINLINK_READY_FOR_VIDEO (000001) # DP_MAINLINK_READY_LINK_TRAINING_SHIFT0x00000003) #define REG_DP_MAINLINK_LEVELS (0x00000044) #define DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2 (0x00000002) #define defineREG_DP_START_HOR_VER_FROM_SYNC(x00000020 #definedefineREG_DP_ACTIVE_HOR_VER (x00000028 #define DP_HBR2_ERM_PATTERN (x00010000 #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0 (0x000000C0) #define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1 (0x000000C4) #defineREG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2(x000000C8 #define MMSS_DP_MISC1_MISC0 (0x0000002C) #define MMSS_DP_AUDIO_TIMING_GEN (0x00000080) ##defineDP_MISC1_VSC_SDP (0x00004000) #define #define MMSS_DP_AUDIO_TIMING_RBR_44 (0x0000008C) #define # DP_MISC0_COLORIMERY_CFG_CEA_RGB (0x04) #define MMSS_DP_AUDIO_TIMING_RBR_48 0x00000094) #define REG_DP_VALID_BOUNDARY_2 (x00000034 #define REG_PSR_CONFIG (0x00000100) #define DISABLE_PSR (0x00000000) #define PSR1_SUPPORTED (0x00000001) #define PSR2_WITHOUT_FRAMESYNC (x00000002 #definePSR2_WITH_FRAMESYNC 0x00000003 #define REG_PSR_CMD (0x00000110) #define PSR_ENTER (0x00000001) #define) java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0 # MMSS_DP_PSR_CRC_B (x00000158) # 0) #definedefine 0) #define MMSS_DP_AUDIO_STATUS (0x00000204 # MMSS_DP_AUDIO_PKT_CTRL (0x00000208 #definedefineREG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1 (0) #define MMSS_DP_AUDIO_ACR_CTRL) #define MMSS_DP_AUDIO_CTRL_RESET (0x00000214) #define # MMSS_DP_AUDIO_TIMING_GEN (0) #defineGEN0_SDP_EN (x00020000 #define MMSS_DP_SDP_CFG2 (0x0000022C MMSS_DP_AUDIO_TIMING_HBR_32 0x00000088) #define MMSS_DP_AUDIO_TIMESTAMP_0 (0x00000230) # MMSS_DP_AUDIO_TIMESTAMP_1(x00000234 #define GENERIC0_SDPSIZE_VALID # MSS_DP_AUDIO_TIMING_HBR_440x00000090) #define MMSS_DP_AUDIO_STREAM_0 (0x00000240) #define MMSS_DP_AUDIO_STREAM_1 (0x00000244) #defineMMSS_DP_SDP_CFG3 (0x0000024c) #define UPDATE_SDP (0x00000001) #define MMSS_DP_EXTENSION_0 (0x00000250) #define MMSS_DP_EXTENSION_1 (0x00000254) #define MMSS_DP_EXTENSION_2 (0x00000258) #define MMSS_DP_EXTENSION_3 (0x0000025C) #define MMSS_DP_EXTENSION_4 (0x00000260) #define MMSS_DP_EXTENSION_5 (0x00000264) #define REG_PSR_CONFIG (0x00000100 #define (0x00000000) #define MMSS_DP_EXTENSION_8 (0x00000270) ##definePSR2_WITHOUT_FRAMESYNC (x00000002 # MMSS_DP_AUDIO_COPYMANAGEMENT_00) #define MMSS_DP_AUDIO_COPYMANAGEMENT_1 (0x0000027C () #define #define PSR_ENTER(0x00000001) #define MMSS_DP_AUDIO_COPYMANAGEMENT_4 (0x00000288) #defineMMSS_DP_AUDIO_COPYMANAGEMENT_5 0x0000028C) define (0) #define MMSS_DP_AUDIO_ISRC_1 (0x00000294) #define MMSS_DP_AUDIO_ISRC_2 (x00000298 #define MMSS_DP_AUDIO_ISRC_3 ( #define MMSS_DP_AUDIO_ISRC_4 (0x000002A0) #define MMSS_DP_AUDIO_ISRC_5 (0x000002A4) #define MMSS_DP_AUDIO_INFOFRAME_0 (0x000002A8) #define MMSS_DP_AUDIO_INFOFRAME_1 (0x000002AC) #define MMSS_DP_AUDIO_INFOFRAME_2 (0x000002B0) #define MMSS_DP_GENERIC0_0 (0x00000300) #define MMSS_DP_GENERIC0_1 (0x00000304) #define MMSS_DP_GENERIC0_2 (0x00000308) #define MMSS_DP_GENERIC0_3 (0x0000030Cdefine 0x00000180) #define MMSS_DP_GENERIC0_4MMSS_DP_AUDIO_CFG (x00000200 # MMSS_DP_GENERIC0_5(0x00000314java.lang.StringIndexOutOfBoundsException: Index 4 #define MMSS_DP_GENERIC0_6 # MMSS_DP_GENERIC0_7 (x0000031C #define MMSS_DP_GENERIC0_8 (0x00000320) # MMSS_DP_GENERIC0_9 (x00000324 #define MMSS_DP_GENERIC1_0 (0x00000328) #efine MMSS_DP_GENERIC1_1 0) #define MMSS_DP_GENERIC1_2 (00003) #define MMSS_DP_GENERIC1_3 (0x00000334) #define MMSS_DP_GENERIC1_4 (0x00000338) #define MMSS_DP_GENERIC1_5 (0x0000033C) #defineMMSS_DP_AUDIO_TIMESTAMP_1 (x00000234 # MMSS_DP_GENERIC1_7 (0x00000344) #defineMMSS_DP_AUDIO_STREAM_0 (x00000240 # MMSS_DP_GENERIC1_9 (0) #defineMMSS_DP_SDP_CFG3 (x0000024c) #defineMMSS_DP_VSCEXT_1 0x000002D4) #define MMSS_DP_VSCEXT_2 #efineMMSS_DP_VSCEXT_3 0x000002DC) #define MMSS_DP_VSCEXT_4 (0x000002E0) #define MMSS_DP_VSCEXT_5 (0x000002E4) #define MMSS_DP_VSCEXT_6 (x000002E8 #defineMMSS_DP_VSCEXT_7 (x000002EC # MMSS_DP_VSCEXT_8 (0x000002F0) #defineMMSS_DP_VSCEXT_9 (x000002F4 #define MMSS_DP_BIST_ENABLE (0x00000000) #define DP_BIST_ENABLE_DPBIST_EN (0x00000001) #define MMSS_DP_TIMING_ENGINE_EN (0) # DP_TIMING_ENGINE_EN_EN (x00000001 #define MMSS_DP_INTF_CONFIG (0x00000014) #define MMSS_DP_INTF_HSYNC_CTL (0x00000018) #defineMMSS_DP_INTF_VSYNC_PERIOD_F00x0000001C #define MMSS_DP_INTF_VSYNC_PERIOD_F1 MMSS_DP_AUDIO_COPYMANAGEMENT_3 (x00000284 #define MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0 (0x00000024) ##defineMMSS_DP_AUDIO_COPYMANAGEMENT_5(x0000028C #defineMMSS_DP_AUDIO_ISRC_0 (0x00000290 # MMSS_INTF_DISPLAY_V_START_F1 (0x00000030 # MMSS_DP_INTF_DISPLAY_V_END_F0(x00000034 #defineMMSS_DP_INTF_DISPLAY_V_END_F1(x00000038 #defineMMSS_DP_INTF_ACTIVE_V_START_F0 0x0000003C) #define MMSS_DP_INTF_ACTIVE_V_START_F10x00000040 #defineMMSS_DP_INTF_ACTIVE_V_END_F0(x00000044 #define MMSS_DP_INTF_ACTIVE_V_END_F1 (x00000048 #define MMSS_DP_INTF_DISPLAY_HCTL (0x0000004C #define define (0x00000300) #define (0x00000058 #define define (0) defineMMSS_DP_DSC_DTO (0) #define DP_TPG_CHECKERED_RECT_PATTERN (0x00000100) #define MMSS_DP_TPG_VIDEO_CONFIG (0x00000064) #define DP_TPG_VIDEO_CONFIG_BPP_8BIT (0x00000001) # DP_TPG_VIDEO_CONFIG_RGB (x00000004 #definedefine 0x0000031C) #defineREG_DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C) # REG_DP_PHY_AUX_BIST_CFG (x00000050 #defineREG_DP_PHY_AUX_INTERRUPT_STATUS(x000000BC /* DP HDCP 1.3 registers */MMSS_DP_GENERIC1_1 (x0000032C #define DP_HDCP_CTRL(0x0A0 #define DP_HDCP_STATUS (0x0A4) #define DP_HDCP_SW_UPPER_AKSV defineMMSS_DP_GENERIC1_4 (0) #define DP_HDCP_SW_LOWER_AKSVdefineMMSS_DP_GENERIC1_6 0) #define MMSS_DP_GENERIC1_7 (0000034) #defineDP_HDCP_ENTROPY_CTRL1(0x35C) #define DP_HDCP_SHA_STATUS (0x0C8) #define DP_HDCP_RCVPORT_DATA2_0 (0x0B0) #define DP_HDCP_RCVPORT_DATA3 (0x0A4) #define DP_HDCP_RCVPORT_DATA4 (0x0A8) #define DP_HDCP_RCVPORT_DATA5 (0x0C0) DP_HDCP_RCVPORT_DATA6 0) #define # (x00000028 #defineHDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_DATA(x028 #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA0 (0x004) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA1 (defineMMSS_INTF_DISPLAY_V_START #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA7 (0x00C) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA8 0) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA9C) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA10 (0x018) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA11 (0x01C) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA12 (0x020) #endif /* _DP_REG_H_ */
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2026-04-06