| Quellcodebibliothek Statistik Leitseite products/Sources/formale Sprachen/C/Linux/drivers/gpu/drm/amd/include/asic_reg/gc/ (Open Source Betriebssystem Version 6.17.9©) Datei vom 24.10.2025 mit Größe 3 MB |
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Quelle gc_9_1_sh_mask.h Sprache: C |
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/* * Copyright (C) 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _gc_9_1_SH_MASK_HEADER #define _gc_9_1_SH_MASK_HEADER // addressBlock: gc_grbmdec //GRBM_CNTL #define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 #define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f #define GRBM_CNTL__READ_TIMEOUT_MASK 0x000000FFL #define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000L //GRBM_SKEW_CNTL #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 #define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 #define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x0000003FL #define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0x00000FC0L //GRBM_STATUS2 #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd #define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe #define GRBM_STATUS2__UTCL2_BUSY__SHIFT 0xf #define GRBM_STATUS2__EA_BUSY__SHIFT 0x10 #define GRBM_STATUS2__RMI_BUSY__SHIFT 0x11 #define GRBM_STATUS2__UTCL2_RQ_PENDING__SHIFT 0x12 #define GRBM_STATUS2__CPF_RQ_PENDING__SHIFT 0x13 #define GRBM_STATUS2__EA_LINK_BUSY__SHIFT 0x14 #define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18 #define GRBM_STATUS2__TC_BUSY__SHIFT 0x19 #define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a #define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c #define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d #define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e #define GRBM_STATUS2__CPAXI_BUSY__SHIFT 0x1f #define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000FL #define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x00000010L #define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x00000020L #define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x00000040L #define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x00000080L #define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x00000100L #define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x00000200L #define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x00000400L #define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x00000800L #define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x00001000L #define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x00002000L #define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x00004000L #define GRBM_STATUS2__UTCL2_BUSY_MASK 0x00008000L #define GRBM_STATUS2__EA_BUSY_MASK 0x00010000L #define GRBM_STATUS2__RMI_BUSY_MASK 0x00020000L #define GRBM_STATUS2__UTCL2_RQ_PENDING_MASK 0x00040000L #define GRBM_STATUS2__CPF_RQ_PENDING_MASK 0x00080000L #define GRBM_STATUS2__EA_LINK_BUSY_MASK 0x00100000L #define GRBM_STATUS2__RLC_BUSY_MASK 0x01000000L #define GRBM_STATUS2__TC_BUSY_MASK 0x02000000L #define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x04000000L #define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000L #define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000L #define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000L #define GRBM_STATUS2__CPAXI_BUSY_MASK 0x80000000L //GRBM_PWR_CNTL #define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0 #define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2 #define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4 #define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6 #define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe #define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf #define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x00000003L #define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0x0000000CL #define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x00000030L #define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0x000000C0L #define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x00004000L #define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x00008000L //GRBM_STATUS #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 #define GRBM_STATUS__RSMU_RQ_PENDING__SHIFT 0x5 #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 #define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 #define GRBM_STATUS__DB_CLEAN__SHIFT 0xc #define GRBM_STATUS__CB_CLEAN__SHIFT 0xd #define GRBM_STATUS__TA_BUSY__SHIFT 0xe #define GRBM_STATUS__GDS_BUSY__SHIFT 0xf #define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10 #define GRBM_STATUS__VGT_BUSY__SHIFT 0x11 #define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12 #define GRBM_STATUS__IA_BUSY__SHIFT 0x13 #define GRBM_STATUS__SX_BUSY__SHIFT 0x14 #define GRBM_STATUS__WD_BUSY__SHIFT 0x15 #define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 #define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 #define GRBM_STATUS__SC_BUSY__SHIFT 0x18 #define GRBM_STATUS__PA_BUSY__SHIFT 0x19 #define GRBM_STATUS__DB_BUSY__SHIFT 0x1a #define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c #define GRBM_STATUS__CP_BUSY__SHIFT 0x1d #define GRBM_STATUS__CB_BUSY__SHIFT 0x1e #define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f #define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000FL #define GRBM_STATUS__RSMU_RQ_PENDING_MASK 0x00000020L #define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x00000080L #define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x00000100L #define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x00000200L #define GRBM_STATUS__DB_CLEAN_MASK 0x00001000L #define GRBM_STATUS__CB_CLEAN_MASK 0x00002000L #define GRBM_STATUS__TA_BUSY_MASK 0x00004000L #define GRBM_STATUS__GDS_BUSY_MASK 0x00008000L #define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x00010000L #define GRBM_STATUS__VGT_BUSY_MASK 0x00020000L #define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x00040000L #define GRBM_STATUS__IA_BUSY_MASK 0x00080000L #define GRBM_STATUS__SX_BUSY_MASK 0x00100000L #define GRBM_STATUS__WD_BUSY_MASK 0x00200000L #define GRBM_STATUS__SPI_BUSY_MASK 0x00400000L #define GRBM_STATUS__BCI_BUSY_MASK 0x00800000L #define GRBM_STATUS__SC_BUSY_MASK 0x01000000L #define GRBM_STATUS__PA_BUSY_MASK 0x02000000L #define GRBM_STATUS__DB_BUSY_MASK 0x04000000L #define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000L #define GRBM_STATUS__CP_BUSY_MASK 0x20000000L #define GRBM_STATUS__CB_BUSY_MASK 0x40000000L #define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000L //GRBM_STATUS_SE0 #define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 #define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 #define GRBM_STATUS_SE0__RMI_BUSY__SHIFT 0x15 #define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 #define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17 #define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 #define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 #define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a #define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b #define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d #define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e #define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f #define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x00000002L #define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x00000004L #define GRBM_STATUS_SE0__RMI_BUSY_MASK 0x00200000L #define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x00400000L #define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x00800000L #define GRBM_STATUS_SE0__PA_BUSY_MASK 0x01000000L #define GRBM_STATUS_SE0__TA_BUSY_MASK 0x02000000L #define GRBM_STATUS_SE0__SX_BUSY_MASK 0x04000000L #define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x08000000L #define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000L #define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000L #define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000L //GRBM_STATUS_SE1 #define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 #define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 #define GRBM_STATUS_SE1__RMI_BUSY__SHIFT 0x15 #define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 #define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17 #define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 #define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 #define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a #define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b #define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d #define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e #define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f #define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x00000002L #define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x00000004L #define GRBM_STATUS_SE1__RMI_BUSY_MASK 0x00200000L #define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x00400000L #define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x00800000L #define GRBM_STATUS_SE1__PA_BUSY_MASK 0x01000000L #define GRBM_STATUS_SE1__TA_BUSY_MASK 0x02000000L #define GRBM_STATUS_SE1__SX_BUSY_MASK 0x04000000L #define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x08000000L #define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000L #define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000L #define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000L //GRBM_SOFT_RESET #define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 #define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 #define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 #define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 #define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 #define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 #define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14 #define GRBM_SOFT_RESET__SOFT_RESET_CPAXI__SHIFT 0x15 #define GRBM_SOFT_RESET__SOFT_RESET_EA__SHIFT 0x16 #define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x00000001L #define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x00000004L #define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x00010000L #define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x00020000L #define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x00040000L #define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x00080000L #define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x00100000L #define GRBM_SOFT_RESET__SOFT_RESET_CPAXI_MASK 0x00200000L #define GRBM_SOFT_RESET__SOFT_RESET_EA_MASK 0x00400000L //GRBM_CGTT_CLK_CNTL #define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0 #define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7__SHIFT 0x10 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6__SHIFT 0x11 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5__SHIFT 0x12 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4__SHIFT 0x13 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3__SHIFT 0x14 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2__SHIFT 0x15 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1__SHIFT 0x16 #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0__SHIFT 0x17 #define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e #define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0x0000000FL #define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0x00000FF0L #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE7_MASK 0x00010000L #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE6_MASK 0x00020000L #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE5_MASK 0x00040000L #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE4_MASK 0x00080000L #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE3_MASK 0x00100000L #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE2_MASK 0x00200000L #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE1_MASK 0x00400000L #define GRBM_CGTT_CLK_CNTL__SOFT_STALL_OVERRIDE0_MASK 0x00800000L #define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000L //GRBM_GFX_CLKEN_CNTL #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 #define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0x0000000FL #define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x00001F00L //GRBM_WAIT_IDLE_CLOCKS #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 #define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0x000000FFL //GRBM_STATUS_SE2 #define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 #define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 #define GRBM_STATUS_SE2__RMI_BUSY__SHIFT 0x15 #define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 #define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17 #define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 #define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 #define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a #define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b #define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d #define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e #define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f #define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x00000002L #define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x00000004L #define GRBM_STATUS_SE2__RMI_BUSY_MASK 0x00200000L #define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x00400000L #define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x00800000L #define GRBM_STATUS_SE2__PA_BUSY_MASK 0x01000000L #define GRBM_STATUS_SE2__TA_BUSY_MASK 0x02000000L #define GRBM_STATUS_SE2__SX_BUSY_MASK 0x04000000L #define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x08000000L #define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000L #define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000L #define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000L //GRBM_STATUS_SE3 #define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1 #define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2 #define GRBM_STATUS_SE3__RMI_BUSY__SHIFT 0x15 #define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16 #define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17 #define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18 #define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19 #define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a #define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b #define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d #define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e #define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f #define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x00000002L #define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x00000004L #define GRBM_STATUS_SE3__RMI_BUSY_MASK 0x00200000L #define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x00400000L #define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x00800000L #define GRBM_STATUS_SE3__PA_BUSY_MASK 0x01000000L #define GRBM_STATUS_SE3__TA_BUSY_MASK 0x02000000L #define GRBM_STATUS_SE3__SX_BUSY_MASK 0x04000000L #define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x08000000L #define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000L #define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000L #define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000L //GRBM_READ_ERROR #define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 #define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 #define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 #define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f #define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x0003FFFCL #define GRBM_READ_ERROR__READ_PIPEID_MASK 0x00300000L #define GRBM_READ_ERROR__READ_MEID_MASK 0x00C00000L #define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000L //GRBM_READ_ERROR2 #define GRBM_READ_ERROR2__READ_REQUESTER_CPF__SHIFT 0x10 #define GRBM_READ_ERROR2__READ_REQUESTER_RSMU__SHIFT 0x11 #define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f #define GRBM_READ_ERROR2__READ_REQUESTER_CPF_MASK 0x00010000L #define GRBM_READ_ERROR2__READ_REQUESTER_RSMU_MASK 0x00020000L #define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x00040000L #define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x00080000L #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x00100000L #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x00200000L #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x00400000L #define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x00800000L #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x01000000L #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x02000000L #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x04000000L #define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x08000000L #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000L #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000L #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000L #define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000L //GRBM_INT_CNTL #define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 #define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x00000001L #define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x00080000L //GRBM_TRAP_OP #define GRBM_TRAP_OP__RW__SHIFT 0x0 #define GRBM_TRAP_OP__RW_MASK 0x00000001L //GRBM_TRAP_ADDR #define GRBM_TRAP_ADDR__DATA__SHIFT 0x0 #define GRBM_TRAP_ADDR__DATA_MASK 0x0003FFFFL //GRBM_TRAP_ADDR_MSK #define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0 #define GRBM_TRAP_ADDR_MSK__DATA_MASK 0x0003FFFFL //GRBM_TRAP_WD #define GRBM_TRAP_WD__DATA__SHIFT 0x0 #define GRBM_TRAP_WD__DATA_MASK 0xFFFFFFFFL //GRBM_TRAP_WD_MSK #define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0 #define GRBM_TRAP_WD_MSK__DATA_MASK 0xFFFFFFFFL //GRBM_DSM_BYPASS #define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0 #define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2 #define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x00000003L #define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x00000004L //GRBM_WRITE_ERROR #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0 #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU__SHIFT 0x1 #define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2 #define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5 #define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc #define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd #define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14 #define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16 #define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x00000001L #define GRBM_WRITE_ERROR__WRITE_REQUESTER_RSMU_MASK 0x00000002L #define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x0000001CL #define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x000001E0L #define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x00001000L #define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x0001E000L #define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x00300000L #define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0x00C00000L #define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000L //GRBM_IOV_ERROR #define GRBM_IOV_ERROR__IOV_ADDR__SHIFT 0x2 #define GRBM_IOV_ERROR__IOV_VFID__SHIFT 0x14 #define GRBM_IOV_ERROR__IOV_VF__SHIFT 0x1a #define GRBM_IOV_ERROR__IOV_OP__SHIFT 0x1b #define GRBM_IOV_ERROR__IOV_ERROR__SHIFT 0x1f #define GRBM_IOV_ERROR__IOV_ADDR_MASK 0x000FFFFCL #define GRBM_IOV_ERROR__IOV_VFID_MASK 0x03F00000L #define GRBM_IOV_ERROR__IOV_VF_MASK 0x04000000L #define GRBM_IOV_ERROR__IOV_OP_MASK 0x08000000L #define GRBM_IOV_ERROR__IOV_ERROR_MASK 0x80000000L //GRBM_CHIP_REVISION #define GRBM_CHIP_REVISION__CHIP_REVISION__SHIFT 0x0 #define GRBM_CHIP_REVISION__CHIP_REVISION_MASK 0x000000FFL //GRBM_GFX_CNTL #define GRBM_GFX_CNTL__PIPEID__SHIFT 0x0 #define GRBM_GFX_CNTL__MEID__SHIFT 0x2 #define GRBM_GFX_CNTL__VMID__SHIFT 0x4 #define GRBM_GFX_CNTL__QUEUEID__SHIFT 0x8 #define GRBM_GFX_CNTL__PIPEID_MASK 0x00000003L #define GRBM_GFX_CNTL__MEID_MASK 0x0000000CL #define GRBM_GFX_CNTL__VMID_MASK 0x000000F0L #define GRBM_GFX_CNTL__QUEUEID_MASK 0x00000700L //GRBM_RSMU_CFG #define GRBM_RSMU_CFG__APERTURE_ID__SHIFT 0x0 #define GRBM_RSMU_CFG__QOS__SHIFT 0xc #define GRBM_RSMU_CFG__POSTED_WR__SHIFT 0x10 #define GRBM_RSMU_CFG__APERTURE_ID_MASK 0x00000FFFL #define GRBM_RSMU_CFG__QOS_MASK 0x0000F000L #define GRBM_RSMU_CFG__POSTED_WR_MASK 0x00010000L //GRBM_IH_CREDIT #define GRBM_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 #define GRBM_IH_CREDIT__IH_CLIENT_ID__SHIFT 0x10 #define GRBM_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L #define GRBM_IH_CREDIT__IH_CLIENT_ID_MASK 0x00FF0000L //GRBM_PWR_CNTL2 #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT__SHIFT 0x10 #define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT__SHIFT 0x14 #define GRBM_PWR_CNTL2__PWR_REQUEST_HALT_MASK 0x00010000L #define GRBM_PWR_CNTL2__PWR_GFX3D_REQUEST_HALT_MASK 0x00100000L //GRBM_UTCL2_INVAL_RANGE_START #define GRBM_UTCL2_INVAL_RANGE_START__DATA__SHIFT 0x0 #define GRBM_UTCL2_INVAL_RANGE_START__DATA_MASK 0x0003FFFFL //GRBM_UTCL2_INVAL_RANGE_END #define GRBM_UTCL2_INVAL_RANGE_END__DATA__SHIFT 0x0 #define GRBM_UTCL2_INVAL_RANGE_END__DATA_MASK 0x0003FFFFL //GRBM_RSMU_READ_ERROR #define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS__SHIFT 0x2 #define GRBM_RSMU_READ_ERROR__RSMU_READ_VF__SHIFT 0x14 #define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID__SHIFT 0x15 #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE__SHIFT 0x1b #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR__SHIFT 0x1f #define GRBM_RSMU_READ_ERROR__RSMU_READ_ADDRESS_MASK 0x000FFFFCL #define GRBM_RSMU_READ_ERROR__RSMU_READ_VF_MASK 0x00100000L #define GRBM_RSMU_READ_ERROR__RSMU_READ_VFID_MASK 0x07E00000L #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_TYPE_MASK 0x08000000L #define GRBM_RSMU_READ_ERROR__RSMU_READ_ERROR_MASK 0x80000000L //GRBM_CHICKEN_BITS #define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ__SHIFT 0x0 #define GRBM_CHICKEN_BITS__DISABLE_CP_VMID_RESET_REQ_MASK 0x00000001L //GRBM_NOWHERE #define GRBM_NOWHERE__DATA__SHIFT 0x0 #define GRBM_NOWHERE__DATA_MASK 0xFFFFFFFFL //GRBM_SCRATCH_REG0 #define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 #define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xFFFFFFFFL //GRBM_SCRATCH_REG1 #define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 #define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xFFFFFFFFL //GRBM_SCRATCH_REG2 #define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 #define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xFFFFFFFFL //GRBM_SCRATCH_REG3 #define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 #define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xFFFFFFFFL //GRBM_SCRATCH_REG4 #define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 #define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xFFFFFFFFL //GRBM_SCRATCH_REG5 #define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 #define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xFFFFFFFFL //GRBM_SCRATCH_REG6 #define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 #define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xFFFFFFFFL //GRBM_SCRATCH_REG7 #define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 #define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xFFFFFFFFL // addressBlock: gc_cpdec //CP_CPC_STATUS #define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 #define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 #define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 #define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 #define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 #define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 #define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 #define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 #define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa #define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb #define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc #define CP_CPC_STATUS__UTCL2IU_BUSY__SHIFT 0xd #define CP_CPC_STATUS__SAVE_RESTORE_BUSY__SHIFT 0xe #define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d #define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e #define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f #define CP_CPC_STATUS__MEC1_BUSY_MASK 0x00000001L #define CP_CPC_STATUS__MEC2_BUSY_MASK 0x00000002L #define CP_CPC_STATUS__DC0_BUSY_MASK 0x00000004L #define CP_CPC_STATUS__DC1_BUSY_MASK 0x00000008L #define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x00000010L #define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x00000020L #define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x00000040L #define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x00000080L #define CP_CPC_STATUS__TCIU_BUSY_MASK 0x00000400L #define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x00000800L #define CP_CPC_STATUS__QU_BUSY_MASK 0x00001000L #define CP_CPC_STATUS__UTCL2IU_BUSY_MASK 0x00002000L #define CP_CPC_STATUS__SAVE_RESTORE_BUSY_MASK 0x00004000L #define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000L #define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000L #define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000L //CP_CPC_BUSY_STAT #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1 #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11 #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d #define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x00000001L #define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x00000002L #define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x00000004L #define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x00000008L #define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x00000010L #define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x00000020L #define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x00000040L #define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x00000080L #define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x00000100L #define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x00000200L #define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x00000400L #define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x00000800L #define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x00001000L #define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x00002000L #define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x00010000L #define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x00020000L #define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x00040000L #define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x00080000L #define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x00100000L #define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x00200000L #define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x00400000L #define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x00800000L #define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x01000000L #define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x02000000L #define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x04000000L #define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x08000000L #define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000L #define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000L //CP_CPC_STALLED_STAT1 #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE__SHIFT 0x16 #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS__SHIFT 0x17 #define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS__SHIFT 0x18 #define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x00000008L #define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x00000010L #define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x00000040L #define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x00000100L #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x00000200L #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x00000400L #define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x00002000L #define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x00010000L #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x00020000L #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x00040000L #define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x00200000L #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_FREE_MASK 0x00400000L #define CP_CPC_STALLED_STAT1__UTCL2IU_WAITING_ON_TAGS_MASK 0x00800000L #define CP_CPC_STALLED_STAT1__UTCL1_WAITING_ON_TRANS_MASK 0x01000000L //CP_CPF_STATUS #define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 #define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 #define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 #define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 #define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 #define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 #define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 #define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 #define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa #define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb #define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc #define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd #define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe #define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf #define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10 #define CP_CPF_STATUS__UTCL2IU_BUSY__SHIFT 0x11 --> -------------------- --> maximum size reached --> --------------------
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2026-04-07