| Quellcodebibliothek Statistik Leitseite products/Sources/formale Sprachen/C/Linux/drivers/gpu/drm/amd/include/asic_reg/dcn/ (Open Source Betriebssystem Version 6.17.9©) Datei vom 24.10.2025 mit Größe 1 MB |
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Quellcode-Bibliothek dcn_1_0_offset.hSprache: C |
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/* * Copyright (C) 2017 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included * in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _dcn_1_0_OFFSET_HEADER #define _dcn_1_0_OFFSET_HEADER // addressBlock: dce_dc_hda_azcontroller_azdec // base address: 0x1300000 // addressBlock: dce_dc_hda_azendpoint_azdec // base address: 0x1300000 // addressBlock: dce_dc_hda_azinputendpoint_azdec // base address: 0x1300000 // addressBlock: dce_dc_hda_azroot_azdec // base address: 0x1300000 // addressBlock: dce_dc_hda_azstream0_azdec // base address: 0x1300000 // addressBlock: dce_dc_hda_azstream1_azdec // base address: 0x1300020 // addressBlock: dce_dc_hda_azstream2_azdec // base address: 0x1300040 // addressBlock: dce_dc_hda_azstream3_azdec // base address: 0x1300060 // addressBlock: dce_dc_hda_azstream4_azdec // base address: 0x1300080 // addressBlock: dce_dc_hda_azstream5_azdec // base address: 0x13000a0 // addressBlock: dce_dc_hda_azstream6_azdec // base address: 0x13000c0 // addressBlock: dce_dc_hda_azstream7_azdec // base address: 0x13000e0 // addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] // base address: 0x48 #define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000 #define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 #define mmVGA_MEM_READ_PAGE_ADDR 0x0001 #define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 // addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986] // base address: 0x3b4 #define mmCRTC8_IDX 0x002d #define mmCRTC8_IDX_BASE_IDX 1 #define mmCRTC8_DATA 0x002d #define mmCRTC8_DATA_BASE_IDX 1 #define mmGENFC_WT 0x002e #define mmGENFC_WT_BASE_IDX 1 #define mmGENS1 0x002e #define mmGENS1_BASE_IDX 1 #define mmATTRDW 0x0030 #define mmATTRDW_BASE_IDX 1 #define mmATTRX 0x0030 #define mmATTRX_BASE_IDX 1 #define mmATTRDR 0x0030 #define mmATTRDR_BASE_IDX 1 #define mmGENMO_WT 0x0030 #define mmGENMO_WT_BASE_IDX 1 #define mmGENS0 0x0030 #define mmGENS0_BASE_IDX 1 #define mmGENENB 0x0030 #define mmGENENB_BASE_IDX 1 #define mmSEQ8_IDX 0x0031 #define mmSEQ8_IDX_BASE_IDX 1 #define mmSEQ8_DATA 0x0031 #define mmSEQ8_DATA_BASE_IDX 1 #define mmDAC_MASK 0x0031 #define mmDAC_MASK_BASE_IDX 1 #define mmDAC_R_INDEX 0x0031 #define mmDAC_R_INDEX_BASE_IDX 1 #define mmDAC_W_INDEX 0x0032 #define mmDAC_W_INDEX_BASE_IDX 1 #define mmDAC_DATA 0x0032 #define mmDAC_DATA_BASE_IDX 1 #define mmGENFC_RD 0x0032 #define mmGENFC_RD_BASE_IDX 1 #define mmGENMO_RD 0x0033 #define mmGENMO_RD_BASE_IDX 1 #define mmGRPH8_IDX 0x0033 #define mmGRPH8_IDX_BASE_IDX 1 #define mmGRPH8_DATA 0x0033 #define mmGRPH8_DATA_BASE_IDX 1 #define mmCRTC8_IDX_1 0x0035 #define mmCRTC8_IDX_1_BASE_IDX 1 #define mmCRTC8_DATA_1 0x0035 #define mmCRTC8_DATA_1_BASE_IDX 1 #define mmGENFC_WT_1 0x0036 #define mmGENFC_WT_1_BASE_IDX 1 #define mmGENS1_1 0x0036 #define mmGENS1_1_BASE_IDX 1 // addressBlock: dce_dc_hda_azcontroller_azdec // base address: 0x0 #define mmCORB_WRITE_POINTER 0x0000 #define mmCORB_WRITE_POINTER_BASE_IDX 0 #define mmCORB_READ_POINTER 0x0000 #define mmCORB_READ_POINTER_BASE_IDX 0 #define mmCORB_CONTROL 0x0001 #define mmCORB_CONTROL_BASE_IDX 0 #define mmCORB_STATUS 0x0001 #define mmCORB_STATUS_BASE_IDX 0 #define mmCORB_SIZE 0x0001 #define mmCORB_SIZE_BASE_IDX 0 #define mmRIRB_LOWER_BASE_ADDRESS 0x0002 #define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 #define mmRIRB_UPPER_BASE_ADDRESS 0x0003 #define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 #define mmRIRB_WRITE_POINTER 0x0004 #define mmRIRB_WRITE_POINTER_BASE_IDX 0 #define mmRESPONSE_INTERRUPT_COUNT 0x0004 #define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0 #define mmRIRB_CONTROL 0x0005 #define mmRIRB_CONTROL_BASE_IDX 0 #define mmRIRB_STATUS 0x0005 #define mmRIRB_STATUS_BASE_IDX 0 #define mmRIRB_SIZE 0x0005 #define mmRIRB_SIZE_BASE_IDX 0 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 #define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 #define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 #define mmIMMEDIATE_COMMAND_STATUS 0x0008 #define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0 #define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a #define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 #define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b #define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 #define mmWALL_CLOCK_COUNTER_ALIAS 0x074c #define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 // addressBlock: dce_dc_hda_azendpoint_azdec // base address: 0x0 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 #define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 // addressBlock: dce_dc_hda_azinputendpoint_azdec // base address: 0x0 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 #define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 // addressBlock: dce_dc_hda_azroot_azdec // base address: 0x0 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 #define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 // addressBlock: dce_dc_hda_azstream0_azdec // base address: 0x0 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BA #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x00 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BAS #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x00 #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BAS #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_AL #define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_AL // addressBlock: dce_dc_hda_azstream1_azdec // base address: 0x20 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BA #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x00 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BAS #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x00 #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BAS #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_AL #define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_AL // addressBlock: dce_dc_hda_azstream2_azdec // base address: 0x40 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BA #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x00 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BAS #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x00 #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BAS #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_AL #define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_AL // addressBlock: dce_dc_hda_azstream3_azdec // base address: 0x60 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BA #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x00 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BAS #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x00 #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BAS #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_AL #define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_AL // addressBlock: dce_dc_hda_azstream4_azdec // base address: 0x80 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BA #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x00 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BAS #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x00 #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BAS #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_AL #define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_AL // addressBlock: dce_dc_hda_azstream5_azdec // base address: 0xa0 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BA #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x00 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BAS #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x00 #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BAS #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_AL #define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_AL // addressBlock: dce_dc_hda_azstream6_azdec // base address: 0xc0 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BA #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x00 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BAS #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x00 #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BAS #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_AL #define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_AL // addressBlock: dce_dc_hda_azstream7_azdec // base address: 0xe0 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BA #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x00 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BAS #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x00 #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BAS #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_AL #define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_AL // addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] // base address: 0x48 //#define mmVGA_VGA_MEM_WRITE_PAGE_ADDR 0x0000 //#define mmVGA_VGA_MEM_READ_PAGE_ADDR 0x0001 // addressBlock: dce_dc_mmhubbub_vga_dispdec // base address: 0x0 //#define mmVGA_VGA_MEM_WRITE_PAGE_ADDR 0x0000 //#define mmVGA_VGA_MEM_READ_PAGE_ADDR 0x0001 #define mmVGA_RENDER_CONTROL 0x0000 #define mmVGA_RENDER_CONTROL_BASE_IDX 1 #define mmVGA_SEQUENCER_RESET_CONTROL 0x0001 #define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 #define mmVGA_MODE_CONTROL 0x0002 #define mmVGA_MODE_CONTROL_BASE_IDX 1 #define mmVGA_SURFACE_PITCH_SELECT 0x0003 #define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 #define mmVGA_MEMORY_BASE_ADDRESS 0x0004 #define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 #define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006 #define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 #define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008 #define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 #define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 #define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 #define mmVGA_HDP_CONTROL 0x000a #define mmVGA_HDP_CONTROL_BASE_IDX 1 #define mmVGA_CACHE_CONTROL 0x000b #define mmVGA_CACHE_CONTROL_BASE_IDX 1 #define mmD1VGA_CONTROL 0x000c #define mmD1VGA_CONTROL_BASE_IDX 1 #define mmD2VGA_CONTROL 0x000e #define mmD2VGA_CONTROL_BASE_IDX 1 #define mmVGA_STATUS 0x0010 #define mmVGA_STATUS_BASE_IDX 1 #define mmVGA_INTERRUPT_CONTROL 0x0011 #define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1 #define mmVGA_STATUS_CLEAR 0x0012 #define mmVGA_STATUS_CLEAR_BASE_IDX 1 #define mmVGA_INTERRUPT_STATUS 0x0013 #define mmVGA_INTERRUPT_STATUS_BASE_IDX 1 #define mmVGA_MAIN_CONTROL 0x0014 #define mmVGA_MAIN_CONTROL_BASE_IDX 1 #define mmVGA_TEST_CONTROL 0x0015 #define mmVGA_TEST_CONTROL_BASE_IDX 1 #define mmVGA_QOS_CTRL 0x0018 #define mmVGA_QOS_CTRL_BASE_IDX 1 //#define mmVGA_CRTC8_IDX 0x002d //#define mmVGA_CRTC8_DATA 0x002d //#define mmVGA_GENFC_WT 0x002e //#define mmVGA_GENS1 0x002e //#define mmVGA_ATTRDW 0x0030 //#define mmVGA_ATTRX 0x0030 //#define mmVGA_ATTRDR 0x0030 //#define mmVGA_GENMO_WT 0x0030 //#define mmVGA_GENS0 0x0030 //#define mmVGA_GENENB 0x0030 //#define mmVGA_SEQ8_IDX 0x0031 //#define mmVGA_SEQ8_DATA 0x0031 //#define mmVGA_DAC_MASK 0x0031 //#define mmVGA_DAC_R_INDEX 0x0031 //#define mmVGA_DAC_W_INDEX 0x0032 //#define mmVGA_DAC_DATA 0x0032 //#define mmVGA_GENFC_RD 0x0032 //#define mmVGA_GENMO_RD 0x0033 //#define mmVGA_GRPH8_IDX 0x0033 //#define mmVGA_GRPH8_DATA 0x0033 //#define mmVGA_CRTC8_IDX_1 0x0035 //#define mmVGA_CRTC8_DATA_1 0x0035 //#define mmVGA_GENFC_WT_1 0x0036 //#define mmVGA_GENS1_1 0x0036 #define mmD3VGA_CONTROL 0x0038 #define mmD3VGA_CONTROL_BASE_IDX 1 #define mmD4VGA_CONTROL 0x0039 #define mmD4VGA_CONTROL_BASE_IDX 1 #define mmD5VGA_CONTROL 0x003a #define mmD5VGA_CONTROL_BASE_IDX 1 #define mmD6VGA_CONTROL 0x003b #define mmD6VGA_CONTROL_BASE_IDX 1 #define mmVGA_SOURCE_SELECT 0x003c #define mmVGA_SOURCE_SELECT_BASE_IDX 1 // addressBlock: dce_dc_dccg_dccg_dispdec // base address: 0x0 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 #define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 #define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 #define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 #define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 #define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 #define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 #define mmDP_DTO_DBUF_EN 0x0044 #define mmDP_DTO_DBUF_EN_BASE_IDX 1 #define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 #define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 #define mmREFCLK_CNTL 0x0049 #define mmREFCLK_CNTL_BASE_IDX 1 #define mmMIPI_CLK_CNTL 0x004a #define mmMIPI_CLK_CNTL_BASE_IDX 1 #define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b #define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 #define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c #define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 #define mmDCCG_PERFMON_CNTL2 0x004e #define mmDCCG_PERFMON_CNTL2_BASE_IDX 1 #define mmDSICLK_CGTT_BLK_CTRL_REG 0x004f #define mmDSICLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 #define mmDCCG_CBUS_WRCMD_DELAY 0x0050 #define mmDCCG_CBUS_WRCMD_DELAY_BASE_IDX 1 #define mmDCCG_DS_DTO_INCR 0x0053 #define mmDCCG_DS_DTO_INCR_BASE_IDX 1 #define mmDCCG_DS_DTO_MODULO 0x0054 #define mmDCCG_DS_DTO_MODULO_BASE_IDX 1 #define mmDCCG_DS_CNTL 0x0055 #define mmDCCG_DS_CNTL_BASE_IDX 1 #define mmDCCG_DS_HW_CAL_INTERVAL 0x0056 #define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 #define mmSYMCLKG_CLOCK_ENABLE 0x0057 #define mmSYMCLKG_CLOCK_ENABLE_BASE_IDX 1 #define mmDPREFCLK_CNTL 0x0058 #define mmDPREFCLK_CNTL_BASE_IDX 1 #define mmAOMCLK0_CNTL 0x0059 #define mmAOMCLK0_CNTL_BASE_IDX 1 #define mmAOMCLK1_CNTL 0x005a #define mmAOMCLK1_CNTL_BASE_IDX 1 #define mmAOMCLK2_CNTL 0x005b #define mmAOMCLK2_CNTL_BASE_IDX 1 #define mmDCCG_AUDIO_DTO2_PHASE 0x005c #define mmDCCG_AUDIO_DTO2_PHASE_BASE_IDX 1 #define mmDCCG_AUDIO_DTO2_MODULO 0x005d #define mmDCCG_AUDIO_DTO2_MODULO_BASE_IDX 1 #define mmDCE_VERSION 0x005e #define mmDCE_VERSION_BASE_IDX 1 #define mmPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f #define mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1 #define mmDCCG_GTC_CNTL 0x0060 #define mmDCCG_GTC_CNTL_BASE_IDX 1 #define mmDCCG_GTC_DTO_INCR 0x0061 #define mmDCCG_GTC_DTO_INCR_BASE_IDX 1 #define mmDCCG_GTC_DTO_MODULO 0x0062 #define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1 #define mmDCCG_GTC_CURRENT 0x0063 #define mmDCCG_GTC_CURRENT_BASE_IDX 1 #define mmMIPI_DTO_CNTL 0x0065 #define mmMIPI_DTO_CNTL_BASE_IDX 1 #define mmMIPI_DTO_PHASE 0x0066 #define mmMIPI_DTO_PHASE_BASE_IDX 1 #define mmMIPI_DTO_MODULO 0x0067 #define mmMIPI_DTO_MODULO_BASE_IDX 1 #define mmDAC_CLK_ENABLE 0x0068 #define mmDAC_CLK_ENABLE_BASE_IDX 1 #define mmDVO_CLK_ENABLE 0x0069 #define mmDVO_CLK_ENABLE_BASE_IDX 1 #define mmAVSYNC_COUNTER_WRITE 0x006a #define mmAVSYNC_COUNTER_WRITE_BASE_IDX 1 #define mmAVSYNC_COUNTER_CONTROL 0x006b #define mmAVSYNC_COUNTER_CONTROL_BASE_IDX 1 #define mmAVSYNC_COUNTER_READ 0x006f #define mmAVSYNC_COUNTER_READ_BASE_IDX 1 #define mmMILLISECOND_TIME_BASE_DIV 0x0070 #define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 #define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071 #define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 #define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 #define mmDCCG_PERFMON_CNTL 0x0073 #define mmDCCG_PERFMON_CNTL_BASE_IDX 1 #define mmDCCG_GATE_DISABLE_CNTL 0x0074 #define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 #define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075 #define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 #define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076 #define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 #define mmDCCG_CAC_STATUS 0x0077 #define mmDCCG_CAC_STATUS_BASE_IDX 1 #define mmPIXCLK1_RESYNC_CNTL 0x0078 #define mmPIXCLK1_RESYNC_CNTL_BASE_IDX 1 #define mmPIXCLK2_RESYNC_CNTL 0x0079 #define mmPIXCLK2_RESYNC_CNTL_BASE_IDX 1 #define mmPIXCLK0_RESYNC_CNTL 0x007a #define mmPIXCLK0_RESYNC_CNTL_BASE_IDX 1 #define mmMICROSECOND_TIME_BASE_DIV 0x007b #define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 #define mmDCCG_GATE_DISABLE_CNTL2 0x007c #define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 #define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d #define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 #define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e #define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1 #define mmDCCG_DISP_CNTL_REG 0x007f #define mmDCCG_DISP_CNTL_REG_BASE_IDX 1 #define mmOTG0_PIXEL_RATE_CNTL 0x0080 #define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 #define mmDP_DTO0_PHASE 0x0081 #define mmDP_DTO0_PHASE_BASE_IDX 1 #define mmDP_DTO0_MODULO 0x0082 #define mmDP_DTO0_MODULO_BASE_IDX 1 #define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 #define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 #define mmOTG1_PIXEL_RATE_CNTL 0x0084 #define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 #define mmDP_DTO1_PHASE 0x0085 #define mmDP_DTO1_PHASE_BASE_IDX 1 #define mmDP_DTO1_MODULO 0x0086 #define mmDP_DTO1_MODULO_BASE_IDX 1 #define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 #define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 #define mmOTG2_PIXEL_RATE_CNTL 0x0088 #define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 #define mmDP_DTO2_PHASE 0x0089 #define mmDP_DTO2_PHASE_BASE_IDX 1 #define mmDP_DTO2_MODULO 0x008a #define mmDP_DTO2_MODULO_BASE_IDX 1 #define mmOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b #define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 #define mmOTG3_PIXEL_RATE_CNTL 0x008c #define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 #define mmDP_DTO3_PHASE 0x008d #define mmDP_DTO3_PHASE_BASE_IDX 1 #define mmDP_DTO3_MODULO 0x008e #define mmDP_DTO3_MODULO_BASE_IDX 1 #define mmOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f #define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 #define mmOTG4_PIXEL_RATE_CNTL 0x0090 #define mmOTG4_PIXEL_RATE_CNTL_BASE_IDX 1 #define mmDP_DTO4_PHASE 0x0091 #define mmDP_DTO4_PHASE_BASE_IDX 1 #define mmDP_DTO4_MODULO 0x0092 #define mmDP_DTO4_MODULO_BASE_IDX 1 #define mmOTG4_PHYPLL_PIXEL_RATE_CNTL 0x0093 #define mmOTG4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 #define mmOTG5_PIXEL_RATE_CNTL 0x0094 #define mmOTG5_PIXEL_RATE_CNTL_BASE_IDX 1 #define mmDP_DTO5_PHASE 0x0095 #define mmDP_DTO5_PHASE_BASE_IDX 1 #define mmDP_DTO5_MODULO 0x0096 #define mmDP_DTO5_MODULO_BASE_IDX 1 #define mmOTG5_PHYPLL_PIXEL_RATE_CNTL 0x0097 #define mmOTG5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 #define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098 #define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 #define mmSYMCLKA_CLOCK_ENABLE 0x00a0 #define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 #define mmSYMCLKB_CLOCK_ENABLE 0x00a1 #define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 #define mmSYMCLKC_CLOCK_ENABLE 0x00a2 #define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 #define mmSYMCLKD_CLOCK_ENABLE 0x00a3 #define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 #define mmSYMCLKE_CLOCK_ENABLE 0x00a4 #define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 #define mmSYMCLKF_CLOCK_ENABLE 0x00a5 #define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1 #define mmDCCG_SOFT_RESET 0x00a6 #define mmDCCG_SOFT_RESET_BASE_IDX 1 #define mmDVOACLKD_CNTL 0x00a8 #define mmDVOACLKD_CNTL_BASE_IDX 1 #define mmDVOACLKC_MVP_CNTL 0x00a9 #define mmDVOACLKC_MVP_CNTL_BASE_IDX 1 #define mmDVOACLKC_CNTL 0x00aa #define mmDVOACLKC_CNTL_BASE_IDX 1 #define mmDCCG_AUDIO_DTO_SOURCE 0x00ab #define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 #define mmDCCG_AUDIO_DTO0_PHASE 0x00ac #define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 #define mmDCCG_AUDIO_DTO0_MODULE 0x00ad #define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 #define mmDCCG_AUDIO_DTO1_PHASE 0x00ae #define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 #define mmDCCG_AUDIO_DTO1_MODULE 0x00af #define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 #define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 #define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 #define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 #define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 #define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 #define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 #define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 #define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 #define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 #define mmDCCG_VSYNC_CNT_CTRL 0x00b8 #define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 #define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9 #define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 #define mmDCCG_TEST_CLK_SEL 0x00be #define mmDCCG_TEST_CLK_SEL_BASE_IDX 1 // addressBlock: dce_dc_dccg_dccg_dfs_dispdec // base address: 0x0 #define mmDENTIST_DISPCLK_CNTL 0x0064 #define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1 // addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec // base address: 0x0 #define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 #define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 #define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 #define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 #define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0002 #define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 #define mmDC_PERFMON0_PERFMON_CNTL 0x0003 #define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 #define mmDC_PERFMON0_PERFMON_CNTL2 0x0004 #define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 #define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 #define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 #define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 #define mmDC_PERFMON0_PERFMON_HI 0x0007 #define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2 #define mmDC_PERFMON0_PERFMON_LOW 0x0008 #define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 // addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec // base address: 0x30 #define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x000c #define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 #define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d #define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 #define mmDC_PERFMON1_PERFCOUNTER_STATE 0x000e #define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 #define mmDC_PERFMON1_PERFMON_CNTL 0x000f #define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 #define mmDC_PERFMON1_PERFMON_CNTL2 0x0010 #define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011 #define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 #define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012 #define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 #define mmDC_PERFMON1_PERFMON_HI 0x0013 #define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2 #define mmDC_PERFMON1_PERFMON_LOW 0x0014 #define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 // addressBlock: dce_dc_dccg_dccg_pll_dispdec // base address: 0x0 #define mmPLL_MACRO_CNTL_RESERVED0 0x0018 #define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED1 0x0019 #define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED2 0x001a #define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED3 0x001b #define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED4 0x001c #define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED5 0x001d #define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED6 0x001e #define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED7 0x001f #define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED8 0x0020 #define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED9 0x0021 #define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED10 0x0022 #define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED11 0x0023 #define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED12 0x0024 #define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED13 0x0025 #define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED14 0x0026 #define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED15 0x0027 #define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED16 0x0028 #define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED17 0x0029 #define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED18 0x002a #define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED19 0x002b #define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED20 0x002c #define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED21 0x002d #define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED22 0x002e #define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED23 0x002f #define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED24 0x0030 #define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED25 0x0031 #define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED26 0x0032 #define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED27 0x0033 #define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED28 0x0034 #define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED29 0x0035 #define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED30 0x0036 #define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED31 0x0037 #define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED32 0x0038 #define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED33 0x0039 #define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED34 0x003a #define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED35 0x003b #define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED36 0x003c #define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED37 0x003d #define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED38 0x003e #define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED39 0x003f #define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED40 0x0040 #define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX 2 #define mmPLL_MACRO_CNTL_RESERVED41 0x0041 #define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX 2 // addressBlock: dce_dc_dmu_rbbmif_dispdec // base address: 0x0 #define mmRBBMIF_TIMEOUT 0x0055 #define mmRBBMIF_TIMEOUT_BASE_IDX 2 #define mmRBBMIF_STATUS 0x0056 #define mmRBBMIF_STATUS_BASE_IDX 2 #define mmRBBMIF_INT_STATUS 0x0057 #define mmRBBMIF_INT_STATUS_BASE_IDX 2 #define mmRBBMIF_TIMEOUT_DIS 0x0058 #define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2 #define mmRBBMIF_STATUS_FLAG 0x0059 #define mmRBBMIF_STATUS_FLAG_BASE_IDX 2 // addressBlock: dce_dc_dmu_dc_pg_dispdec // base address: 0x0 #define mmDOMAIN0_PG_CONFIG 0x008a #define mmDOMAIN0_PG_CONFIG_BASE_IDX 2 #define mmDOMAIN0_PG_STATUS 0x008b #define mmDOMAIN0_PG_STATUS_BASE_IDX 2 #define mmDOMAIN1_PG_CONFIG 0x008c #define mmDOMAIN1_PG_CONFIG_BASE_IDX 2 #define mmDOMAIN1_PG_STATUS 0x008d #define mmDOMAIN1_PG_STATUS_BASE_IDX 2 #define mmDOMAIN2_PG_CONFIG 0x008e #define mmDOMAIN2_PG_CONFIG_BASE_IDX 2 #define mmDOMAIN2_PG_STATUS 0x008f #define mmDOMAIN2_PG_STATUS_BASE_IDX 2 #define mmDOMAIN3_PG_CONFIG 0x0090 #define mmDOMAIN3_PG_CONFIG_BASE_IDX 2 #define mmDOMAIN3_PG_STATUS 0x0091 #define mmDOMAIN3_PG_STATUS_BASE_IDX 2 #define mmDOMAIN4_PG_CONFIG 0x0092 #define mmDOMAIN4_PG_CONFIG_BASE_IDX 2 #define mmDOMAIN4_PG_STATUS 0x0093 #define mmDOMAIN4_PG_STATUS_BASE_IDX 2 #define mmDOMAIN5_PG_CONFIG 0x0094 #define mmDOMAIN5_PG_CONFIG_BASE_IDX 2 #define mmDOMAIN5_PG_STATUS 0x0095 #define mmDOMAIN5_PG_STATUS_BASE_IDX 2 #define mmDOMAIN6_PG_CONFIG 0x0096 #define mmDOMAIN6_PG_CONFIG_BASE_IDX 2 #define mmDOMAIN6_PG_STATUS 0x0097 #define mmDOMAIN6_PG_STATUS_BASE_IDX 2 #define mmDOMAIN7_PG_CONFIG 0x0098 #define mmDOMAIN7_PG_CONFIG_BASE_IDX 2 #define mmDOMAIN7_PG_STATUS 0x0099 #define mmDOMAIN7_PG_STATUS_BASE_IDX 2 #define mmDOMAIN8_PG_CONFIG 0x009a #define mmDOMAIN8_PG_CONFIG_BASE_IDX 2 #define mmDOMAIN8_PG_STATUS 0x009b #define mmDOMAIN8_PG_STATUS_BASE_IDX 2 #define mmDOMAIN9_PG_CONFIG 0x009c #define mmDOMAIN9_PG_CONFIG_BASE_IDX 2 #define mmDOMAIN9_PG_STATUS 0x009d #define mmDOMAIN9_PG_STATUS_BASE_IDX 2 #define mmDOMAIN10_PG_CONFIG 0x009e #define mmDOMAIN10_PG_CONFIG_BASE_IDX 2 #define mmDOMAIN10_PG_STATUS 0x009f #define mmDOMAIN10_PG_STATUS_BASE_IDX 2 #define mmDOMAIN11_PG_CONFIG 0x00a0 #define mmDOMAIN11_PG_CONFIG_BASE_IDX 2 #define mmDOMAIN11_PG_STATUS 0x00a1 #define mmDOMAIN11_PG_STATUS_BASE_IDX 2 #define mmDOMAIN12_PG_CONFIG 0x00a2 #define mmDOMAIN12_PG_CONFIG_BASE_IDX 2 #define mmDOMAIN12_PG_STATUS 0x00a3 #define mmDOMAIN12_PG_STATUS_BASE_IDX 2 #define mmDOMAIN13_PG_CONFIG 0x00a4 #define mmDOMAIN13_PG_CONFIG_BASE_IDX 2 #define mmDOMAIN13_PG_STATUS 0x00a5 #define mmDOMAIN13_PG_STATUS_BASE_IDX 2 #define mmDOMAIN14_PG_CONFIG 0x00a6 #define mmDOMAIN14_PG_CONFIG_BASE_IDX 2 #define mmDOMAIN14_PG_STATUS 0x00a7 #define mmDOMAIN14_PG_STATUS_BASE_IDX 2 #define mmDOMAIN15_PG_CONFIG 0x00a8 #define mmDOMAIN15_PG_CONFIG_BASE_IDX 2 #define mmDOMAIN15_PG_STATUS 0x00a9 #define mmDOMAIN15_PG_STATUS_BASE_IDX 2 #define mmDCPG_INTERRUPT_STATUS 0x00aa #define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2 #define mmDCPG_INTERRUPT_CONTROL_1 0x00ab #define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 #define mmDCPG_INTERRUPT_CONTROL_2 0x00ac #define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2 #define mmDC_IP_REQUEST_CNTL 0x00ad #define mmDC_IP_REQUEST_CNTL_BASE_IDX 2 #define mmDC_PGCNTL_STATUS_REG 0x00ae #define mmDC_PGCNTL_STATUS_REG_BASE_IDX 2 // addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec // base address: 0x2f8 #define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x00be #define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 #define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf #define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 #define mmDC_PERFMON2_PERFCOUNTER_STATE 0x00c0 #define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 #define mmDC_PERFMON2_PERFMON_CNTL 0x00c1 #define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 #define mmDC_PERFMON2_PERFMON_CNTL2 0x00c2 #define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3 #define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 #define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4 #define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 #define mmDC_PERFMON2_PERFMON_HI 0x00c5 #define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2 #define mmDC_PERFMON2_PERFMON_LOW 0x00c6 #define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 // addressBlock: dce_dc_dmu_dmu_misc_dispdec // base address: 0x0 #define mmCC_DC_PIPE_DIS 0x00ca #define mmCC_DC_PIPE_DIS_BASE_IDX 2 #define mmDMU_CLK_CNTL 0x00cb #define mmDMU_CLK_CNTL_BASE_IDX 2 #define mmDMU_MEM_PWR_CNTL 0x00cc #define mmDMU_MEM_PWR_CNTL_BASE_IDX 2 #define mmDMCU_SMU_INTERRUPT_CNTL 0x00cd #define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2 #define mmSMU_INTERRUPT_CONTROL 0x00ce #define mmSMU_INTERRUPT_CONTROL_BASE_IDX 2 // addressBlock: dce_dc_dmu_dmcu_dispdec // base address: 0x0 #define mmDMCU_CTRL 0x00da #define mmDMCU_CTRL_BASE_IDX 2 #define mmDMCU_STATUS 0x00db #define mmDMCU_STATUS_BASE_IDX 2 #define mmDMCU_PC_START_ADDR 0x00dc #define mmDMCU_PC_START_ADDR_BASE_IDX 2 #define mmDMCU_FW_START_ADDR 0x00dd #define mmDMCU_FW_START_ADDR_BASE_IDX 2 #define mmDMCU_FW_END_ADDR 0x00de #define mmDMCU_FW_END_ADDR_BASE_IDX 2 #define mmDMCU_FW_ISR_START_ADDR 0x00df #define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2 #define mmDMCU_FW_CS_HI 0x00e0 #define mmDMCU_FW_CS_HI_BASE_IDX 2 #define mmDMCU_FW_CS_LO 0x00e1 #define mmDMCU_FW_CS_LO_BASE_IDX 2 #define mmDMCU_RAM_ACCESS_CTRL 0x00e2 #define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2 #define mmDMCU_ERAM_WR_CTRL 0x00e3 #define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2 #define mmDMCU_ERAM_WR_DATA 0x00e4 #define mmDMCU_ERAM_WR_DATA_BASE_IDX 2 #define mmDMCU_ERAM_RD_CTRL 0x00e5 #define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2 #define mmDMCU_ERAM_RD_DATA 0x00e6 #define mmDMCU_ERAM_RD_DATA_BASE_IDX 2 #define mmDMCU_IRAM_WR_CTRL 0x00e7 #define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2 #define mmDMCU_IRAM_WR_DATA 0x00e8 #define mmDMCU_IRAM_WR_DATA_BASE_IDX 2 #define mmDMCU_IRAM_RD_CTRL 0x00e9 #define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2 #define mmDMCU_IRAM_RD_DATA 0x00ea #define mmDMCU_IRAM_RD_DATA_BASE_IDX 2 #define mmDMCU_EVENT_TRIGGER 0x00eb #define mmDMCU_EVENT_TRIGGER_BASE_IDX 2 #define mmDMCU_UC_INTERNAL_INT_STATUS 0x00ec #define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2 #define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed #define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2 #define mmDMCU_INTERRUPT_STATUS 0x00ee #define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2 #define mmDMCU_INTERRUPT_STATUS_1 0x00ef #define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2 #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0 #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2 #define mmDC_DMCU_SCRATCH 0x00f5 #define mmDC_DMCU_SCRATCH_BASE_IDX 2 #define mmDMCU_INT_CNT 0x00f6 #define mmDMCU_INT_CNT_BASE_IDX 2 #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7 #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2 #define mmDMCU_UC_CLK_GATING_CNTL 0x00f8 #define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2 #define mmMASTER_COMM_DATA_REG1 0x00f9 #define mmMASTER_COMM_DATA_REG1_BASE_IDX 2 #define mmMASTER_COMM_DATA_REG2 0x00fa #define mmMASTER_COMM_DATA_REG2_BASE_IDX 2 #define mmMASTER_COMM_DATA_REG3 0x00fb #define mmMASTER_COMM_DATA_REG3_BASE_IDX 2 #define mmMASTER_COMM_CMD_REG 0x00fc #define mmMASTER_COMM_CMD_REG_BASE_IDX 2 #define mmMASTER_COMM_CNTL_REG 0x00fd #define mmMASTER_COMM_CNTL_REG_BASE_IDX 2 #define mmSLAVE_COMM_DATA_REG1 0x00fe #define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2 #define mmSLAVE_COMM_DATA_REG2 0x00ff #define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2 #define mmSLAVE_COMM_DATA_REG3 0x0100 #define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2 #define mmSLAVE_COMM_CMD_REG 0x0101 #define mmSLAVE_COMM_CMD_REG_BASE_IDX 2 #define mmSLAVE_COMM_CNTL_REG 0x0102 #define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2 #define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x0105 #define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2 #define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x0106 #define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2 #define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x0107 #define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2 #define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x0108 #define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2 #define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x0109 #define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e #define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113 #define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2 #define mmDMCU_DPRX_INTERRUPT_STATUS1 0x0114 #define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2 #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115 #define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116 #define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 #define mmDMCU_INTERRUPT_STATUS_CONTINUE 0x0119 #define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a #define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2 #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2 #define mmDMCU_INT_CNT_CONTINUE 0x011c #define mmDMCU_INT_CNT_CONTINUE_BASE_IDX 2 // addressBlock: dce_dc_dmu_ihc_dispdec // base address: 0x0 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 #define mmDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 #define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 #define mmDC_GPU_TIMER_READ 0x0128 #define mmDC_GPU_TIMER_READ_BASE_IDX 2 #define mmDC_GPU_TIMER_READ_CNTL 0x0129 #define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS 0x012a #define mmDISP_INTERRUPT_STATUS_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE 0x012b #define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x012c #define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x012d #define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x012e #define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x012f #define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 #define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 #define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 #define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 #define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 #define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 #define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 #define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 #define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 #define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 #define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE16 0x013a #define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE17 0x013b #define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE18 0x013c #define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE19 0x013d #define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE20 0x013e #define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE21 0x013f #define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 #define mmDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 #define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 #define mmDC_GPU_TIMER_START_POSITION_VREADY 0x0141 #define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 #define mmDC_GPU_TIMER_START_POSITION_FLIP 0x0142 #define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 #define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 #define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 // addressBlock: dce_dc_wb0_dispdec_cnv_dispdec // base address: 0x0 #define mmCNV0_WB_ENABLE 0x01da #define mmCNV0_WB_ENABLE_BASE_IDX 2 #define mmCNV0_WB_EC_CONFIG 0x01db #define mmCNV0_WB_EC_CONFIG_BASE_IDX 2 #define mmCNV0_CNV_MODE 0x01dc #define mmCNV0_CNV_MODE_BASE_IDX 2 #define mmCNV0_CNV_WINDOW_START 0x01dd #define mmCNV0_CNV_WINDOW_START_BASE_IDX 2 #define mmCNV0_CNV_WINDOW_SIZE 0x01de #define mmCNV0_CNV_WINDOW_SIZE_BASE_IDX 2 #define mmCNV0_CNV_UPDATE 0x01df #define mmCNV0_CNV_UPDATE_BASE_IDX 2 #define mmCNV0_CNV_SOURCE_SIZE 0x01e0 #define mmCNV0_CNV_SOURCE_SIZE_BASE_IDX 2 #define mmCNV0_CNV_CSC_CONTROL 0x01e1 #define mmCNV0_CNV_CSC_CONTROL_BASE_IDX 2 #define mmCNV0_CNV_CSC_C11_C12 0x01e2 #define mmCNV0_CNV_CSC_C11_C12_BASE_IDX 2 #define mmCNV0_CNV_CSC_C13_C14 0x01e3 #define mmCNV0_CNV_CSC_C13_C14_BASE_IDX 2 #define mmCNV0_CNV_CSC_C21_C22 0x01e4 #define mmCNV0_CNV_CSC_C21_C22_BASE_IDX 2 #define mmCNV0_CNV_CSC_C23_C24 0x01e5 #define mmCNV0_CNV_CSC_C23_C24_BASE_IDX 2 #define mmCNV0_CNV_CSC_C31_C32 0x01e6 #define mmCNV0_CNV_CSC_C31_C32_BASE_IDX 2 #define mmCNV0_CNV_CSC_C33_C34 0x01e7 #define mmCNV0_CNV_CSC_C33_C34_BASE_IDX 2 #define mmCNV0_CNV_CSC_ROUND_OFFSET_R 0x01e8 #define mmCNV0_CNV_CSC_ROUND_OFFSET_R_BASE_IDX 2 #define mmCNV0_CNV_CSC_ROUND_OFFSET_G 0x01e9 #define mmCNV0_CNV_CSC_ROUND_OFFSET_G_BASE_IDX 2 #define mmCNV0_CNV_CSC_ROUND_OFFSET_B 0x01ea #define mmCNV0_CNV_CSC_ROUND_OFFSET_B_BASE_IDX 2 #define mmCNV0_CNV_CSC_CLAMP_R 0x01eb #define mmCNV0_CNV_CSC_CLAMP_R_BASE_IDX 2 #define mmCNV0_CNV_CSC_CLAMP_G 0x01ec #define mmCNV0_CNV_CSC_CLAMP_G_BASE_IDX 2 #define mmCNV0_CNV_CSC_CLAMP_B 0x01ed #define mmCNV0_CNV_CSC_CLAMP_B_BASE_IDX 2 #define mmCNV0_CNV_TEST_CNTL 0x01ee #define mmCNV0_CNV_TEST_CNTL_BASE_IDX 2 #define mmCNV0_CNV_TEST_CRC_RED 0x01ef #define mmCNV0_CNV_TEST_CRC_RED_BASE_IDX 2 #define mmCNV0_CNV_TEST_CRC_GREEN 0x01f0 #define mmCNV0_CNV_TEST_CRC_GREEN_BASE_IDX 2 #define mmCNV0_CNV_TEST_CRC_BLUE 0x01f1 #define mmCNV0_CNV_TEST_CRC_BLUE_BASE_IDX 2 #define mmCNV0_CNV_INPUT_SELECT 0x01f5 #define mmCNV0_CNV_INPUT_SELECT_BASE_IDX 2 #define mmCNV0_WB_SOFT_RESET 0x01f8 #define mmCNV0_WB_SOFT_RESET_BASE_IDX 2 #define mmCNV0_WB_WARM_UP_MODE_CTL1 0x01f9 #define mmCNV0_WB_WARM_UP_MODE_CTL1_BASE_IDX 2 #define mmCNV0_WB_WARM_UP_MODE_CTL2 0x01fa #define mmCNV0_WB_WARM_UP_MODE_CTL2_BASE_IDX 2 // addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec // base address: 0x0 #define mmWBSCL0_WBSCL_COEF_RAM_SELECT 0x020a #define mmWBSCL0_WBSCL_COEF_RAM_SELECT_BASE_IDX 2 #define mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA 0x020b #define mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2 #define mmWBSCL0_WBSCL_MODE 0x020c #define mmWBSCL0_WBSCL_MODE_BASE_IDX 2 #define mmWBSCL0_WBSCL_TAP_CONTROL 0x020d #define mmWBSCL0_WBSCL_TAP_CONTROL_BASE_IDX 2 #define mmWBSCL0_WBSCL_DEST_SIZE 0x020e #define mmWBSCL0_WBSCL_DEST_SIZE_BASE_IDX 2 #define mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO 0x020f #define mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 #define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB 0x0210 #define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2 #define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR 0x0211 #define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2 #define mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO 0x0212 #define mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 #define mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB 0x0213 #define mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2 #define mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR 0x0214 #define mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2 #define mmWBSCL0_WBSCL_ROUND_OFFSET 0x0215 #define mmWBSCL0_WBSCL_ROUND_OFFSET_BASE_IDX 2 #define mmWBSCL0_WBSCL_CLAMP 0x0216 #define mmWBSCL0_WBSCL_CLAMP_BASE_IDX 2 #define mmWBSCL0_WBSCL_OVERFLOW_STATUS 0x0217 #define mmWBSCL0_WBSCL_OVERFLOW_STATUS_BASE_IDX 2 #define mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS 0x0218 #define mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 #define mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY 0x0219 #define mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2 #define mmWBSCL0_WBSCL_TEST_CNTL 0x021a #define mmWBSCL0_WBSCL_TEST_CNTL_BASE_IDX 2 #define mmWBSCL0_WBSCL_TEST_CRC_RED 0x021b #define mmWBSCL0_WBSCL_TEST_CRC_RED_BASE_IDX 2 #define mmWBSCL0_WBSCL_TEST_CRC_GREEN 0x021c #define mmWBSCL0_WBSCL_TEST_CRC_GREEN_BASE_IDX 2 #define mmWBSCL0_WBSCL_TEST_CRC_BLUE 0x021d #define mmWBSCL0_WBSCL_TEST_CRC_BLUE_BASE_IDX 2 #define mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN 0x021e #define mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2 #define mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT 0x021f #define mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2 #define mmWBSCL0_WBSCL_RAM_SHUTDOWN 0x0222 #define mmWBSCL0_WBSCL_RAM_SHUTDOWN_BASE_IDX 2 // addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec // base address: 0x8e8 #define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x023a #define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 #define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x023b #define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 #define mmDC_PERFMON3_PERFCOUNTER_STATE 0x023c #define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 #define mmDC_PERFMON3_PERFMON_CNTL 0x023d #define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 #define mmDC_PERFMON3_PERFMON_CNTL2 0x023e #define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x023f #define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 #define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0240 #define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 #define mmDC_PERFMON3_PERFMON_HI 0x0241 #define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2 #define mmDC_PERFMON3_PERFMON_LOW 0x0242 #define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 // addressBlock: dce_dc_wb1_dispdec_cnv_dispdec // base address: 0x1b0 #define mmCNV1_WB_ENABLE 0x0246 #define mmCNV1_WB_ENABLE_BASE_IDX 2 #define mmCNV1_WB_EC_CONFIG 0x0247 #define mmCNV1_WB_EC_CONFIG_BASE_IDX 2 #define mmCNV1_CNV_MODE 0x0248 #define mmCNV1_CNV_MODE_BASE_IDX 2 #define mmCNV1_CNV_WINDOW_START 0x0249 #define mmCNV1_CNV_WINDOW_START_BASE_IDX 2 #define mmCNV1_CNV_WINDOW_SIZE 0x024a #define mmCNV1_CNV_WINDOW_SIZE_BASE_IDX 2 #define mmCNV1_CNV_UPDATE 0x024b #define mmCNV1_CNV_UPDATE_BASE_IDX 2 #define mmCNV1_CNV_SOURCE_SIZE 0x024c #define mmCNV1_CNV_SOURCE_SIZE_BASE_IDX 2 #define mmCNV1_CNV_CSC_CONTROL 0x024d #define mmCNV1_CNV_CSC_CONTROL_BASE_IDX 2 #define mmCNV1_CNV_CSC_C11_C12 0x024e #define mmCNV1_CNV_CSC_C11_C12_BASE_IDX 2 #define mmCNV1_CNV_CSC_C13_C14 0x024f #define mmCNV1_CNV_CSC_C13_C14_BASE_IDX 2 #define mmCNV1_CNV_CSC_C21_C22 0x0250 #define mmCNV1_CNV_CSC_C21_C22_BASE_IDX 2 #define mmCNV1_CNV_CSC_C23_C24 0x0251 #define mmCNV1_CNV_CSC_C23_C24_BASE_IDX 2 #define mmCNV1_CNV_CSC_C31_C32 0x0252 #define mmCNV1_CNV_CSC_C31_C32_BASE_IDX 2 #define mmCNV1_CNV_CSC_C33_C34 0x0253 #define mmCNV1_CNV_CSC_C33_C34_BASE_IDX 2 #define mmCNV1_CNV_CSC_ROUND_OFFSET_R 0x0254 #define mmCNV1_CNV_CSC_ROUND_OFFSET_R_BASE_IDX 2 #define mmCNV1_CNV_CSC_ROUND_OFFSET_G 0x0255 #define mmCNV1_CNV_CSC_ROUND_OFFSET_G_BASE_IDX 2 #define mmCNV1_CNV_CSC_ROUND_OFFSET_B 0x0256 #define mmCNV1_CNV_CSC_ROUND_OFFSET_B_BASE_IDX 2 #define mmCNV1_CNV_CSC_CLAMP_R 0x0257 #define mmCNV1_CNV_CSC_CLAMP_R_BASE_IDX 2 #define mmCNV1_CNV_CSC_CLAMP_G 0x0258 #define mmCNV1_CNV_CSC_CLAMP_G_BASE_IDX 2 #define mmCNV1_CNV_CSC_CLAMP_B 0x0259 #define mmCNV1_CNV_CSC_CLAMP_B_BASE_IDX 2 #define mmCNV1_CNV_TEST_CNTL 0x025a #define mmCNV1_CNV_TEST_CNTL_BASE_IDX 2 #define mmCNV1_CNV_TEST_CRC_RED 0x025b #define mmCNV1_CNV_TEST_CRC_RED_BASE_IDX 2 #define mmCNV1_CNV_TEST_CRC_GREEN 0x025c #define mmCNV1_CNV_TEST_CRC_GREEN_BASE_IDX 2 #define mmCNV1_CNV_TEST_CRC_BLUE 0x025d #define mmCNV1_CNV_TEST_CRC_BLUE_BASE_IDX 2 #define mmCNV1_CNV_INPUT_SELECT 0x0261 #define mmCNV1_CNV_INPUT_SELECT_BASE_IDX 2 #define mmCNV1_WB_SOFT_RESET 0x0264 #define mmCNV1_WB_SOFT_RESET_BASE_IDX 2 #define mmCNV1_WB_WARM_UP_MODE_CTL1 0x0265 #define mmCNV1_WB_WARM_UP_MODE_CTL1_BASE_IDX 2 #define mmCNV1_WB_WARM_UP_MODE_CTL2 0x0266 #define mmCNV1_WB_WARM_UP_MODE_CTL2_BASE_IDX 2 // addressBlock: dce_dc_wb1_dispdec_wbscl_dispdec // base address: 0x1b0 #define mmWBSCL1_WBSCL_COEF_RAM_SELECT 0x0276 #define mmWBSCL1_WBSCL_COEF_RAM_SELECT_BASE_IDX 2 #define mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA 0x0277 #define mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2 #define mmWBSCL1_WBSCL_MODE 0x0278 #define mmWBSCL1_WBSCL_MODE_BASE_IDX 2 #define mmWBSCL1_WBSCL_TAP_CONTROL 0x0279 #define mmWBSCL1_WBSCL_TAP_CONTROL_BASE_IDX 2 #define mmWBSCL1_WBSCL_DEST_SIZE 0x027a #define mmWBSCL1_WBSCL_DEST_SIZE_BASE_IDX 2 #define mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO 0x027b #define mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 #define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB 0x027c #define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2 #define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR 0x027d #define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2 #define mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO 0x027e #define mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 #define mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB 0x027f #define mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2 #define mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR 0x0280 #define mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2 #define mmWBSCL1_WBSCL_ROUND_OFFSET 0x0281 #define mmWBSCL1_WBSCL_ROUND_OFFSET_BASE_IDX 2 #define mmWBSCL1_WBSCL_CLAMP 0x0282 #define mmWBSCL1_WBSCL_CLAMP_BASE_IDX 2 #define mmWBSCL1_WBSCL_OVERFLOW_STATUS 0x0283 #define mmWBSCL1_WBSCL_OVERFLOW_STATUS_BASE_IDX 2 #define mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS 0x0284 #define mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 #define mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY 0x0285 #define mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2 #define mmWBSCL1_WBSCL_TEST_CNTL 0x0286 #define mmWBSCL1_WBSCL_TEST_CNTL_BASE_IDX 2 #define mmWBSCL1_WBSCL_TEST_CRC_RED 0x0287 #define mmWBSCL1_WBSCL_TEST_CRC_RED_BASE_IDX 2 #define mmWBSCL1_WBSCL_TEST_CRC_GREEN 0x0288 #define mmWBSCL1_WBSCL_TEST_CRC_GREEN_BASE_IDX 2 #define mmWBSCL1_WBSCL_TEST_CRC_BLUE 0x0289 #define mmWBSCL1_WBSCL_TEST_CRC_BLUE_BASE_IDX 2 #define mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN 0x028a #define mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2 #define mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT 0x028b #define mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2 #define mmWBSCL1_WBSCL_RAM_SHUTDOWN 0x028e #define mmWBSCL1_WBSCL_RAM_SHUTDOWN_BASE_IDX 2 // addressBlock: dce_dc_wb1_dispdec_wb_dcperfmon_dc_perfmon_dispdec // base address: 0xa98 #define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x02a6 #define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 #define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x02a7 #define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 #define mmDC_PERFMON4_PERFCOUNTER_STATE 0x02a8 #define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 #define mmDC_PERFMON4_PERFMON_CNTL 0x02a9 #define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 #define mmDC_PERFMON4_PERFMON_CNTL2 0x02aa #define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x02ab #define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 #define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x02ac #define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 #define mmDC_PERFMON4_PERFMON_HI 0x02ad #define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2 #define mmDC_PERFMON4_PERFMON_LOW 0x02ae #define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 // addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec // base address: 0x0 #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x02b2 #define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x02b3 #define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x02b4 #define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x02b5 #define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x02b6 #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x02b7 #define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x02b8 #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x02b9 #define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x02ba #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x02bb #define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x02bc #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x02bd #define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x02be #define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0x02bf #define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x02c2 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x02c3 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x02c4 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x02c5 #define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x02c6 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x02c7 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x02c8 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x02c9 #define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x02ca #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x02cb #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x02cc #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x02cd #define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x02ce #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x02cf #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x02d0 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x02d1 #define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x02d2 #define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02d3 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0x02d4 #define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_WATERMARK 0x02d5 #define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0x02d6 #define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0x02d7 #define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0x02d8 #define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 #define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x02d9 #define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x02db #define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 #define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x02dc #define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 // addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec // base address: 0x100 #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x02f2 #define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x02f3 #define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x02f4 #define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x02f5 #define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x02f6 #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x02f7 #define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x02f8 #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x02f9 #define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x02fa #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x02fb #define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x02fc #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x02fd #define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x02fe #define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0x02ff #define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x0302 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0303 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x0304 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0305 #define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x0306 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0307 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x0308 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0309 #define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x030a #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x030b #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x030c #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x030d #define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x030e #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x030f #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x0310 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0311 #define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x0312 #define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0313 #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0x0314 #define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_WATERMARK 0x0315 #define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0x0316 #define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0x0317 #define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0x0318 #define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 #define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0x0319 #define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0x031b #define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 #define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0x031c #define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 // addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec // base address: 0x0 #define mmWBIF0_MISC_CTRL 0x0333 #define mmWBIF0_MISC_CTRL_BASE_IDX 2 #define mmWBIF0_SMU_WM_CONTROL 0x0334 #define mmWBIF0_SMU_WM_CONTROL_BASE_IDX 2 #define mmWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0335 #define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 #define mmWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0336 #define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 #define mmWBIF1_MISC_CTRL 0x0337 #define mmWBIF1_MISC_CTRL_BASE_IDX 2 #define mmWBIF1_SMU_WM_CONTROL 0x0338 #define mmWBIF1_SMU_WM_CONTROL_BASE_IDX 2 #define mmWBIF1_PHASE0_OUTSTANDING_COUNTER 0x0339 #define mmWBIF1_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 #define mmWBIF1_PHASE1_OUTSTANDING_COUNTER 0x033a #define mmWBIF1_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 #define mmVGA_SRC_SPLIT_CNTL 0x033b #define mmVGA_SRC_SPLIT_CNTL_BASE_IDX 2 #define mmMMHUBBUB_MEM_PWR_STATUS 0x033c #define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 #define mmMMHUBBUB_MEM_PWR_CNTL 0x033d #define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 #define mmMMHUBBUB_CLOCK_CNTL 0x033e #define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 #define mmMMHUBBUB_SOFT_RESET 0x033f #define mmMMHUBBUB_SOFT_RESET_BASE_IDX 2 // addressBlock: dce_dc_mmhubbub_vgaif_dispdec // base address: 0x0 #define mmMCIF_CONTROL 0x034a #define mmMCIF_CONTROL_BASE_IDX 2 #define mmMCIF_WRITE_COMBINE_CONTROL 0x034b #define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 #define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e #define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 #define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f #define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 #define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350 #define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 // addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec // base address: 0xd48 #define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x0352 #define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 #define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x0353 #define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 #define mmDC_PERFMON5_PERFCOUNTER_STATE 0x0354 #define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 #define mmDC_PERFMON5_PERFMON_CNTL 0x0355 #define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 #define mmDC_PERFMON5_PERFMON_CNTL2 0x0356 #define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0357 #define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 #define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0358 #define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 #define mmDC_PERFMON5_PERFMON_HI 0x0359 #define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2 #define mmDC_PERFMON5_PERFMON_LOW 0x035a #define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0stream0_dispdec // base address: 0x0 #define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e #define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 #define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x035f #define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0stream1_dispdec // base address: 0x8 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 #define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 #define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 #define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0stream2_dispdec // base address: 0x10 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 #define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 #define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 #define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0stream3_dispdec // base address: 0x18 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 #define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 #define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 #define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0stream4_dispdec // base address: 0x20 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 #define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 #define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 #define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0stream5_dispdec // base address: 0x28 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 #define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 #define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 #define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0stream6_dispdec // base address: 0x30 #define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a #define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 #define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x036b #define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0stream7_dispdec // base address: 0x38 #define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c #define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 #define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x036d #define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_az_misc_dispdec // base address: 0x0 #define mmAZ_CLOCK_CNTL 0x0372 #define mmAZ_CLOCK_CNTL_BASE_IDX 2 // addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec // base address: 0xde8 #define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x037a #define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 #define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x037b #define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 #define mmDC_PERFMON6_PERFCOUNTER_STATE 0x037c #define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 #define mmDC_PERFMON6_PERFMON_CNTL 0x037d #define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 #define mmDC_PERFMON6_PERFMON_CNTL2 0x037e #define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x037f #define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 #define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x0380 #define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 #define mmDC_PERFMON6_PERFMON_HI 0x0381 #define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2 #define mmDC_PERFMON6_PERFMON_LOW 0x0382 #define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0endpoint0_dispdec // base address: 0x0 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0endpoint1_dispdec // base address: 0x18 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0endpoint2_dispdec // base address: 0x30 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0endpoint3_dispdec // base address: 0x48 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0endpoint4_dispdec // base address: 0x60 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0endpoint5_dispdec // base address: 0x78 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0endpoint6_dispdec // base address: 0x90 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab #define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0endpoint7_dispdec // base address: 0xa8 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 #define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0controller_dispdec // base address: 0x0 #define mmAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 #define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 #define mmAZALIA_AUDIO_DTO 0x03c3 #define mmAZALIA_AUDIO_DTO_BASE_IDX 2 #define mmAZALIA_AUDIO_DTO_CONTROL 0x03c4 #define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 #define mmAZALIA_SOCCLK_CONTROL 0x03c5 #define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 #define mmAZALIA_DATA_DMA_CONTROL 0x03c7 #define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 #define mmAZALIA_BDL_DMA_CONTROL 0x03c8 #define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 #define mmAZALIA_RIRB_AND_DP_CONTROL 0x03c9 #define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 #define mmAZALIA_CORB_DMA_CONTROL 0x03ca #define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1 #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 #define mmAZALIA_CYCLIC_BUFFER_SYNC 0x03d2 #define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 #define mmAZALIA_GLOBAL_CAPABILITIES 0x03d3 #define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 #define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 #define mmAZALIA_INPUT_CRC0_CONTROL0 0x03d9 #define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 #define mmAZALIA_INPUT_CRC0_CONTROL1 0x03da #define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 #define mmAZALIA_INPUT_CRC0_CONTROL2 0x03db #define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 #define mmAZALIA_INPUT_CRC0_CONTROL3 0x03dc #define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 #define mmAZALIA_INPUT_CRC0_RESULT 0x03dd #define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 #define mmAZALIA_INPUT_CRC1_CONTROL0 0x03de #define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 #define mmAZALIA_INPUT_CRC1_CONTROL1 0x03df #define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 #define mmAZALIA_INPUT_CRC1_CONTROL2 0x03e0 #define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 #define mmAZALIA_INPUT_CRC1_CONTROL3 0x03e1 #define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 #define mmAZALIA_INPUT_CRC1_RESULT 0x03e2 #define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 #define mmAZALIA_CRC0_CONTROL0 0x03e3 #define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2 #define mmAZALIA_CRC0_CONTROL1 0x03e4 #define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2 #define mmAZALIA_CRC0_CONTROL2 0x03e5 #define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2 #define mmAZALIA_CRC0_CONTROL3 0x03e6 #define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2 #define mmAZALIA_CRC0_RESULT 0x03e7 #define mmAZALIA_CRC0_RESULT_BASE_IDX 2 #define mmAZALIA_CRC1_CONTROL0 0x03e8 #define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2 #define mmAZALIA_CRC1_CONTROL1 0x03e9 #define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2 #define mmAZALIA_CRC1_CONTROL2 0x03ea #define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2 #define mmAZALIA_CRC1_CONTROL3 0x03eb #define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2 #define mmAZALIA_CRC1_RESULT 0x03ec #define mmAZALIA_CRC1_RESULT_BASE_IDX 2 #define mmAZALIA_MEM_PWR_CTRL 0x03ee #define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2 #define mmAZALIA_MEM_PWR_STATUS 0x03ef #define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0root_dispdec // base address: 0x0 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 #define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 #define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 #define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 #define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 #define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 #define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 #define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 #define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 #define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 #define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 #define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 #define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x041a #define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 #define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x041b #define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 #define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c #define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d #define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0stream8_dispdec // base address: 0x320 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 #define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 #define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 #define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0stream9_dispdec // base address: 0x328 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 #define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 #define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 #define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0stream10_dispdec // base address: 0x330 #define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a #define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 #define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x042b #define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0stream11_dispdec // base address: 0x338 #define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c #define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 #define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x042d #define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0stream12_dispdec // base address: 0x340 #define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e #define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 #define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x042f #define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0stream13_dispdec // base address: 0x348 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 #define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 #define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 #define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0stream14_dispdec // base address: 0x350 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 #define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 #define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 #define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0stream15_dispdec // base address: 0x358 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 #define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 #define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 #define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec // base address: 0x0 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b #define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec // base address: 0x10 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f #define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec // base address: 0x20 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443 #define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec // base address: 0x30 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 #define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec // base address: 0x40 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b #define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec // base address: 0x50 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f #define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec // base address: 0x60 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 #define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 // addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec // base address: 0x70 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 #define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 // addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec // base address: 0x0 #define mmDCHUBBUB_SDPIF_CFG0 0x048f #define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_CFG1 0x0490 #define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 #define mmDCHUBBUB_FORCE_IO_STATUS_0 0x0491 #define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 #define mmDCHUBBUB_FORCE_IO_STATUS_1 0x0492 #define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_FB_BASE 0x0493 #define mmDCHUBBUB_SDPIF_FB_BASE_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_FB_TOP 0x0494 #define mmDCHUBBUB_SDPIF_FB_TOP_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_FB_OFFSET 0x0495 #define mmDCHUBBUB_SDPIF_FB_OFFSET_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_AGP_BOT 0x0496 #define mmDCHUBBUB_SDPIF_AGP_BOT_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_AGP_TOP 0x0497 #define mmDCHUBBUB_SDPIF_AGP_TOP_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_AGP_BASE 0x0498 #define mmDCHUBBUB_SDPIF_AGP_BASE_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_APER_BASE 0x0499 #define mmDCHUBBUB_SDPIF_APER_BASE_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_APER_TOP 0x049a #define mmDCHUBBUB_SDPIF_APER_TOP_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_APER_DEF_0 0x049b #define mmDCHUBBUB_SDPIF_APER_DEF_0_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_APER_DEF_1 0x049c #define mmDCHUBBUB_SDPIF_APER_DEF_1_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_1 0x049e #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_1_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_W 0x049f #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_W_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_0 0x04a0 #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_0_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_0 0x04a1 #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_0_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0 0x04a2 #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0 0x04a3 #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0 0x04a4 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0 0x04a5 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_1 0x04a6 #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_1_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_1 0x04a7 #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_1_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1 0x04a8 #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1 0x04a9 #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1 0x04aa #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1 0x04ab #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_2 0x04ac #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_2_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_2 0x04ad #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_2_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2 0x04ae #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2 0x04af #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2 0x04b0 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2 0x04b1 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_3 0x04b2 #define mmDCHUBBUB_SDPIF_MARC_BASE_LO_3_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_3 0x04b3 #define mmDCHUBBUB_SDPIF_MARC_BASE_HI_3_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3 0x04b4 #define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3 0x04b5 #define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3 0x04b6 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3 0x04b7 #define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x04b8 #define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x04b9 #define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 #define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x04ba #define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 // addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec // base address: 0x0 #define mmDCHUBBUB_RET_PATH_DCC_CFG 0x04cf #define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04d0 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04d1 #define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04d2 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04d3 #define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04d4 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04d5 #define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04d6 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04d7 #define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04d8 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04d9 #define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04da #define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2 #define mmDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04db #define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04dc #define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2 #define mmDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04dd #define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04de #define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2 #define mmDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04df #define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2 #define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04e0 #define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 #define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04e1 #define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 #define mmDCHUBBUB_CRC_CTRL 0x04e2 #define mmDCHUBBUB_CRC_CTRL_BASE_IDX 2 #define mmDCHUBBUB_CRC0_VAL_R_G 0x04e3 #define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 #define mmDCHUBBUB_CRC0_VAL_B_A 0x04e4 #define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 #define mmDCHUBBUB_CRC1_VAL_R_G 0x04e5 #define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 #define mmDCHUBBUB_CRC1_VAL_B_A 0x04e6 #define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 // addressBlock: dce_dc_dchubbub_hubbub_dispdec // base address: 0x0 #define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x0505 #define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 #define mmDCHUBBUB_ARB_SAT_LEVEL 0x0506 #define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 #define mmDCHUBBUB_ARB_QOS_FORCE 0x0507 #define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 #define mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0x0508 #define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x0509 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A 0x050a #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_BASE_IDX 2 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x050b #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x050c #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x050d #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x050e #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B 0x050f #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_BASE_IDX 2 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0510 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0511 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x0512 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0513 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C 0x0514 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_BASE_IDX 2 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0515 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0516 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0517 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518 #define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D 0x0519 #define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_BASE_IDX 2 #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a #define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051b #define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051c #define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2 #define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x051d #define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 #define mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0x051e #define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 #define mmDCHUBBUB_GLOBAL_TIMER_CNTL 0x051f #define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 #define mmSURFACE_CHECK0_ADDRESS_LSB 0x0520 #define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 #define mmSURFACE_CHECK0_ADDRESS_MSB 0x0521 #define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 #define mmSURFACE_CHECK1_ADDRESS_LSB 0x0522 #define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 #define mmSURFACE_CHECK1_ADDRESS_MSB 0x0523 #define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 #define mmSURFACE_CHECK2_ADDRESS_LSB 0x0524 #define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 #define mmSURFACE_CHECK2_ADDRESS_MSB 0x0525 #define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 #define mmSURFACE_CHECK3_ADDRESS_LSB 0x0526 #define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 #define mmSURFACE_CHECK3_ADDRESS_MSB 0x0527 #define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 #define mmVTG0_CONTROL 0x0528 #define mmVTG0_CONTROL_BASE_IDX 2 #define mmVTG1_CONTROL 0x0529 #define mmVTG1_CONTROL_BASE_IDX 2 #define mmVTG2_CONTROL 0x052a #define mmVTG2_CONTROL_BASE_IDX 2 #define mmVTG3_CONTROL 0x052b #define mmVTG3_CONTROL_BASE_IDX 2 #define mmVTG4_CONTROL 0x052c #define mmVTG4_CONTROL_BASE_IDX 2 #define mmVTG5_CONTROL 0x052d #define mmVTG5_CONTROL_BASE_IDX 2 #define mmDCHUBBUB_SOFT_RESET 0x052e #define mmDCHUBBUB_SOFT_RESET_BASE_IDX 2 #define mmDCHUBBUB_CLOCK_CNTL 0x052f #define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 #define mmDCFCLK_CNTL 0x0530 #define mmDCFCLK_CNTL_BASE_IDX 2 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0531 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0532 #define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 #define mmDCHUBBUB_VLINE_SNAPSHOT 0x0533 #define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 #define mmDCHUBBUB_SPARE 0x0534 #define mmDCHUBBUB_SPARE_BASE_IDX 2 #define mmDCHUBBUB_TEST_DEBUG_INDEX 0x053a #define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 #define mmDCHUBBUB_TEST_DEBUG_DATA 0x053b #define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 // addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec // base address: 0x1534 #define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x054d #define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 #define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x054e #define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 #define mmDC_PERFMON7_PERFCOUNTER_STATE 0x054f #define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 #define mmDC_PERFMON7_PERFMON_CNTL 0x0550 #define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 #define mmDC_PERFMON7_PERFMON_CNTL2 0x0551 #define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x0552 #define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 #define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x0553 #define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 #define mmDC_PERFMON7_PERFMON_HI 0x0554 #define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2 #define mmDC_PERFMON7_PERFMON_LOW 0x0555 #define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec // base address: 0x0 #define mmHUBP0_DCSURF_SURFACE_CONFIG 0x0559 #define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 #define mmHUBP0_DCSURF_ADDR_CONFIG 0x055a #define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 #define mmHUBP0_DCSURF_TILING_CONFIG 0x055b #define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START 0x055c #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x055e #define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x055f #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START 0x0560 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x0561 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x0562 #define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0563 #define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x0564 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x0565 #define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 #define mmHUBP0_DCHUBP_CNTL 0x0566 #define mmHUBP0_DCHUBP_CNTL_BASE_IDX 2 #define mmHUBP0_HUBP_CLK_CNTL 0x0567 #define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 #define mmHUBP0_DCHUBP_VMPG_CONFIG 0x0568 #define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 #define mmHUBP0_HUBPREQ_DEBUG_DB 0x0569 #define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 #define mmHUBP0_HUBPREQ_DEBUG 0x056a #define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x056e #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x056f #define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 // addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec // base address: 0x0 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH 0x057b #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x057c #define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x057d #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x057e #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x057f #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0580 #define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0581 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x0582 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0583 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0584 #define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0585 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0586 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0587 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0588 #define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0589 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x058a #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x058b #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x058c #define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0x058d #define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL 0x058e #define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0x058f #define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL 0x0590 #define mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME 0x0591 #define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0592 #define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE 0x0593 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0594 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0595 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0596 #define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0597 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0598 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0599 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x059a #define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 #define mmHUBPREQ0_DCN_EXPANSION_MODE 0x059b #define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 #define mmHUBPREQ0_DCN_TTU_QOS_WM 0x059c #define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 #define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x059d #define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x059e #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x059f #define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x05a0 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x05a1 #define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x05a2 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x05a3 #define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x05a4 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x05a5 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x05a6 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x05a7 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x05a8 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x05a9 #define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x05aa #define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x05ab #define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x05ac #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x05ad #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x05ae #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x05af #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x05b0 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x05b1 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS 0x05b2 #define mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x05b3 #define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL 0x05b4 #define mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2 #define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x05b5 #define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 #define mmHUBPREQ0_BLANK_OFFSET_0 0x05b6 #define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 #define mmHUBPREQ0_BLANK_OFFSET_1 0x05b7 #define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 #define mmHUBPREQ0_DST_DIMENSIONS 0x05b8 #define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 #define mmHUBPREQ0_DST_AFTER_SCALER 0x05b9 #define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 #define mmHUBPREQ0_PREFETCH_SETTINS 0x05ba #define mmHUBPREQ0_PREFETCH_SETTINS_BASE_IDX 2 #define mmHUBPREQ0_PREFETCH_SETTINS_C 0x05bb #define mmHUBPREQ0_PREFETCH_SETTINS_C_BASE_IDX 2 #define mmHUBPREQ0_VBLANK_PARAMETERS_0 0x05bc #define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 #define mmHUBPREQ0_VBLANK_PARAMETERS_1 0x05bd #define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 #define mmHUBPREQ0_VBLANK_PARAMETERS_2 0x05be #define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 #define mmHUBPREQ0_VBLANK_PARAMETERS_3 0x05bf #define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 #define mmHUBPREQ0_VBLANK_PARAMETERS_4 0x05c0 #define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 #define mmHUBPREQ0_NOM_PARAMETERS_0 0x05c1 #define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 #define mmHUBPREQ0_NOM_PARAMETERS_1 0x05c2 #define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 #define mmHUBPREQ0_NOM_PARAMETERS_2 0x05c3 #define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 #define mmHUBPREQ0_NOM_PARAMETERS_3 0x05c4 #define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 #define mmHUBPREQ0_NOM_PARAMETERS_4 0x05c5 #define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 #define mmHUBPREQ0_NOM_PARAMETERS_5 0x05c6 #define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 #define mmHUBPREQ0_NOM_PARAMETERS_6 0x05c7 #define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 #define mmHUBPREQ0_NOM_PARAMETERS_7 0x05c8 #define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 #define mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0x05c9 #define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 #define mmHUBPREQ0_PER_LINE_DELIVERY 0x05ca #define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 #define mmHUBPREQ0_CURSOR_SETTINS 0x05cb #define mmHUBPREQ0_CURSOR_SETTINS_BASE_IDX 2 #define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x05cc #define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x05cd #define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 #define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x05ce #define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 // addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec // base address: 0x0 #define mmHUBPRET0_HUBPRET_CONTROL 0x05e0 #define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 #define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x05e1 #define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 #define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x05e2 #define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x05e3 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x05e4 #define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 #define mmHUBPRET0_HUBPRET_READ_LINE0 0x05e5 #define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 #define mmHUBPRET0_HUBPRET_READ_LINE1 0x05e6 #define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 #define mmHUBPRET0_HUBPRET_INTERRUPT 0x05e7 #define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 #define mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0x05e8 #define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 #define mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0x05e9 #define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 // addressBlock: dce_dc_dcbubp0_dispdec_cursor_dispdec // base address: 0x0 #define mmCURSOR0_CURSOR_CONTROL 0x05ec #define mmCURSOR0_CURSOR_CONTROL_BASE_IDX 2 #define mmCURSOR0_CURSOR_SURFACE_ADDRESS 0x05ed #define mmCURSOR0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 #define mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH 0x05ee #define mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 #define mmCURSOR0_CURSOR_SIZE 0x05ef #define mmCURSOR0_CURSOR_SIZE_BASE_IDX 2 #define mmCURSOR0_CURSOR_POSITION 0x05f0 #define mmCURSOR0_CURSOR_POSITION_BASE_IDX 2 #define mmCURSOR0_CURSOR_HOT_SPOT 0x05f1 #define mmCURSOR0_CURSOR_HOT_SPOT_BASE_IDX 2 #define mmCURSOR0_CURSOR_STEREO_CONTROL 0x05f2 #define mmCURSOR0_CURSOR_STEREO_CONTROL_BASE_IDX 2 #define mmCURSOR0_CURSOR_DST_OFFSET 0x05f3 #define mmCURSOR0_CURSOR_DST_OFFSET_BASE_IDX 2 #define mmCURSOR0_CURSOR_MEM_PWR_CTRL 0x05f4 #define mmCURSOR0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 #define mmCURSOR0_CURSOR_MEM_PWR_STATUS 0x05f5 #define mmCURSOR0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 // addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec // base address: 0x1844 #define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x0611 #define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 #define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x0612 #define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 #define mmDC_PERFMON8_PERFCOUNTER_STATE 0x0613 #define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 #define mmDC_PERFMON8_PERFMON_CNTL 0x0614 #define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 #define mmDC_PERFMON8_PERFMON_CNTL2 0x0615 #define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x0616 #define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 #define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x0617 #define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 #define mmDC_PERFMON8_PERFMON_HI 0x0618 #define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2 #define mmDC_PERFMON8_PERFMON_LOW 0x0619 #define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec // base address: 0x310 #define mmHUBP1_DCSURF_SURFACE_CONFIG 0x061d #define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 #define mmHUBP1_DCSURF_ADDR_CONFIG 0x061e #define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 #define mmHUBP1_DCSURF_TILING_CONFIG 0x061f #define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START 0x0620 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x0621 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x0622 #define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0623 #define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START 0x0624 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x0625 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x0626 #define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0627 #define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x0628 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x0629 #define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 #define mmHUBP1_DCHUBP_CNTL 0x062a #define mmHUBP1_DCHUBP_CNTL_BASE_IDX 2 #define mmHUBP1_HUBP_CLK_CNTL 0x062b #define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 #define mmHUBP1_DCHUBP_VMPG_CONFIG 0x062c #define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 #define mmHUBP1_HUBPREQ_DEBUG_DB 0x062d #define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 #define mmHUBP1_HUBPREQ_DEBUG 0x062e #define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0632 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0633 #define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 // addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec // base address: 0x310 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH 0x063f #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x0640 #define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x0641 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x0642 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x0643 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0644 #define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0645 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x0646 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0647 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0648 #define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0649 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x064a #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x064b #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x064c #define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x064d #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x064e #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x064f #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0650 #define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0x0651 #define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL 0x0652 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0x0653 #define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL 0x0654 #define mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME 0x0655 #define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x0656 #define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE 0x0657 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x0658 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x0659 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x065a #define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x065b #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x065c #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x065d #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x065e #define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 #define mmHUBPREQ1_DCN_EXPANSION_MODE 0x065f #define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 #define mmHUBPREQ1_DCN_TTU_QOS_WM 0x0660 #define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 #define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0661 #define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0662 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0663 #define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x0664 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x0665 #define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x0666 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x0667 #define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x0668 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x0669 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x066a #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x066b #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x066c #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x066d #define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x066e #define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x066f #define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x0670 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x0671 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x0672 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x0673 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x0674 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x0675 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS 0x0676 #define mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x0677 #define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL 0x0678 #define mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2 #define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x0679 #define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 #define mmHUBPREQ1_BLANK_OFFSET_0 0x067a #define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 #define mmHUBPREQ1_BLANK_OFFSET_1 0x067b #define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 #define mmHUBPREQ1_DST_DIMENSIONS 0x067c #define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 #define mmHUBPREQ1_DST_AFTER_SCALER 0x067d #define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 #define mmHUBPREQ1_PREFETCH_SETTINS 0x067e #define mmHUBPREQ1_PREFETCH_SETTINS_BASE_IDX 2 #define mmHUBPREQ1_PREFETCH_SETTINS_C 0x067f #define mmHUBPREQ1_PREFETCH_SETTINS_C_BASE_IDX 2 #define mmHUBPREQ1_VBLANK_PARAMETERS_0 0x0680 #define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 #define mmHUBPREQ1_VBLANK_PARAMETERS_1 0x0681 #define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 #define mmHUBPREQ1_VBLANK_PARAMETERS_2 0x0682 #define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 #define mmHUBPREQ1_VBLANK_PARAMETERS_3 0x0683 #define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 #define mmHUBPREQ1_VBLANK_PARAMETERS_4 0x0684 #define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 #define mmHUBPREQ1_NOM_PARAMETERS_0 0x0685 #define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 #define mmHUBPREQ1_NOM_PARAMETERS_1 0x0686 #define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 #define mmHUBPREQ1_NOM_PARAMETERS_2 0x0687 #define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 #define mmHUBPREQ1_NOM_PARAMETERS_3 0x0688 #define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 #define mmHUBPREQ1_NOM_PARAMETERS_4 0x0689 #define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 #define mmHUBPREQ1_NOM_PARAMETERS_5 0x068a #define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 #define mmHUBPREQ1_NOM_PARAMETERS_6 0x068b #define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 #define mmHUBPREQ1_NOM_PARAMETERS_7 0x068c #define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 #define mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0x068d #define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 #define mmHUBPREQ1_PER_LINE_DELIVERY 0x068e #define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 #define mmHUBPREQ1_CURSOR_SETTINS 0x068f #define mmHUBPREQ1_CURSOR_SETTINS_BASE_IDX 2 #define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0690 #define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x0691 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x0692 #define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 // addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec // base address: 0x310 #define mmHUBPRET1_HUBPRET_CONTROL 0x06a4 #define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 #define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x06a5 #define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 #define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x06a6 #define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x06a7 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x06a8 #define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 #define mmHUBPRET1_HUBPRET_READ_LINE0 0x06a9 #define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 #define mmHUBPRET1_HUBPRET_READ_LINE1 0x06aa #define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 #define mmHUBPRET1_HUBPRET_INTERRUPT 0x06ab #define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 #define mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0x06ac #define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 #define mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0x06ad #define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 // addressBlock: dce_dc_dcbubp1_dispdec_cursor_dispdec // base address: 0x310 #define mmCURSOR1_CURSOR_CONTROL 0x06b0 #define mmCURSOR1_CURSOR_CONTROL_BASE_IDX 2 #define mmCURSOR1_CURSOR_SURFACE_ADDRESS 0x06b1 #define mmCURSOR1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 #define mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH 0x06b2 #define mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 #define mmCURSOR1_CURSOR_SIZE 0x06b3 #define mmCURSOR1_CURSOR_SIZE_BASE_IDX 2 #define mmCURSOR1_CURSOR_POSITION 0x06b4 #define mmCURSOR1_CURSOR_POSITION_BASE_IDX 2 #define mmCURSOR1_CURSOR_HOT_SPOT 0x06b5 #define mmCURSOR1_CURSOR_HOT_SPOT_BASE_IDX 2 #define mmCURSOR1_CURSOR_STEREO_CONTROL 0x06b6 #define mmCURSOR1_CURSOR_STEREO_CONTROL_BASE_IDX 2 #define mmCURSOR1_CURSOR_DST_OFFSET 0x06b7 #define mmCURSOR1_CURSOR_DST_OFFSET_BASE_IDX 2 #define mmCURSOR1_CURSOR_MEM_PWR_CTRL 0x06b8 #define mmCURSOR1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 #define mmCURSOR1_CURSOR_MEM_PWR_STATUS 0x06b9 #define mmCURSOR1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 // addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec // base address: 0x1b54 #define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x06d5 #define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 #define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x06d6 #define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 #define mmDC_PERFMON9_PERFCOUNTER_STATE 0x06d7 #define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 #define mmDC_PERFMON9_PERFMON_CNTL 0x06d8 #define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 #define mmDC_PERFMON9_PERFMON_CNTL2 0x06d9 #define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x06da #define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 #define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x06db #define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 #define mmDC_PERFMON9_PERFMON_HI 0x06dc #define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2 #define mmDC_PERFMON9_PERFMON_LOW 0x06dd #define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec // base address: 0x620 #define mmHUBP2_DCSURF_SURFACE_CONFIG 0x06e1 #define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 #define mmHUBP2_DCSURF_ADDR_CONFIG 0x06e2 #define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 #define mmHUBP2_DCSURF_TILING_CONFIG 0x06e3 #define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START 0x06e4 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x06e5 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x06e6 #define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06e7 #define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START 0x06e8 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x06e9 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x06ea #define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06eb #define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x06ec #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x06ed #define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 #define mmHUBP2_DCHUBP_CNTL 0x06ee #define mmHUBP2_DCHUBP_CNTL_BASE_IDX 2 #define mmHUBP2_HUBP_CLK_CNTL 0x06ef #define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 #define mmHUBP2_DCHUBP_VMPG_CONFIG 0x06f0 #define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 #define mmHUBP2_HUBPREQ_DEBUG_DB 0x06f1 #define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 #define mmHUBP2_HUBPREQ_DEBUG 0x06f2 #define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06f6 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06f7 #define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 // addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec // base address: 0x620 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH 0x0703 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x0704 #define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x0705 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x0706 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x0707 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0708 #define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0709 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x070a #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x070b #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x070c #define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x070d #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x070e #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x070f #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0710 #define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0711 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0712 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0713 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0714 #define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_SURFACE_CONTROL 0x0715 #define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL 0x0716 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL2 0x0717 #define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL 0x0718 #define mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME 0x0719 #define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x071a #define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE 0x071b #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x071c #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x071d #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x071e #define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x071f #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0720 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0721 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0722 #define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 #define mmHUBPREQ2_DCN_EXPANSION_MODE 0x0723 #define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 #define mmHUBPREQ2_DCN_TTU_QOS_WM 0x0724 #define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 #define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x0725 #define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x0726 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x0727 #define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x0728 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x0729 #define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x072a #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x072b #define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x072c #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x072d #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x072e #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x072f #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0730 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0731 #define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x0732 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x0733 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x0734 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x0735 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x0736 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x0737 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x0738 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x0739 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS 0x073a #define mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2 #define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x073b #define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL 0x073c #define mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2 #define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x073d #define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 #define mmHUBPREQ2_BLANK_OFFSET_0 0x073e #define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 #define mmHUBPREQ2_BLANK_OFFSET_1 0x073f #define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 #define mmHUBPREQ2_DST_DIMENSIONS 0x0740 #define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 #define mmHUBPREQ2_DST_AFTER_SCALER 0x0741 #define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 #define mmHUBPREQ2_PREFETCH_SETTINS 0x0742 #define mmHUBPREQ2_PREFETCH_SETTINS_BASE_IDX 2 #define mmHUBPREQ2_PREFETCH_SETTINS_C 0x0743 #define mmHUBPREQ2_PREFETCH_SETTINS_C_BASE_IDX 2 #define mmHUBPREQ2_VBLANK_PARAMETERS_0 0x0744 #define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 #define mmHUBPREQ2_VBLANK_PARAMETERS_1 0x0745 #define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 #define mmHUBPREQ2_VBLANK_PARAMETERS_2 0x0746 #define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 #define mmHUBPREQ2_VBLANK_PARAMETERS_3 0x0747 #define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 #define mmHUBPREQ2_VBLANK_PARAMETERS_4 0x0748 #define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 #define mmHUBPREQ2_NOM_PARAMETERS_0 0x0749 #define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 #define mmHUBPREQ2_NOM_PARAMETERS_1 0x074a #define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 #define mmHUBPREQ2_NOM_PARAMETERS_2 0x074b #define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 #define mmHUBPREQ2_NOM_PARAMETERS_3 0x074c #define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 #define mmHUBPREQ2_NOM_PARAMETERS_4 0x074d #define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 #define mmHUBPREQ2_NOM_PARAMETERS_5 0x074e #define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 #define mmHUBPREQ2_NOM_PARAMETERS_6 0x074f #define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 #define mmHUBPREQ2_NOM_PARAMETERS_7 0x0750 #define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 #define mmHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0751 #define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 #define mmHUBPREQ2_PER_LINE_DELIVERY 0x0752 #define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 #define mmHUBPREQ2_CURSOR_SETTINS 0x0753 #define mmHUBPREQ2_CURSOR_SETTINS_BASE_IDX 2 #define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0754 #define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0755 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0756 #define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 // addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec // base address: 0x620 #define mmHUBPRET2_HUBPRET_CONTROL 0x0768 #define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 #define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0769 #define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 #define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x076a #define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x076b #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x076c #define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 #define mmHUBPRET2_HUBPRET_READ_LINE0 0x076d #define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 #define mmHUBPRET2_HUBPRET_READ_LINE1 0x076e #define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 #define mmHUBPRET2_HUBPRET_INTERRUPT 0x076f #define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 #define mmHUBPRET2_HUBPRET_READ_LINE_VALUE 0x0770 #define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 #define mmHUBPRET2_HUBPRET_READ_LINE_STATUS 0x0771 #define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 // addressBlock: dce_dc_dcbubp2_dispdec_cursor_dispdec // base address: 0x620 #define mmCURSOR2_CURSOR_CONTROL 0x0774 #define mmCURSOR2_CURSOR_CONTROL_BASE_IDX 2 #define mmCURSOR2_CURSOR_SURFACE_ADDRESS 0x0775 #define mmCURSOR2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 #define mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH 0x0776 #define mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 #define mmCURSOR2_CURSOR_SIZE 0x0777 #define mmCURSOR2_CURSOR_SIZE_BASE_IDX 2 #define mmCURSOR2_CURSOR_POSITION 0x0778 #define mmCURSOR2_CURSOR_POSITION_BASE_IDX 2 #define mmCURSOR2_CURSOR_HOT_SPOT 0x0779 #define mmCURSOR2_CURSOR_HOT_SPOT_BASE_IDX 2 #define mmCURSOR2_CURSOR_STEREO_CONTROL 0x077a #define mmCURSOR2_CURSOR_STEREO_CONTROL_BASE_IDX 2 #define mmCURSOR2_CURSOR_DST_OFFSET 0x077b #define mmCURSOR2_CURSOR_DST_OFFSET_BASE_IDX 2 #define mmCURSOR2_CURSOR_MEM_PWR_CTRL 0x077c #define mmCURSOR2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 #define mmCURSOR2_CURSOR_MEM_PWR_STATUS 0x077d #define mmCURSOR2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 // addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec // base address: 0x1e64 #define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x0799 #define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 #define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x079a #define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 #define mmDC_PERFMON10_PERFCOUNTER_STATE 0x079b #define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 #define mmDC_PERFMON10_PERFMON_CNTL 0x079c #define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 #define mmDC_PERFMON10_PERFMON_CNTL2 0x079d #define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x079e #define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 #define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x079f #define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 #define mmDC_PERFMON10_PERFMON_HI 0x07a0 #define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2 #define mmDC_PERFMON10_PERFMON_LOW 0x07a1 #define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec // base address: 0x930 #define mmHUBP3_DCSURF_SURFACE_CONFIG 0x07a5 #define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 #define mmHUBP3_DCSURF_ADDR_CONFIG 0x07a6 #define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 #define mmHUBP3_DCSURF_TILING_CONFIG 0x07a7 #define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START 0x07a8 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a9 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x07aa #define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07ab #define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START 0x07ac #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x07ad #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x07ae #define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07af #define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x07b0 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x07b1 #define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 #define mmHUBP3_DCHUBP_CNTL 0x07b2 #define mmHUBP3_DCHUBP_CNTL_BASE_IDX 2 #define mmHUBP3_HUBP_CLK_CNTL 0x07b3 #define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 #define mmHUBP3_DCHUBP_VMPG_CONFIG 0x07b4 #define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 #define mmHUBP3_HUBPREQ_DEBUG_DB 0x07b5 #define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 #define mmHUBP3_HUBPREQ_DEBUG 0x07b6 #define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07ba #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07bb #define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 // addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec // base address: 0x930 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH 0x07c7 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x07c8 #define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c9 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07ca #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07cb #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07cc #define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07cd #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07ce #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07cf #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07d0 #define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07d1 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07d2 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07d3 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07d4 #define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07d5 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07d6 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d7 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d8 #define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_SURFACE_CONTROL 0x07d9 #define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL 0x07da #define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_FLIP_CONTROL2 0x07db #define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL 0x07dc #define mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME 0x07dd #define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x07de #define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE 0x07df #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x07e0 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x07e1 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x07e2 #define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x07e3 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07e4 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07e5 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e6 #define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 #define mmHUBPREQ3_DCN_EXPANSION_MODE 0x07e7 #define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 #define mmHUBPREQ3_DCN_TTU_QOS_WM 0x07e8 #define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 #define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x07e9 #define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x07ea #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x07eb #define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x07ec #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x07ed #define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x07ee #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x07ef #define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x07f0 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x07f1 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x07f2 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x07f3 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x07f4 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x07f5 #define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x07f6 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x07f7 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x07f8 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x07f9 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x07fa #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x07fb #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x07fc #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x07fd #define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2 #define mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS 0x07fe #define mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2 #define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x07ff #define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2 #define mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL 0x0800 #define mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2 #define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x0801 #define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 #define mmHUBPREQ3_BLANK_OFFSET_0 0x0802 #define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 #define mmHUBPREQ3_BLANK_OFFSET_1 0x0803 #define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 #define mmHUBPREQ3_DST_DIMENSIONS 0x0804 #define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 #define mmHUBPREQ3_DST_AFTER_SCALER 0x0805 #define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 #define mmHUBPREQ3_PREFETCH_SETTINS 0x0806 #define mmHUBPREQ3_PREFETCH_SETTINS_BASE_IDX 2 #define mmHUBPREQ3_PREFETCH_SETTINS_C 0x0807 #define mmHUBPREQ3_PREFETCH_SETTINS_C_BASE_IDX 2 #define mmHUBPREQ3_VBLANK_PARAMETERS_0 0x0808 #define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 #define mmHUBPREQ3_VBLANK_PARAMETERS_1 0x0809 #define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 #define mmHUBPREQ3_VBLANK_PARAMETERS_2 0x080a #define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 #define mmHUBPREQ3_VBLANK_PARAMETERS_3 0x080b #define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 #define mmHUBPREQ3_VBLANK_PARAMETERS_4 0x080c #define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 #define mmHUBPREQ3_NOM_PARAMETERS_0 0x080d #define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 #define mmHUBPREQ3_NOM_PARAMETERS_1 0x080e #define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 #define mmHUBPREQ3_NOM_PARAMETERS_2 0x080f #define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 #define mmHUBPREQ3_NOM_PARAMETERS_3 0x0810 #define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 #define mmHUBPREQ3_NOM_PARAMETERS_4 0x0811 #define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 #define mmHUBPREQ3_NOM_PARAMETERS_5 0x0812 #define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 #define mmHUBPREQ3_NOM_PARAMETERS_6 0x0813 #define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 #define mmHUBPREQ3_NOM_PARAMETERS_7 0x0814 #define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 #define mmHUBPREQ3_PER_LINE_DELIVERY_PRE 0x0815 #define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 #define mmHUBPREQ3_PER_LINE_DELIVERY 0x0816 #define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 #define mmHUBPREQ3_CURSOR_SETTINS 0x0817 #define mmHUBPREQ3_CURSOR_SETTINS_BASE_IDX 2 #define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x0818 #define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x0819 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 #define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x081a #define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 // addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec // base address: 0x930 #define mmHUBPRET3_HUBPRET_CONTROL 0x082c #define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 #define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x082d #define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 #define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x082e #define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x082f #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0830 #define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 #define mmHUBPRET3_HUBPRET_READ_LINE0 0x0831 #define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 #define mmHUBPRET3_HUBPRET_READ_LINE1 0x0832 #define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 #define mmHUBPRET3_HUBPRET_INTERRUPT 0x0833 #define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 #define mmHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0834 #define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 #define mmHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0835 #define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 // addressBlock: dce_dc_dcbubp3_dispdec_cursor_dispdec // base address: 0x930 #define mmCURSOR3_CURSOR_CONTROL 0x0838 #define mmCURSOR3_CURSOR_CONTROL_BASE_IDX 2 #define mmCURSOR3_CURSOR_SURFACE_ADDRESS 0x0839 #define mmCURSOR3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 #define mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH 0x083a #define mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 #define mmCURSOR3_CURSOR_SIZE 0x083b #define mmCURSOR3_CURSOR_SIZE_BASE_IDX 2 #define mmCURSOR3_CURSOR_POSITION 0x083c #define mmCURSOR3_CURSOR_POSITION_BASE_IDX 2 #define mmCURSOR3_CURSOR_HOT_SPOT 0x083d #define mmCURSOR3_CURSOR_HOT_SPOT_BASE_IDX 2 #define mmCURSOR3_CURSOR_STEREO_CONTROL 0x083e #define mmCURSOR3_CURSOR_STEREO_CONTROL_BASE_IDX 2 #define mmCURSOR3_CURSOR_DST_OFFSET 0x083f #define mmCURSOR3_CURSOR_DST_OFFSET_BASE_IDX 2 #define mmCURSOR3_CURSOR_MEM_PWR_CTRL 0x0840 #define mmCURSOR3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 #define mmCURSOR3_CURSOR_MEM_PWR_STATUS 0x0841 #define mmCURSOR3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 // addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec // base address: 0x2174 #define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x085d #define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 #define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x085e #define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 #define mmDC_PERFMON11_PERFCOUNTER_STATE 0x085f #define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 #define mmDC_PERFMON11_PERFMON_CNTL 0x0860 #define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 #define mmDC_PERFMON11_PERFMON_CNTL2 0x0861 #define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0862 #define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 #define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x0863 #define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 #define mmDC_PERFMON11_PERFMON_HI 0x0864 #define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2 #define mmDC_PERFMON11_PERFMON_LOW 0x0865 #define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 // addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec // base address: 0x0 #define mmDPP_TOP0_DPP_CONTROL 0x0c3d #define mmDPP_TOP0_DPP_CONTROL_BASE_IDX 2 #define mmDPP_TOP0_DPP_SOFT_RESET 0x0c3e #define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 #define mmDPP_TOP0_DPP_CRC_VAL_R_G 0x0c3f #define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 #define mmDPP_TOP0_DPP_CRC_VAL_B_A 0x0c40 #define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 #define mmDPP_TOP0_DPP_CRC_CTRL 0x0c41 #define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 #define mmDPP_TOP0_HOST_READ_CONTROL 0x0c42 #define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 // addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec // base address: 0x0 #define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0c47 #define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 #define mmCNVC_CFG0_FORMAT_CONTROL 0x0c48 #define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 #define mmCNVC_CFG0_FCNV_FP_SCALE_BIAS 0x0c49 #define mmCNVC_CFG0_FCNV_FP_SCALE_BIAS_BASE_IDX 2 #define mmCNVC_CFG0_DENORM_CONTROL 0x0c4a #define mmCNVC_CFG0_DENORM_CONTROL_BASE_IDX 2 #define mmCNVC_CFG0_COLOR_KEYER_CONTROL 0x0c4c #define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 #define mmCNVC_CFG0_COLOR_KEYER_ALPHA 0x0c4d #define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 #define mmCNVC_CFG0_COLOR_KEYER_RED 0x0c4e #define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 #define mmCNVC_CFG0_COLOR_KEYER_GREEN 0x0c4f #define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 #define mmCNVC_CFG0_COLOR_KEYER_BLUE 0x0c50 #define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 // addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec // base address: 0x0 #define mmCNVC_CUR0_CURSOR0_CONTROL 0x0c58 #define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 #define mmCNVC_CUR0_CURSOR0_COLOR0 0x0c59 #define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 #define mmCNVC_CUR0_CURSOR0_COLOR1 0x0c5a #define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 #define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0c5b #define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 // addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec // base address: 0x0 #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0c62 #define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 #define mmDSCL0_SCL_COEF_RAM_TAP_DATA 0x0c63 #define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 #define mmDSCL0_SCL_MODE 0x0c64 #define mmDSCL0_SCL_MODE_BASE_IDX 2 #define mmDSCL0_SCL_TAP_CONTROL 0x0c65 #define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 #define mmDSCL0_DSCL_CONTROL 0x0c66 #define mmDSCL0_DSCL_CONTROL_BASE_IDX 2 #define mmDSCL0_DSCL_2TAP_CONTROL 0x0c67 #define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 #define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0c68 #define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0c69 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 #define mmDSCL0_SCL_HORZ_FILTER_INIT 0x0c6a #define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0c6b #define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 #define mmDSCL0_SCL_HORZ_FILTER_INIT_C 0x0c6c #define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0c6d #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 #define mmDSCL0_SCL_VERT_FILTER_INIT 0x0c6e #define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0c6f #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0c70 #define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 #define mmDSCL0_SCL_VERT_FILTER_INIT_C 0x0c71 #define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0c72 #define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 #define mmDSCL0_SCL_BLACK_OFFSET 0x0c73 #define mmDSCL0_SCL_BLACK_OFFSET_BASE_IDX 2 #define mmDSCL0_DSCL_UPDATE 0x0c74 #define mmDSCL0_DSCL_UPDATE_BASE_IDX 2 #define mmDSCL0_DSCL_AUTOCAL 0x0c75 #define mmDSCL0_DSCL_AUTOCAL_BASE_IDX 2 #define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0c76 #define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 #define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0c77 #define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 #define mmDSCL0_OTG_H_BLANK 0x0c78 #define mmDSCL0_OTG_H_BLANK_BASE_IDX 2 #define mmDSCL0_OTG_V_BLANK 0x0c79 #define mmDSCL0_OTG_V_BLANK_BASE_IDX 2 #define mmDSCL0_RECOUT_START 0x0c7a #define mmDSCL0_RECOUT_START_BASE_IDX 2 #define mmDSCL0_RECOUT_SIZE 0x0c7b #define mmDSCL0_RECOUT_SIZE_BASE_IDX 2 #define mmDSCL0_MPC_SIZE 0x0c7c #define mmDSCL0_MPC_SIZE_BASE_IDX 2 #define mmDSCL0_LB_DATA_FORMAT 0x0c7d #define mmDSCL0_LB_DATA_FORMAT_BASE_IDX 2 #define mmDSCL0_LB_MEMORY_CTRL 0x0c7e #define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 #define mmDSCL0_LB_V_COUNTER 0x0c7f #define mmDSCL0_LB_V_COUNTER_BASE_IDX 2 #define mmDSCL0_DSCL_MEM_PWR_CTRL 0x0c80 #define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 #define mmDSCL0_DSCL_MEM_PWR_STATUS 0x0c81 #define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 #define mmDSCL0_OBUF_CONTROL 0x0c82 #define mmDSCL0_OBUF_CONTROL_BASE_IDX 2 #define mmDSCL0_OBUF_MEM_PWR_CTRL 0x0c83 #define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 // addressBlock: dce_dc_dpp0_dispdec_cm_dispdec // base address: 0x0 #define mmCM0_CM_CONTROL 0x0c92 #define mmCM0_CM_CONTROL_BASE_IDX 2 #define mmCM0_CM_COMA_C11_C12 0x0c93 #define mmCM0_CM_COMA_C11_C12_BASE_IDX 2 #define mmCM0_CM_COMA_C13_C14 0x0c94 #define mmCM0_CM_COMA_C13_C14_BASE_IDX 2 #define mmCM0_CM_COMA_C21_C22 0x0c95 #define mmCM0_CM_COMA_C21_C22_BASE_IDX 2 #define mmCM0_CM_COMA_C23_C24 0x0c96 #define mmCM0_CM_COMA_C23_C24_BASE_IDX 2 #define mmCM0_CM_COMA_C31_C32 0x0c97 #define mmCM0_CM_COMA_C31_C32_BASE_IDX 2 #define mmCM0_CM_COMA_C33_C34 0x0c98 #define mmCM0_CM_COMA_C33_C34_BASE_IDX 2 #define mmCM0_CM_COMB_C11_C12 0x0c99 #define mmCM0_CM_COMB_C11_C12_BASE_IDX 2 #define mmCM0_CM_COMB_C13_C14 0x0c9a #define mmCM0_CM_COMB_C13_C14_BASE_IDX 2 #define mmCM0_CM_COMB_C21_C22 0x0c9b #define mmCM0_CM_COMB_C21_C22_BASE_IDX 2 #define mmCM0_CM_COMB_C23_C24 0x0c9c #define mmCM0_CM_COMB_C23_C24_BASE_IDX 2 #define mmCM0_CM_COMB_C31_C32 0x0c9d #define mmCM0_CM_COMB_C31_C32_BASE_IDX 2 #define mmCM0_CM_COMB_C33_C34 0x0c9e #define mmCM0_CM_COMB_C33_C34_BASE_IDX 2 #define mmCM0_CM_IGAM_CONTROL 0x0c9f #define mmCM0_CM_IGAM_CONTROL_BASE_IDX 2 #define mmCM0_CM_IGAM_LUT_RW_CONTROL 0x0ca0 #define mmCM0_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2 #define mmCM0_CM_IGAM_LUT_RW_INDEX 0x0ca1 #define mmCM0_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2 #define mmCM0_CM_IGAM_LUT_SEQ_COLOR 0x0ca2 #define mmCM0_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2 #define mmCM0_CM_IGAM_LUT_30_COLOR 0x0ca3 #define mmCM0_CM_IGAM_LUT_30_COLOR_BASE_IDX 2 #define mmCM0_CM_IGAM_LUT_PWL_DATA 0x0ca4 #define mmCM0_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2 #define mmCM0_CM_IGAM_LUT_AUTOFILL 0x0ca5 #define mmCM0_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2 #define mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0ca6 #define mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2 #define mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0ca7 #define mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2 #define mmCM0_CM_IGAM_LUT_BW_OFFSET_RED 0x0ca8 #define mmCM0_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2 #define mmCM0_CM_ICSC_CONTROL 0x0ca9 #define mmCM0_CM_ICSC_CONTROL_BASE_IDX 2 #define mmCM0_CM_ICSC_C11_C12 0x0caa #define mmCM0_CM_ICSC_C11_C12_BASE_IDX 2 #define mmCM0_CM_ICSC_C13_C14 0x0cab #define mmCM0_CM_ICSC_C13_C14_BASE_IDX 2 #define mmCM0_CM_ICSC_C21_C22 0x0cac #define mmCM0_CM_ICSC_C21_C22_BASE_IDX 2 #define mmCM0_CM_ICSC_C23_C24 0x0cad #define mmCM0_CM_ICSC_C23_C24_BASE_IDX 2 #define mmCM0_CM_ICSC_C31_C32 0x0cae #define mmCM0_CM_ICSC_C31_C32_BASE_IDX 2 #define mmCM0_CM_ICSC_C33_C34 0x0caf #define mmCM0_CM_ICSC_C33_C34_BASE_IDX 2 #define mmCM0_CM_GAMUT_REMAP_CONTROL 0x0cb0 #define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 #define mmCM0_CM_GAMUT_REMAP_C11_C12 0x0cb1 #define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 #define mmCM0_CM_GAMUT_REMAP_C13_C14 0x0cb2 #define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 #define mmCM0_CM_GAMUT_REMAP_C21_C22 0x0cb3 #define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 #define mmCM0_CM_GAMUT_REMAP_C23_C24 0x0cb4 #define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 #define mmCM0_CM_GAMUT_REMAP_C31_C32 0x0cb5 #define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 #define mmCM0_CM_GAMUT_REMAP_C33_C34 0x0cb6 #define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 #define mmCM0_CM_OCSC_CONTROL 0x0cb7 #define mmCM0_CM_OCSC_CONTROL_BASE_IDX 2 #define mmCM0_CM_OCSC_C11_C12 0x0cb8 #define mmCM0_CM_OCSC_C11_C12_BASE_IDX 2 #define mmCM0_CM_OCSC_C13_C14 0x0cb9 #define mmCM0_CM_OCSC_C13_C14_BASE_IDX 2 #define mmCM0_CM_OCSC_C21_C22 0x0cba #define mmCM0_CM_OCSC_C21_C22_BASE_IDX 2 #define mmCM0_CM_OCSC_C23_C24 0x0cbb #define mmCM0_CM_OCSC_C23_C24_BASE_IDX 2 #define mmCM0_CM_OCSC_C31_C32 0x0cbc #define mmCM0_CM_OCSC_C31_C32_BASE_IDX 2 #define mmCM0_CM_OCSC_C33_C34 0x0cbd #define mmCM0_CM_OCSC_C33_C34_BASE_IDX 2 #define mmCM0_CM_BNS_VALUES_R 0x0cbe #define mmCM0_CM_BNS_VALUES_R_BASE_IDX 2 #define mmCM0_CM_BNS_VALUES_G 0x0cbf #define mmCM0_CM_BNS_VALUES_G_BASE_IDX 2 #define mmCM0_CM_BNS_VALUES_B 0x0cc0 #define mmCM0_CM_BNS_VALUES_B_BASE_IDX 2 #define mmCM0_CM_DGAM_CONTROL 0x0cc1 #define mmCM0_CM_DGAM_CONTROL_BASE_IDX 2 #define mmCM0_CM_DGAM_LUT_INDEX 0x0cc2 #define mmCM0_CM_DGAM_LUT_INDEX_BASE_IDX 2 #define mmCM0_CM_DGAM_LUT_DATA 0x0cc3 #define mmCM0_CM_DGAM_LUT_DATA_BASE_IDX 2 #define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK 0x0cc4 #define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMA_START_CNTL_B 0x0cc5 #define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMA_START_CNTL_G 0x0cc6 #define mmCM0_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMA_START_CNTL_R 0x0cc7 #define mmCM0_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0cc8 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0cc9 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0cca #define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_B 0x0ccb #define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_B 0x0ccc #define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_G 0x0ccd #define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_G 0x0cce #define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMA_END_CNTL1_R 0x0ccf #define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_R 0x0cd0 #define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMA_REGION_0_1 0x0cd1 #define mmCM0_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMA_REGION_2_3 0x0cd2 #define mmCM0_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMA_REGION_4_5 0x0cd3 #define mmCM0_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMA_REGION_6_7 0x0cd4 #define mmCM0_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMA_REGION_8_9 0x0cd5 #define mmCM0_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMA_REGION_10_11 0x0cd6 #define mmCM0_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMA_REGION_12_13 0x0cd7 #define mmCM0_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMA_REGION_14_15 0x0cd8 #define mmCM0_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMB_START_CNTL_B 0x0cd9 #define mmCM0_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMB_START_CNTL_G 0x0cda #define mmCM0_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMB_START_CNTL_R 0x0cdb #define mmCM0_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0cdc #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0cdd #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0cde #define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_B 0x0cdf #define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_B 0x0ce0 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_G 0x0ce1 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_G 0x0ce2 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_R 0x0ce3 #define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_R 0x0ce4 #define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMB_REGION_0_1 0x0ce5 #define mmCM0_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMB_REGION_2_3 0x0ce6 #define mmCM0_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMB_REGION_4_5 0x0ce7 #define mmCM0_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMB_REGION_6_7 0x0ce8 #define mmCM0_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMB_REGION_8_9 0x0ce9 #define mmCM0_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMB_REGION_10_11 0x0cea #define mmCM0_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMB_REGION_12_13 0x0ceb #define mmCM0_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 #define mmCM0_CM_DGAM_RAMB_REGION_14_15 0x0cec #define mmCM0_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 #define mmCM0_CM_RGAM_CONTROL 0x0ced #define mmCM0_CM_RGAM_CONTROL_BASE_IDX 2 #define mmCM0_CM_RGAM_LUT_INDEX 0x0cee #define mmCM0_CM_RGAM_LUT_INDEX_BASE_IDX 2 #define mmCM0_CM_RGAM_LUT_DATA 0x0cef #define mmCM0_CM_RGAM_LUT_DATA_BASE_IDX 2 #define mmCM0_CM_RGAM_LUT_WRITE_EN_MASK 0x0cf0 #define mmCM0_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_START_CNTL_B 0x0cf1 #define mmCM0_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_START_CNTL_G 0x0cf2 #define mmCM0_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_START_CNTL_R 0x0cf3 #define mmCM0_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B 0x0cf4 #define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G 0x0cf5 #define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R 0x0cf6 #define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_END_CNTL1_B 0x0cf7 #define mmCM0_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_END_CNTL2_B 0x0cf8 #define mmCM0_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_END_CNTL1_G 0x0cf9 #define mmCM0_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_END_CNTL2_G 0x0cfa #define mmCM0_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_END_CNTL1_R 0x0cfb #define mmCM0_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_END_CNTL2_R 0x0cfc #define mmCM0_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_REGION_0_1 0x0cfd #define mmCM0_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_REGION_2_3 0x0cfe #define mmCM0_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_REGION_4_5 0x0cff #define mmCM0_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_REGION_6_7 0x0d00 #define mmCM0_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_REGION_8_9 0x0d01 #define mmCM0_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_REGION_10_11 0x0d02 #define mmCM0_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_REGION_12_13 0x0d03 #define mmCM0_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_REGION_14_15 0x0d04 #define mmCM0_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_REGION_16_17 0x0d05 #define mmCM0_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_REGION_18_19 0x0d06 #define mmCM0_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_REGION_20_21 0x0d07 #define mmCM0_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_REGION_22_23 0x0d08 #define mmCM0_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_REGION_24_25 0x0d09 #define mmCM0_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_REGION_26_27 0x0d0a #define mmCM0_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_REGION_28_29 0x0d0b #define mmCM0_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_REGION_30_31 0x0d0c #define mmCM0_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMA_REGION_32_33 0x0d0d #define mmCM0_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_START_CNTL_B 0x0d0e #define mmCM0_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_START_CNTL_G 0x0d0f #define mmCM0_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_START_CNTL_R 0x0d10 #define mmCM0_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B 0x0d11 #define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G 0x0d12 #define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R 0x0d13 #define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_END_CNTL1_B 0x0d14 #define mmCM0_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_END_CNTL2_B 0x0d15 #define mmCM0_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_END_CNTL1_G 0x0d16 #define mmCM0_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_END_CNTL2_G 0x0d17 #define mmCM0_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_END_CNTL1_R 0x0d18 #define mmCM0_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_END_CNTL2_R 0x0d19 #define mmCM0_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_REGION_0_1 0x0d1a #define mmCM0_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_REGION_2_3 0x0d1b #define mmCM0_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_REGION_4_5 0x0d1c #define mmCM0_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_REGION_6_7 0x0d1d #define mmCM0_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_REGION_8_9 0x0d1e #define mmCM0_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_REGION_10_11 0x0d1f #define mmCM0_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_REGION_12_13 0x0d20 #define mmCM0_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_REGION_14_15 0x0d21 #define mmCM0_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_REGION_16_17 0x0d22 #define mmCM0_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_REGION_18_19 0x0d23 #define mmCM0_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_REGION_20_21 0x0d24 #define mmCM0_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_REGION_22_23 0x0d25 #define mmCM0_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_REGION_24_25 0x0d26 #define mmCM0_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_REGION_26_27 0x0d27 #define mmCM0_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_REGION_28_29 0x0d28 #define mmCM0_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_REGION_30_31 0x0d29 #define mmCM0_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2 #define mmCM0_CM_RGAM_RAMB_REGION_32_33 0x0d2a #define mmCM0_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2 #define mmCM0_CM_HDR_MULT_COEF 0x0d2b #define mmCM0_CM_HDR_MULT_COEF_BASE_IDX 2 #define mmCM0_CM_RANGE_CLAMP_CONTROL_R 0x0d2c #define mmCM0_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2 #define mmCM0_CM_RANGE_CLAMP_CONTROL_G 0x0d2d #define mmCM0_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2 #define mmCM0_CM_RANGE_CLAMP_CONTROL_B 0x0d2e #define mmCM0_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2 #define mmCM0_CM_DENORM_CONTROL 0x0d2f #define mmCM0_CM_DENORM_CONTROL_BASE_IDX 2 #define mmCM0_CM_CMOUT_CONTROL 0x0d30 #define mmCM0_CM_CMOUT_CONTROL_BASE_IDX 2 #define mmCM0_CM_CMOUT_RANDOM_SEEDS 0x0d31 #define mmCM0_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2 #define mmCM0_CM_MEM_PWR_CTRL 0x0d32 #define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 #define mmCM0_CM_MEM_PWR_STATUS 0x0d33 #define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 #define mmCM0_CM_TEST_DEBUG_INDEX 0x0d35 #define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 #define mmCM0_CM_TEST_DEBUG_DATA 0x0d36 #define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 // addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec // base address: 0x3530 #define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x0d4c #define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 #define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x0d4d #define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 #define mmDC_PERFMON12_PERFCOUNTER_STATE 0x0d4e #define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 #define mmDC_PERFMON12_PERFMON_CNTL 0x0d4f #define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 #define mmDC_PERFMON12_PERFMON_CNTL2 0x0d50 #define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0d51 #define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 #define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x0d52 #define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 #define mmDC_PERFMON12_PERFMON_HI 0x0d53 #define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2 #define mmDC_PERFMON12_PERFMON_LOW 0x0d54 #define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 // addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec // base address: 0x46c #define mmDPP_TOP1_DPP_CONTROL 0x0d58 #define mmDPP_TOP1_DPP_CONTROL_BASE_IDX 2 #define mmDPP_TOP1_DPP_SOFT_RESET 0x0d59 #define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 #define mmDPP_TOP1_DPP_CRC_VAL_R_G 0x0d5a #define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 #define mmDPP_TOP1_DPP_CRC_VAL_B_A 0x0d5b #define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 #define mmDPP_TOP1_DPP_CRC_CTRL 0x0d5c #define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 #define mmDPP_TOP1_HOST_READ_CONTROL 0x0d5d #define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 // addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec // base address: 0x46c #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0d62 #define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 #define mmCNVC_CFG1_FORMAT_CONTROL 0x0d63 #define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 #define mmCNVC_CFG1_FCNV_FP_SCALE_BIAS 0x0d64 #define mmCNVC_CFG1_FCNV_FP_SCALE_BIAS_BASE_IDX 2 #define mmCNVC_CFG1_DENORM_CONTROL 0x0d65 #define mmCNVC_CFG1_DENORM_CONTROL_BASE_IDX 2 #define mmCNVC_CFG1_COLOR_KEYER_CONTROL 0x0d67 #define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 #define mmCNVC_CFG1_COLOR_KEYER_ALPHA 0x0d68 #define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 #define mmCNVC_CFG1_COLOR_KEYER_RED 0x0d69 #define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 #define mmCNVC_CFG1_COLOR_KEYER_GREEN 0x0d6a #define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 #define mmCNVC_CFG1_COLOR_KEYER_BLUE 0x0d6b #define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 // addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec // base address: 0x46c #define mmCNVC_CUR1_CURSOR0_CONTROL 0x0d73 #define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 #define mmCNVC_CUR1_CURSOR0_COLOR0 0x0d74 #define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 #define mmCNVC_CUR1_CURSOR0_COLOR1 0x0d75 #define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 #define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0d76 #define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 // addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec // base address: 0x46c #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0d7d #define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 #define mmDSCL1_SCL_COEF_RAM_TAP_DATA 0x0d7e #define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 #define mmDSCL1_SCL_MODE 0x0d7f #define mmDSCL1_SCL_MODE_BASE_IDX 2 #define mmDSCL1_SCL_TAP_CONTROL 0x0d80 #define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 #define mmDSCL1_DSCL_CONTROL 0x0d81 #define mmDSCL1_DSCL_CONTROL_BASE_IDX 2 #define mmDSCL1_DSCL_2TAP_CONTROL 0x0d82 #define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 #define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0d83 #define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0d84 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 #define mmDSCL1_SCL_HORZ_FILTER_INIT 0x0d85 #define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d86 #define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 #define mmDSCL1_SCL_HORZ_FILTER_INIT_C 0x0d87 #define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0d88 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 #define mmDSCL1_SCL_VERT_FILTER_INIT 0x0d89 #define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0d8a #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d8b #define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 #define mmDSCL1_SCL_VERT_FILTER_INIT_C 0x0d8c #define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0d8d #define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 #define mmDSCL1_SCL_BLACK_OFFSET 0x0d8e #define mmDSCL1_SCL_BLACK_OFFSET_BASE_IDX 2 #define mmDSCL1_DSCL_UPDATE 0x0d8f #define mmDSCL1_DSCL_UPDATE_BASE_IDX 2 #define mmDSCL1_DSCL_AUTOCAL 0x0d90 #define mmDSCL1_DSCL_AUTOCAL_BASE_IDX 2 #define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d91 #define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 #define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d92 #define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 #define mmDSCL1_OTG_H_BLANK 0x0d93 #define mmDSCL1_OTG_H_BLANK_BASE_IDX 2 #define mmDSCL1_OTG_V_BLANK 0x0d94 #define mmDSCL1_OTG_V_BLANK_BASE_IDX 2 #define mmDSCL1_RECOUT_START 0x0d95 #define mmDSCL1_RECOUT_START_BASE_IDX 2 #define mmDSCL1_RECOUT_SIZE 0x0d96 #define mmDSCL1_RECOUT_SIZE_BASE_IDX 2 #define mmDSCL1_MPC_SIZE 0x0d97 #define mmDSCL1_MPC_SIZE_BASE_IDX 2 #define mmDSCL1_LB_DATA_FORMAT 0x0d98 #define mmDSCL1_LB_DATA_FORMAT_BASE_IDX 2 #define mmDSCL1_LB_MEMORY_CTRL 0x0d99 #define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 #define mmDSCL1_LB_V_COUNTER 0x0d9a #define mmDSCL1_LB_V_COUNTER_BASE_IDX 2 #define mmDSCL1_DSCL_MEM_PWR_CTRL 0x0d9b #define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 #define mmDSCL1_DSCL_MEM_PWR_STATUS 0x0d9c #define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 #define mmDSCL1_OBUF_CONTROL 0x0d9d #define mmDSCL1_OBUF_CONTROL_BASE_IDX 2 #define mmDSCL1_OBUF_MEM_PWR_CTRL 0x0d9e #define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 // addressBlock: dce_dc_dpp1_dispdec_cm_dispdec // base address: 0x46c #define mmCM1_CM_CONTROL 0x0dad #define mmCM1_CM_CONTROL_BASE_IDX 2 #define mmCM1_CM_COMA_C11_C12 0x0dae #define mmCM1_CM_COMA_C11_C12_BASE_IDX 2 #define mmCM1_CM_COMA_C13_C14 0x0daf #define mmCM1_CM_COMA_C13_C14_BASE_IDX 2 #define mmCM1_CM_COMA_C21_C22 0x0db0 #define mmCM1_CM_COMA_C21_C22_BASE_IDX 2 #define mmCM1_CM_COMA_C23_C24 0x0db1 #define mmCM1_CM_COMA_C23_C24_BASE_IDX 2 #define mmCM1_CM_COMA_C31_C32 0x0db2 #define mmCM1_CM_COMA_C31_C32_BASE_IDX 2 #define mmCM1_CM_COMA_C33_C34 0x0db3 #define mmCM1_CM_COMA_C33_C34_BASE_IDX 2 #define mmCM1_CM_COMB_C11_C12 0x0db4 #define mmCM1_CM_COMB_C11_C12_BASE_IDX 2 #define mmCM1_CM_COMB_C13_C14 0x0db5 #define mmCM1_CM_COMB_C13_C14_BASE_IDX 2 #define mmCM1_CM_COMB_C21_C22 0x0db6 #define mmCM1_CM_COMB_C21_C22_BASE_IDX 2 #define mmCM1_CM_COMB_C23_C24 0x0db7 #define mmCM1_CM_COMB_C23_C24_BASE_IDX 2 #define mmCM1_CM_COMB_C31_C32 0x0db8 #define mmCM1_CM_COMB_C31_C32_BASE_IDX 2 #define mmCM1_CM_COMB_C33_C34 0x0db9 #define mmCM1_CM_COMB_C33_C34_BASE_IDX 2 #define mmCM1_CM_IGAM_CONTROL 0x0dba #define mmCM1_CM_IGAM_CONTROL_BASE_IDX 2 #define mmCM1_CM_IGAM_LUT_RW_CONTROL 0x0dbb #define mmCM1_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2 #define mmCM1_CM_IGAM_LUT_RW_INDEX 0x0dbc #define mmCM1_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2 #define mmCM1_CM_IGAM_LUT_SEQ_COLOR 0x0dbd #define mmCM1_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2 #define mmCM1_CM_IGAM_LUT_30_COLOR 0x0dbe #define mmCM1_CM_IGAM_LUT_30_COLOR_BASE_IDX 2 #define mmCM1_CM_IGAM_LUT_PWL_DATA 0x0dbf #define mmCM1_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2 #define mmCM1_CM_IGAM_LUT_AUTOFILL 0x0dc0 #define mmCM1_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2 #define mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0dc1 #define mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2 #define mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0dc2 #define mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2 #define mmCM1_CM_IGAM_LUT_BW_OFFSET_RED 0x0dc3 #define mmCM1_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2 #define mmCM1_CM_ICSC_CONTROL 0x0dc4 #define mmCM1_CM_ICSC_CONTROL_BASE_IDX 2 #define mmCM1_CM_ICSC_C11_C12 0x0dc5 #define mmCM1_CM_ICSC_C11_C12_BASE_IDX 2 #define mmCM1_CM_ICSC_C13_C14 0x0dc6 #define mmCM1_CM_ICSC_C13_C14_BASE_IDX 2 #define mmCM1_CM_ICSC_C21_C22 0x0dc7 #define mmCM1_CM_ICSC_C21_C22_BASE_IDX 2 #define mmCM1_CM_ICSC_C23_C24 0x0dc8 #define mmCM1_CM_ICSC_C23_C24_BASE_IDX 2 #define mmCM1_CM_ICSC_C31_C32 0x0dc9 #define mmCM1_CM_ICSC_C31_C32_BASE_IDX 2 #define mmCM1_CM_ICSC_C33_C34 0x0dca #define mmCM1_CM_ICSC_C33_C34_BASE_IDX 2 #define mmCM1_CM_GAMUT_REMAP_CONTROL 0x0dcb #define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 #define mmCM1_CM_GAMUT_REMAP_C11_C12 0x0dcc #define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 #define mmCM1_CM_GAMUT_REMAP_C13_C14 0x0dcd #define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 #define mmCM1_CM_GAMUT_REMAP_C21_C22 0x0dce #define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 #define mmCM1_CM_GAMUT_REMAP_C23_C24 0x0dcf #define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 #define mmCM1_CM_GAMUT_REMAP_C31_C32 0x0dd0 #define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 #define mmCM1_CM_GAMUT_REMAP_C33_C34 0x0dd1 #define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 #define mmCM1_CM_OCSC_CONTROL 0x0dd2 #define mmCM1_CM_OCSC_CONTROL_BASE_IDX 2 #define mmCM1_CM_OCSC_C11_C12 0x0dd3 #define mmCM1_CM_OCSC_C11_C12_BASE_IDX 2 #define mmCM1_CM_OCSC_C13_C14 0x0dd4 #define mmCM1_CM_OCSC_C13_C14_BASE_IDX 2 #define mmCM1_CM_OCSC_C21_C22 0x0dd5 #define mmCM1_CM_OCSC_C21_C22_BASE_IDX 2 #define mmCM1_CM_OCSC_C23_C24 0x0dd6 #define mmCM1_CM_OCSC_C23_C24_BASE_IDX 2 #define mmCM1_CM_OCSC_C31_C32 0x0dd7 #define mmCM1_CM_OCSC_C31_C32_BASE_IDX 2 #define mmCM1_CM_OCSC_C33_C34 0x0dd8 #define mmCM1_CM_OCSC_C33_C34_BASE_IDX 2 #define mmCM1_CM_BNS_VALUES_R 0x0dd9 #define mmCM1_CM_BNS_VALUES_R_BASE_IDX 2 #define mmCM1_CM_BNS_VALUES_G 0x0dda #define mmCM1_CM_BNS_VALUES_G_BASE_IDX 2 #define mmCM1_CM_BNS_VALUES_B 0x0ddb #define mmCM1_CM_BNS_VALUES_B_BASE_IDX 2 #define mmCM1_CM_DGAM_CONTROL 0x0ddc #define mmCM1_CM_DGAM_CONTROL_BASE_IDX 2 #define mmCM1_CM_DGAM_LUT_INDEX 0x0ddd #define mmCM1_CM_DGAM_LUT_INDEX_BASE_IDX 2 #define mmCM1_CM_DGAM_LUT_DATA 0x0dde #define mmCM1_CM_DGAM_LUT_DATA_BASE_IDX 2 #define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK 0x0ddf #define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMA_START_CNTL_B 0x0de0 #define mmCM1_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMA_START_CNTL_G 0x0de1 #define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMA_START_CNTL_R 0x0de2 #define mmCM1_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0de3 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0de4 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0de5 #define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_B 0x0de6 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_B 0x0de7 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_G 0x0de8 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_G 0x0de9 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMA_END_CNTL1_R 0x0dea #define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMA_END_CNTL2_R 0x0deb #define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMA_REGION_0_1 0x0dec #define mmCM1_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMA_REGION_2_3 0x0ded #define mmCM1_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMA_REGION_4_5 0x0dee #define mmCM1_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMA_REGION_6_7 0x0def #define mmCM1_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMA_REGION_8_9 0x0df0 #define mmCM1_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMA_REGION_10_11 0x0df1 #define mmCM1_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMA_REGION_12_13 0x0df2 #define mmCM1_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMA_REGION_14_15 0x0df3 #define mmCM1_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMB_START_CNTL_B 0x0df4 #define mmCM1_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMB_START_CNTL_G 0x0df5 #define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMB_START_CNTL_R 0x0df6 #define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0df7 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0df8 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0df9 #define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_B 0x0dfa #define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_B 0x0dfb #define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_G 0x0dfc #define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_G 0x0dfd #define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMB_END_CNTL1_R 0x0dfe #define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMB_END_CNTL2_R 0x0dff #define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMB_REGION_0_1 0x0e00 #define mmCM1_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMB_REGION_2_3 0x0e01 #define mmCM1_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMB_REGION_4_5 0x0e02 #define mmCM1_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMB_REGION_6_7 0x0e03 #define mmCM1_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMB_REGION_8_9 0x0e04 #define mmCM1_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMB_REGION_10_11 0x0e05 #define mmCM1_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMB_REGION_12_13 0x0e06 #define mmCM1_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 #define mmCM1_CM_DGAM_RAMB_REGION_14_15 0x0e07 #define mmCM1_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 #define mmCM1_CM_RGAM_CONTROL 0x0e08 #define mmCM1_CM_RGAM_CONTROL_BASE_IDX 2 #define mmCM1_CM_RGAM_LUT_INDEX 0x0e09 #define mmCM1_CM_RGAM_LUT_INDEX_BASE_IDX 2 #define mmCM1_CM_RGAM_LUT_DATA 0x0e0a #define mmCM1_CM_RGAM_LUT_DATA_BASE_IDX 2 #define mmCM1_CM_RGAM_LUT_WRITE_EN_MASK 0x0e0b #define mmCM1_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_START_CNTL_B 0x0e0c #define mmCM1_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_START_CNTL_G 0x0e0d #define mmCM1_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_START_CNTL_R 0x0e0e #define mmCM1_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B 0x0e0f #define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G 0x0e10 #define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R 0x0e11 #define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_END_CNTL1_B 0x0e12 #define mmCM1_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_END_CNTL2_B 0x0e13 #define mmCM1_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_END_CNTL1_G 0x0e14 #define mmCM1_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_END_CNTL2_G 0x0e15 #define mmCM1_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_END_CNTL1_R 0x0e16 #define mmCM1_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_END_CNTL2_R 0x0e17 #define mmCM1_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_REGION_0_1 0x0e18 #define mmCM1_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_REGION_2_3 0x0e19 #define mmCM1_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_REGION_4_5 0x0e1a #define mmCM1_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_REGION_6_7 0x0e1b #define mmCM1_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_REGION_8_9 0x0e1c #define mmCM1_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_REGION_10_11 0x0e1d #define mmCM1_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_REGION_12_13 0x0e1e #define mmCM1_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_REGION_14_15 0x0e1f #define mmCM1_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_REGION_16_17 0x0e20 #define mmCM1_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_REGION_18_19 0x0e21 #define mmCM1_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_REGION_20_21 0x0e22 #define mmCM1_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_REGION_22_23 0x0e23 #define mmCM1_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_REGION_24_25 0x0e24 #define mmCM1_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_REGION_26_27 0x0e25 #define mmCM1_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_REGION_28_29 0x0e26 #define mmCM1_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_REGION_30_31 0x0e27 #define mmCM1_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMA_REGION_32_33 0x0e28 #define mmCM1_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_START_CNTL_B 0x0e29 #define mmCM1_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_START_CNTL_G 0x0e2a #define mmCM1_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_START_CNTL_R 0x0e2b #define mmCM1_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B 0x0e2c #define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G 0x0e2d #define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R 0x0e2e #define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_END_CNTL1_B 0x0e2f #define mmCM1_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_END_CNTL2_B 0x0e30 #define mmCM1_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_END_CNTL1_G 0x0e31 #define mmCM1_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_END_CNTL2_G 0x0e32 #define mmCM1_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_END_CNTL1_R 0x0e33 #define mmCM1_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_END_CNTL2_R 0x0e34 #define mmCM1_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_REGION_0_1 0x0e35 #define mmCM1_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_REGION_2_3 0x0e36 #define mmCM1_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_REGION_4_5 0x0e37 #define mmCM1_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_REGION_6_7 0x0e38 #define mmCM1_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_REGION_8_9 0x0e39 #define mmCM1_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_REGION_10_11 0x0e3a #define mmCM1_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_REGION_12_13 0x0e3b #define mmCM1_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_REGION_14_15 0x0e3c #define mmCM1_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_REGION_16_17 0x0e3d #define mmCM1_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_REGION_18_19 0x0e3e #define mmCM1_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_REGION_20_21 0x0e3f #define mmCM1_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_REGION_22_23 0x0e40 #define mmCM1_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_REGION_24_25 0x0e41 #define mmCM1_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_REGION_26_27 0x0e42 #define mmCM1_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_REGION_28_29 0x0e43 #define mmCM1_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_REGION_30_31 0x0e44 #define mmCM1_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2 #define mmCM1_CM_RGAM_RAMB_REGION_32_33 0x0e45 #define mmCM1_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2 #define mmCM1_CM_HDR_MULT_COEF 0x0e46 #define mmCM1_CM_HDR_MULT_COEF_BASE_IDX 2 #define mmCM1_CM_RANGE_CLAMP_CONTROL_R 0x0e47 #define mmCM1_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2 #define mmCM1_CM_RANGE_CLAMP_CONTROL_G 0x0e48 #define mmCM1_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2 #define mmCM1_CM_RANGE_CLAMP_CONTROL_B 0x0e49 #define mmCM1_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2 #define mmCM1_CM_DENORM_CONTROL 0x0e4a #define mmCM1_CM_DENORM_CONTROL_BASE_IDX 2 #define mmCM1_CM_CMOUT_CONTROL 0x0e4b #define mmCM1_CM_CMOUT_CONTROL_BASE_IDX 2 #define mmCM1_CM_CMOUT_RANDOM_SEEDS 0x0e4c #define mmCM1_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2 #define mmCM1_CM_MEM_PWR_CTRL 0x0e4d #define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 #define mmCM1_CM_MEM_PWR_STATUS 0x0e4e #define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 #define mmCM1_CM_TEST_DEBUG_INDEX 0x0e50 #define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 #define mmCM1_CM_TEST_DEBUG_DATA 0x0e51 #define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 // addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec // base address: 0x399c #define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x0e67 #define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 #define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x0e68 #define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 #define mmDC_PERFMON13_PERFCOUNTER_STATE 0x0e69 #define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 #define mmDC_PERFMON13_PERFMON_CNTL 0x0e6a #define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 #define mmDC_PERFMON13_PERFMON_CNTL2 0x0e6b #define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0e6c #define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 #define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0e6d #define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 #define mmDC_PERFMON13_PERFMON_HI 0x0e6e #define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2 #define mmDC_PERFMON13_PERFMON_LOW 0x0e6f #define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 // addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec // base address: 0x8d8 #define mmDPP_TOP2_DPP_CONTROL 0x0e73 #define mmDPP_TOP2_DPP_CONTROL_BASE_IDX 2 #define mmDPP_TOP2_DPP_SOFT_RESET 0x0e74 #define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 #define mmDPP_TOP2_DPP_CRC_VAL_R_G 0x0e75 #define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 #define mmDPP_TOP2_DPP_CRC_VAL_B_A 0x0e76 #define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 #define mmDPP_TOP2_DPP_CRC_CTRL 0x0e77 #define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 #define mmDPP_TOP2_HOST_READ_CONTROL 0x0e78 #define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 // addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec // base address: 0x8d8 #define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0e7d #define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 #define mmCNVC_CFG2_FORMAT_CONTROL 0x0e7e #define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 #define mmCNVC_CFG2_FCNV_FP_SCALE_BIAS 0x0e7f #define mmCNVC_CFG2_FCNV_FP_SCALE_BIAS_BASE_IDX 2 #define mmCNVC_CFG2_DENORM_CONTROL 0x0e80 #define mmCNVC_CFG2_DENORM_CONTROL_BASE_IDX 2 #define mmCNVC_CFG2_COLOR_KEYER_CONTROL 0x0e82 #define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 #define mmCNVC_CFG2_COLOR_KEYER_ALPHA 0x0e83 #define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 #define mmCNVC_CFG2_COLOR_KEYER_RED 0x0e84 #define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 #define mmCNVC_CFG2_COLOR_KEYER_GREEN 0x0e85 #define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 #define mmCNVC_CFG2_COLOR_KEYER_BLUE 0x0e86 #define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 // addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec // base address: 0x8d8 #define mmCNVC_CUR2_CURSOR0_CONTROL 0x0e8e #define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 #define mmCNVC_CUR2_CURSOR0_COLOR0 0x0e8f #define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 #define mmCNVC_CUR2_CURSOR0_COLOR1 0x0e90 #define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 #define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0e91 #define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 // addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec // base address: 0x8d8 #define mmDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0e98 #define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 #define mmDSCL2_SCL_COEF_RAM_TAP_DATA 0x0e99 #define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 #define mmDSCL2_SCL_MODE 0x0e9a #define mmDSCL2_SCL_MODE_BASE_IDX 2 #define mmDSCL2_SCL_TAP_CONTROL 0x0e9b #define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 #define mmDSCL2_DSCL_CONTROL 0x0e9c #define mmDSCL2_DSCL_CONTROL_BASE_IDX 2 #define mmDSCL2_DSCL_2TAP_CONTROL 0x0e9d #define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 #define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0e9e #define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0e9f #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 #define mmDSCL2_SCL_HORZ_FILTER_INIT 0x0ea0 #define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0ea1 #define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 #define mmDSCL2_SCL_HORZ_FILTER_INIT_C 0x0ea2 #define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0ea3 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 #define mmDSCL2_SCL_VERT_FILTER_INIT 0x0ea4 #define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0ea5 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0ea6 #define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 #define mmDSCL2_SCL_VERT_FILTER_INIT_C 0x0ea7 #define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0ea8 #define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 #define mmDSCL2_SCL_BLACK_OFFSET 0x0ea9 #define mmDSCL2_SCL_BLACK_OFFSET_BASE_IDX 2 #define mmDSCL2_DSCL_UPDATE 0x0eaa #define mmDSCL2_DSCL_UPDATE_BASE_IDX 2 #define mmDSCL2_DSCL_AUTOCAL 0x0eab #define mmDSCL2_DSCL_AUTOCAL_BASE_IDX 2 #define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0eac #define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 #define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0ead #define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 #define mmDSCL2_OTG_H_BLANK 0x0eae #define mmDSCL2_OTG_H_BLANK_BASE_IDX 2 #define mmDSCL2_OTG_V_BLANK 0x0eaf #define mmDSCL2_OTG_V_BLANK_BASE_IDX 2 #define mmDSCL2_RECOUT_START 0x0eb0 #define mmDSCL2_RECOUT_START_BASE_IDX 2 #define mmDSCL2_RECOUT_SIZE 0x0eb1 #define mmDSCL2_RECOUT_SIZE_BASE_IDX 2 #define mmDSCL2_MPC_SIZE 0x0eb2 #define mmDSCL2_MPC_SIZE_BASE_IDX 2 #define mmDSCL2_LB_DATA_FORMAT 0x0eb3 #define mmDSCL2_LB_DATA_FORMAT_BASE_IDX 2 #define mmDSCL2_LB_MEMORY_CTRL 0x0eb4 #define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 #define mmDSCL2_LB_V_COUNTER 0x0eb5 #define mmDSCL2_LB_V_COUNTER_BASE_IDX 2 #define mmDSCL2_DSCL_MEM_PWR_CTRL 0x0eb6 #define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 #define mmDSCL2_DSCL_MEM_PWR_STATUS 0x0eb7 #define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 #define mmDSCL2_OBUF_CONTROL 0x0eb8 #define mmDSCL2_OBUF_CONTROL_BASE_IDX 2 #define mmDSCL2_OBUF_MEM_PWR_CTRL 0x0eb9 #define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 // addressBlock: dce_dc_dpp2_dispdec_cm_dispdec // base address: 0x8d8 #define mmCM2_CM_CONTROL 0x0ec8 #define mmCM2_CM_CONTROL_BASE_IDX 2 #define mmCM2_CM_COMA_C11_C12 0x0ec9 #define mmCM2_CM_COMA_C11_C12_BASE_IDX 2 #define mmCM2_CM_COMA_C13_C14 0x0eca #define mmCM2_CM_COMA_C13_C14_BASE_IDX 2 #define mmCM2_CM_COMA_C21_C22 0x0ecb #define mmCM2_CM_COMA_C21_C22_BASE_IDX 2 #define mmCM2_CM_COMA_C23_C24 0x0ecc #define mmCM2_CM_COMA_C23_C24_BASE_IDX 2 #define mmCM2_CM_COMA_C31_C32 0x0ecd #define mmCM2_CM_COMA_C31_C32_BASE_IDX 2 #define mmCM2_CM_COMA_C33_C34 0x0ece #define mmCM2_CM_COMA_C33_C34_BASE_IDX 2 #define mmCM2_CM_COMB_C11_C12 0x0ecf #define mmCM2_CM_COMB_C11_C12_BASE_IDX 2 #define mmCM2_CM_COMB_C13_C14 0x0ed0 #define mmCM2_CM_COMB_C13_C14_BASE_IDX 2 #define mmCM2_CM_COMB_C21_C22 0x0ed1 #define mmCM2_CM_COMB_C21_C22_BASE_IDX 2 #define mmCM2_CM_COMB_C23_C24 0x0ed2 #define mmCM2_CM_COMB_C23_C24_BASE_IDX 2 #define mmCM2_CM_COMB_C31_C32 0x0ed3 #define mmCM2_CM_COMB_C31_C32_BASE_IDX 2 #define mmCM2_CM_COMB_C33_C34 0x0ed4 #define mmCM2_CM_COMB_C33_C34_BASE_IDX 2 #define mmCM2_CM_IGAM_CONTROL 0x0ed5 #define mmCM2_CM_IGAM_CONTROL_BASE_IDX 2 #define mmCM2_CM_IGAM_LUT_RW_CONTROL 0x0ed6 #define mmCM2_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2 #define mmCM2_CM_IGAM_LUT_RW_INDEX 0x0ed7 #define mmCM2_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2 #define mmCM2_CM_IGAM_LUT_SEQ_COLOR 0x0ed8 #define mmCM2_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2 #define mmCM2_CM_IGAM_LUT_30_COLOR 0x0ed9 #define mmCM2_CM_IGAM_LUT_30_COLOR_BASE_IDX 2 #define mmCM2_CM_IGAM_LUT_PWL_DATA 0x0eda #define mmCM2_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2 #define mmCM2_CM_IGAM_LUT_AUTOFILL 0x0edb #define mmCM2_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2 #define mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0edc #define mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2 #define mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0edd #define mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2 #define mmCM2_CM_IGAM_LUT_BW_OFFSET_RED 0x0ede #define mmCM2_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2 #define mmCM2_CM_ICSC_CONTROL 0x0edf #define mmCM2_CM_ICSC_CONTROL_BASE_IDX 2 #define mmCM2_CM_ICSC_C11_C12 0x0ee0 #define mmCM2_CM_ICSC_C11_C12_BASE_IDX 2 #define mmCM2_CM_ICSC_C13_C14 0x0ee1 #define mmCM2_CM_ICSC_C13_C14_BASE_IDX 2 #define mmCM2_CM_ICSC_C21_C22 0x0ee2 #define mmCM2_CM_ICSC_C21_C22_BASE_IDX 2 #define mmCM2_CM_ICSC_C23_C24 0x0ee3 #define mmCM2_CM_ICSC_C23_C24_BASE_IDX 2 #define mmCM2_CM_ICSC_C31_C32 0x0ee4 #define mmCM2_CM_ICSC_C31_C32_BASE_IDX 2 #define mmCM2_CM_ICSC_C33_C34 0x0ee5 #define mmCM2_CM_ICSC_C33_C34_BASE_IDX 2 #define mmCM2_CM_GAMUT_REMAP_CONTROL 0x0ee6 #define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 #define mmCM2_CM_GAMUT_REMAP_C11_C12 0x0ee7 #define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 #define mmCM2_CM_GAMUT_REMAP_C13_C14 0x0ee8 #define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 #define mmCM2_CM_GAMUT_REMAP_C21_C22 0x0ee9 #define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 #define mmCM2_CM_GAMUT_REMAP_C23_C24 0x0eea #define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 #define mmCM2_CM_GAMUT_REMAP_C31_C32 0x0eeb #define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 #define mmCM2_CM_GAMUT_REMAP_C33_C34 0x0eec #define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 #define mmCM2_CM_OCSC_CONTROL 0x0eed #define mmCM2_CM_OCSC_CONTROL_BASE_IDX 2 #define mmCM2_CM_OCSC_C11_C12 0x0eee #define mmCM2_CM_OCSC_C11_C12_BASE_IDX 2 #define mmCM2_CM_OCSC_C13_C14 0x0eef #define mmCM2_CM_OCSC_C13_C14_BASE_IDX 2 #define mmCM2_CM_OCSC_C21_C22 0x0ef0 #define mmCM2_CM_OCSC_C21_C22_BASE_IDX 2 #define mmCM2_CM_OCSC_C23_C24 0x0ef1 #define mmCM2_CM_OCSC_C23_C24_BASE_IDX 2 #define mmCM2_CM_OCSC_C31_C32 0x0ef2 #define mmCM2_CM_OCSC_C31_C32_BASE_IDX 2 #define mmCM2_CM_OCSC_C33_C34 0x0ef3 #define mmCM2_CM_OCSC_C33_C34_BASE_IDX 2 #define mmCM2_CM_BNS_VALUES_R 0x0ef4 #define mmCM2_CM_BNS_VALUES_R_BASE_IDX 2 #define mmCM2_CM_BNS_VALUES_G 0x0ef5 #define mmCM2_CM_BNS_VALUES_G_BASE_IDX 2 #define mmCM2_CM_BNS_VALUES_B 0x0ef6 #define mmCM2_CM_BNS_VALUES_B_BASE_IDX 2 #define mmCM2_CM_DGAM_CONTROL 0x0ef7 #define mmCM2_CM_DGAM_CONTROL_BASE_IDX 2 #define mmCM2_CM_DGAM_LUT_INDEX 0x0ef8 #define mmCM2_CM_DGAM_LUT_INDEX_BASE_IDX 2 #define mmCM2_CM_DGAM_LUT_DATA 0x0ef9 #define mmCM2_CM_DGAM_LUT_DATA_BASE_IDX 2 #define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK 0x0efa #define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMA_START_CNTL_B 0x0efb #define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMA_START_CNTL_G 0x0efc #define mmCM2_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMA_START_CNTL_R 0x0efd #define mmCM2_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0efe #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0eff #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0f00 #define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_B 0x0f01 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_B 0x0f02 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_G 0x0f03 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_G 0x0f04 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_R 0x0f05 #define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_R 0x0f06 #define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMA_REGION_0_1 0x0f07 #define mmCM2_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMA_REGION_2_3 0x0f08 #define mmCM2_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMA_REGION_4_5 0x0f09 #define mmCM2_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMA_REGION_6_7 0x0f0a #define mmCM2_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMA_REGION_8_9 0x0f0b #define mmCM2_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMA_REGION_10_11 0x0f0c #define mmCM2_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMA_REGION_12_13 0x0f0d #define mmCM2_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMA_REGION_14_15 0x0f0e #define mmCM2_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMB_START_CNTL_B 0x0f0f #define mmCM2_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMB_START_CNTL_G 0x0f10 #define mmCM2_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMB_START_CNTL_R 0x0f11 #define mmCM2_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0f12 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0f13 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0f14 #define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_B 0x0f15 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_B 0x0f16 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_G 0x0f17 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_G 0x0f18 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_R 0x0f19 #define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMB_END_CNTL2_R 0x0f1a #define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMB_REGION_0_1 0x0f1b #define mmCM2_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMB_REGION_2_3 0x0f1c #define mmCM2_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMB_REGION_4_5 0x0f1d #define mmCM2_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMB_REGION_6_7 0x0f1e #define mmCM2_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMB_REGION_8_9 0x0f1f #define mmCM2_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMB_REGION_10_11 0x0f20 #define mmCM2_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMB_REGION_12_13 0x0f21 #define mmCM2_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 #define mmCM2_CM_DGAM_RAMB_REGION_14_15 0x0f22 #define mmCM2_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 #define mmCM2_CM_RGAM_CONTROL 0x0f23 #define mmCM2_CM_RGAM_CONTROL_BASE_IDX 2 #define mmCM2_CM_RGAM_LUT_INDEX 0x0f24 #define mmCM2_CM_RGAM_LUT_INDEX_BASE_IDX 2 #define mmCM2_CM_RGAM_LUT_DATA 0x0f25 #define mmCM2_CM_RGAM_LUT_DATA_BASE_IDX 2 #define mmCM2_CM_RGAM_LUT_WRITE_EN_MASK 0x0f26 #define mmCM2_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_START_CNTL_B 0x0f27 #define mmCM2_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_START_CNTL_G 0x0f28 #define mmCM2_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_START_CNTL_R 0x0f29 #define mmCM2_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B 0x0f2a #define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G 0x0f2b #define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R 0x0f2c #define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_END_CNTL1_B 0x0f2d #define mmCM2_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_END_CNTL2_B 0x0f2e #define mmCM2_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_END_CNTL1_G 0x0f2f #define mmCM2_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_END_CNTL2_G 0x0f30 #define mmCM2_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_END_CNTL1_R 0x0f31 #define mmCM2_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_END_CNTL2_R 0x0f32 #define mmCM2_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_REGION_0_1 0x0f33 #define mmCM2_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_REGION_2_3 0x0f34 #define mmCM2_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_REGION_4_5 0x0f35 #define mmCM2_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_REGION_6_7 0x0f36 #define mmCM2_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_REGION_8_9 0x0f37 #define mmCM2_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_REGION_10_11 0x0f38 #define mmCM2_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_REGION_12_13 0x0f39 #define mmCM2_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_REGION_14_15 0x0f3a #define mmCM2_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_REGION_16_17 0x0f3b #define mmCM2_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_REGION_18_19 0x0f3c #define mmCM2_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_REGION_20_21 0x0f3d #define mmCM2_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_REGION_22_23 0x0f3e #define mmCM2_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_REGION_24_25 0x0f3f #define mmCM2_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_REGION_26_27 0x0f40 #define mmCM2_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_REGION_28_29 0x0f41 #define mmCM2_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_REGION_30_31 0x0f42 #define mmCM2_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMA_REGION_32_33 0x0f43 #define mmCM2_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_START_CNTL_B 0x0f44 #define mmCM2_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_START_CNTL_G 0x0f45 #define mmCM2_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_START_CNTL_R 0x0f46 #define mmCM2_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B 0x0f47 #define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G 0x0f48 #define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R 0x0f49 #define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_END_CNTL1_B 0x0f4a #define mmCM2_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_END_CNTL2_B 0x0f4b #define mmCM2_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_END_CNTL1_G 0x0f4c #define mmCM2_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_END_CNTL2_G 0x0f4d #define mmCM2_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_END_CNTL1_R 0x0f4e #define mmCM2_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_END_CNTL2_R 0x0f4f #define mmCM2_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_REGION_0_1 0x0f50 #define mmCM2_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_REGION_2_3 0x0f51 #define mmCM2_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_REGION_4_5 0x0f52 #define mmCM2_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_REGION_6_7 0x0f53 #define mmCM2_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_REGION_8_9 0x0f54 #define mmCM2_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_REGION_10_11 0x0f55 #define mmCM2_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_REGION_12_13 0x0f56 #define mmCM2_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_REGION_14_15 0x0f57 #define mmCM2_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_REGION_16_17 0x0f58 #define mmCM2_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_REGION_18_19 0x0f59 #define mmCM2_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_REGION_20_21 0x0f5a #define mmCM2_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_REGION_22_23 0x0f5b #define mmCM2_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_REGION_24_25 0x0f5c #define mmCM2_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_REGION_26_27 0x0f5d #define mmCM2_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_REGION_28_29 0x0f5e #define mmCM2_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_REGION_30_31 0x0f5f #define mmCM2_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2 #define mmCM2_CM_RGAM_RAMB_REGION_32_33 0x0f60 #define mmCM2_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2 #define mmCM2_CM_HDR_MULT_COEF 0x0f61 #define mmCM2_CM_HDR_MULT_COEF_BASE_IDX 2 #define mmCM2_CM_RANGE_CLAMP_CONTROL_R 0x0f62 #define mmCM2_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2 #define mmCM2_CM_RANGE_CLAMP_CONTROL_G 0x0f63 #define mmCM2_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2 #define mmCM2_CM_RANGE_CLAMP_CONTROL_B 0x0f64 #define mmCM2_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2 #define mmCM2_CM_DENORM_CONTROL 0x0f65 #define mmCM2_CM_DENORM_CONTROL_BASE_IDX 2 #define mmCM2_CM_CMOUT_CONTROL 0x0f66 #define mmCM2_CM_CMOUT_CONTROL_BASE_IDX 2 #define mmCM2_CM_CMOUT_RANDOM_SEEDS 0x0f67 #define mmCM2_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2 #define mmCM2_CM_MEM_PWR_CTRL 0x0f68 #define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 #define mmCM2_CM_MEM_PWR_STATUS 0x0f69 #define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 #define mmCM2_CM_TEST_DEBUG_INDEX 0x0f6b #define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2 #define mmCM2_CM_TEST_DEBUG_DATA 0x0f6c #define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2 // addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec // base address: 0x3e08 #define mmDC_PERFMON14_PERFCOUNTER_CNTL 0x0f82 #define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 #define mmDC_PERFMON14_PERFCOUNTER_CNTL2 0x0f83 #define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 #define mmDC_PERFMON14_PERFCOUNTER_STATE 0x0f84 #define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 #define mmDC_PERFMON14_PERFMON_CNTL 0x0f85 #define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 #define mmDC_PERFMON14_PERFMON_CNTL2 0x0f86 #define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 #define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x0f87 #define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 #define mmDC_PERFMON14_PERFMON_CVALUE_LOW 0x0f88 #define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 #define mmDC_PERFMON14_PERFMON_HI 0x0f89 #define mmDC_PERFMON14_PERFMON_HI_BASE_IDX 2 #define mmDC_PERFMON14_PERFMON_LOW 0x0f8a #define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 // addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec // base address: 0xd44 #define mmDPP_TOP3_DPP_CONTROL 0x0f8e #define mmDPP_TOP3_DPP_CONTROL_BASE_IDX 2 #define mmDPP_TOP3_DPP_SOFT_RESET 0x0f8f #define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 #define mmDPP_TOP3_DPP_CRC_VAL_R_G 0x0f90 #define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 #define mmDPP_TOP3_DPP_CRC_VAL_B_A 0x0f91 #define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 #define mmDPP_TOP3_DPP_CRC_CTRL 0x0f92 #define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 #define mmDPP_TOP3_HOST_READ_CONTROL 0x0f93 #define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 // addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec // base address: 0xd44 #define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x0f98 #define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 #define mmCNVC_CFG3_FORMAT_CONTROL 0x0f99 #define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 #define mmCNVC_CFG3_FCNV_FP_SCALE_BIAS 0x0f9a #define mmCNVC_CFG3_FCNV_FP_SCALE_BIAS_BASE_IDX 2 #define mmCNVC_CFG3_DENORM_CONTROL 0x0f9b #define mmCNVC_CFG3_DENORM_CONTROL_BASE_IDX 2 #define mmCNVC_CFG3_COLOR_KEYER_CONTROL 0x0f9d #define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 #define mmCNVC_CFG3_COLOR_KEYER_ALPHA 0x0f9e #define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 #define mmCNVC_CFG3_COLOR_KEYER_RED 0x0f9f #define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 #define mmCNVC_CFG3_COLOR_KEYER_GREEN 0x0fa0 #define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 #define mmCNVC_CFG3_COLOR_KEYER_BLUE 0x0fa1 #define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 // addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec // base address: 0xd44 #define mmCNVC_CUR3_CURSOR0_CONTROL 0x0fa9 #define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 #define mmCNVC_CUR3_CURSOR0_COLOR0 0x0faa #define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 #define mmCNVC_CUR3_CURSOR0_COLOR1 0x0fab #define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 #define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x0fac #define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 // addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec // base address: 0xd44 #define mmDSCL3_SCL_COEF_RAM_TAP_SELECT 0x0fb3 #define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 #define mmDSCL3_SCL_COEF_RAM_TAP_DATA 0x0fb4 #define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 #define mmDSCL3_SCL_MODE 0x0fb5 #define mmDSCL3_SCL_MODE_BASE_IDX 2 #define mmDSCL3_SCL_TAP_CONTROL 0x0fb6 #define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 #define mmDSCL3_DSCL_CONTROL 0x0fb7 #define mmDSCL3_DSCL_CONTROL_BASE_IDX 2 #define mmDSCL3_DSCL_2TAP_CONTROL 0x0fb8 #define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 #define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x0fb9 #define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x0fba #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 #define mmDSCL3_SCL_HORZ_FILTER_INIT 0x0fbb #define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fbc #define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 #define mmDSCL3_SCL_HORZ_FILTER_INIT_C 0x0fbd #define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x0fbe #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 #define mmDSCL3_SCL_VERT_FILTER_INIT 0x0fbf #define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT 0x0fc0 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fc1 #define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 #define mmDSCL3_SCL_VERT_FILTER_INIT_C 0x0fc2 #define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x0fc3 #define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 #define mmDSCL3_SCL_BLACK_OFFSET 0x0fc4 #define mmDSCL3_SCL_BLACK_OFFSET_BASE_IDX 2 #define mmDSCL3_DSCL_UPDATE 0x0fc5 #define mmDSCL3_DSCL_UPDATE_BASE_IDX 2 #define mmDSCL3_DSCL_AUTOCAL 0x0fc6 #define mmDSCL3_DSCL_AUTOCAL_BASE_IDX 2 #define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fc7 #define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 #define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fc8 #define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 #define mmDSCL3_OTG_H_BLANK 0x0fc9 #define mmDSCL3_OTG_H_BLANK_BASE_IDX 2 #define mmDSCL3_OTG_V_BLANK 0x0fca #define mmDSCL3_OTG_V_BLANK_BASE_IDX 2 #define mmDSCL3_RECOUT_START 0x0fcb #define mmDSCL3_RECOUT_START_BASE_IDX 2 #define mmDSCL3_RECOUT_SIZE 0x0fcc #define mmDSCL3_RECOUT_SIZE_BASE_IDX 2 #define mmDSCL3_MPC_SIZE 0x0fcd #define mmDSCL3_MPC_SIZE_BASE_IDX 2 #define mmDSCL3_LB_DATA_FORMAT 0x0fce #define mmDSCL3_LB_DATA_FORMAT_BASE_IDX 2 #define mmDSCL3_LB_MEMORY_CTRL 0x0fcf #define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 #define mmDSCL3_LB_V_COUNTER 0x0fd0 #define mmDSCL3_LB_V_COUNTER_BASE_IDX 2 #define mmDSCL3_DSCL_MEM_PWR_CTRL 0x0fd1 #define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 #define mmDSCL3_DSCL_MEM_PWR_STATUS 0x0fd2 #define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 #define mmDSCL3_OBUF_CONTROL 0x0fd3 #define mmDSCL3_OBUF_CONTROL_BASE_IDX 2 #define mmDSCL3_OBUF_MEM_PWR_CTRL 0x0fd4 #define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 // addressBlock: dce_dc_dpp3_dispdec_cm_dispdec // base address: 0xd44 #define mmCM3_CM_CONTROL 0x0fe3 #define mmCM3_CM_CONTROL_BASE_IDX 2 #define mmCM3_CM_COMA_C11_C12 0x0fe4 #define mmCM3_CM_COMA_C11_C12_BASE_IDX 2 #define mmCM3_CM_COMA_C13_C14 0x0fe5 #define mmCM3_CM_COMA_C13_C14_BASE_IDX 2 #define mmCM3_CM_COMA_C21_C22 0x0fe6 #define mmCM3_CM_COMA_C21_C22_BASE_IDX 2 #define mmCM3_CM_COMA_C23_C24 0x0fe7 #define mmCM3_CM_COMA_C23_C24_BASE_IDX 2 #define mmCM3_CM_COMA_C31_C32 0x0fe8 #define mmCM3_CM_COMA_C31_C32_BASE_IDX 2 #define mmCM3_CM_COMA_C33_C34 0x0fe9 #define mmCM3_CM_COMA_C33_C34_BASE_IDX 2 #define mmCM3_CM_COMB_C11_C12 0x0fea #define mmCM3_CM_COMB_C11_C12_BASE_IDX 2 #define mmCM3_CM_COMB_C13_C14 0x0feb #define mmCM3_CM_COMB_C13_C14_BASE_IDX 2 #define mmCM3_CM_COMB_C21_C22 0x0fec #define mmCM3_CM_COMB_C21_C22_BASE_IDX 2 #define mmCM3_CM_COMB_C23_C24 0x0fed #define mmCM3_CM_COMB_C23_C24_BASE_IDX 2 #define mmCM3_CM_COMB_C31_C32 0x0fee #define mmCM3_CM_COMB_C31_C32_BASE_IDX 2 #define mmCM3_CM_COMB_C33_C34 0x0fef #define mmCM3_CM_COMB_C33_C34_BASE_IDX 2 #define mmCM3_CM_IGAM_CONTROL 0x0ff0 #define mmCM3_CM_IGAM_CONTROL_BASE_IDX 2 #define mmCM3_CM_IGAM_LUT_RW_CONTROL 0x0ff1 #define mmCM3_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2 #define mmCM3_CM_IGAM_LUT_RW_INDEX 0x0ff2 #define mmCM3_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2 #define mmCM3_CM_IGAM_LUT_SEQ_COLOR 0x0ff3 #define mmCM3_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2 #define mmCM3_CM_IGAM_LUT_30_COLOR 0x0ff4 #define mmCM3_CM_IGAM_LUT_30_COLOR_BASE_IDX 2 #define mmCM3_CM_IGAM_LUT_PWL_DATA 0x0ff5 #define mmCM3_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2 #define mmCM3_CM_IGAM_LUT_AUTOFILL 0x0ff6 #define mmCM3_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2 #define mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0ff7 #define mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2 #define mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0ff8 #define mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2 #define mmCM3_CM_IGAM_LUT_BW_OFFSET_RED 0x0ff9 #define mmCM3_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2 #define mmCM3_CM_ICSC_CONTROL 0x0ffa #define mmCM3_CM_ICSC_CONTROL_BASE_IDX 2 #define mmCM3_CM_ICSC_C11_C12 0x0ffb #define mmCM3_CM_ICSC_C11_C12_BASE_IDX 2 #define mmCM3_CM_ICSC_C13_C14 0x0ffc #define mmCM3_CM_ICSC_C13_C14_BASE_IDX 2 #define mmCM3_CM_ICSC_C21_C22 0x0ffd #define mmCM3_CM_ICSC_C21_C22_BASE_IDX 2 #define mmCM3_CM_ICSC_C23_C24 0x0ffe #define mmCM3_CM_ICSC_C23_C24_BASE_IDX 2 #define mmCM3_CM_ICSC_C31_C32 0x0fff #define mmCM3_CM_ICSC_C31_C32_BASE_IDX 2 #define mmCM3_CM_ICSC_C33_C34 0x1000 #define mmCM3_CM_ICSC_C33_C34_BASE_IDX 2 #define mmCM3_CM_GAMUT_REMAP_CONTROL 0x1001 #define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 #define mmCM3_CM_GAMUT_REMAP_C11_C12 0x1002 #define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 #define mmCM3_CM_GAMUT_REMAP_C13_C14 0x1003 #define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 #define mmCM3_CM_GAMUT_REMAP_C21_C22 0x1004 #define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 #define mmCM3_CM_GAMUT_REMAP_C23_C24 0x1005 #define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 #define mmCM3_CM_GAMUT_REMAP_C31_C32 0x1006 #define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 #define mmCM3_CM_GAMUT_REMAP_C33_C34 0x1007 #define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 #define mmCM3_CM_OCSC_CONTROL 0x1008 #define mmCM3_CM_OCSC_CONTROL_BASE_IDX 2 #define mmCM3_CM_OCSC_C11_C12 0x1009 #define mmCM3_CM_OCSC_C11_C12_BASE_IDX 2 #define mmCM3_CM_OCSC_C13_C14 0x100a #define mmCM3_CM_OCSC_C13_C14_BASE_IDX 2 #define mmCM3_CM_OCSC_C21_C22 0x100b #define mmCM3_CM_OCSC_C21_C22_BASE_IDX 2 #define mmCM3_CM_OCSC_C23_C24 0x100c #define mmCM3_CM_OCSC_C23_C24_BASE_IDX 2 #define mmCM3_CM_OCSC_C31_C32 0x100d #define mmCM3_CM_OCSC_C31_C32_BASE_IDX 2 #define mmCM3_CM_OCSC_C33_C34 0x100e #define mmCM3_CM_OCSC_C33_C34_BASE_IDX 2 #define mmCM3_CM_BNS_VALUES_R 0x100f #define mmCM3_CM_BNS_VALUES_R_BASE_IDX 2 #define mmCM3_CM_BNS_VALUES_G 0x1010 #define mmCM3_CM_BNS_VALUES_G_BASE_IDX 2 #define mmCM3_CM_BNS_VALUES_B 0x1011 #define mmCM3_CM_BNS_VALUES_B_BASE_IDX 2 #define mmCM3_CM_DGAM_CONTROL 0x1012 #define mmCM3_CM_DGAM_CONTROL_BASE_IDX 2 #define mmCM3_CM_DGAM_LUT_INDEX 0x1013 #define mmCM3_CM_DGAM_LUT_INDEX_BASE_IDX 2 #define mmCM3_CM_DGAM_LUT_DATA 0x1014 #define mmCM3_CM_DGAM_LUT_DATA_BASE_IDX 2 #define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK 0x1015 #define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMA_START_CNTL_B 0x1016 #define mmCM3_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMA_START_CNTL_G 0x1017 #define mmCM3_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMA_START_CNTL_R 0x1018 #define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B 0x1019 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G 0x101a #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R 0x101b #define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_B 0x101c #define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_B 0x101d #define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_G 0x101e #define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_G 0x101f #define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_R 0x1020 #define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_R 0x1021 #define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMA_REGION_0_1 0x1022 #define mmCM3_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMA_REGION_2_3 0x1023 #define mmCM3_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMA_REGION_4_5 0x1024 #define mmCM3_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMA_REGION_6_7 0x1025 #define mmCM3_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMA_REGION_8_9 0x1026 #define mmCM3_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMA_REGION_10_11 0x1027 #define mmCM3_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMA_REGION_12_13 0x1028 #define mmCM3_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMA_REGION_14_15 0x1029 #define mmCM3_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMB_START_CNTL_B 0x102a #define mmCM3_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMB_START_CNTL_G 0x102b #define mmCM3_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMB_START_CNTL_R 0x102c #define mmCM3_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B 0x102d #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G 0x102e #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R 0x102f #define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_B 0x1030 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_B 0x1031 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_G 0x1032 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_G 0x1033 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_R 0x1034 #define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_R 0x1035 #define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMB_REGION_0_1 0x1036 #define mmCM3_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMB_REGION_2_3 0x1037 #define mmCM3_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMB_REGION_4_5 0x1038 #define mmCM3_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMB_REGION_6_7 0x1039 #define mmCM3_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMB_REGION_8_9 0x103a #define mmCM3_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMB_REGION_10_11 0x103b #define mmCM3_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMB_REGION_12_13 0x103c #define mmCM3_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 #define mmCM3_CM_DGAM_RAMB_REGION_14_15 0x103d #define mmCM3_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 #define mmCM3_CM_RGAM_CONTROL 0x103e #define mmCM3_CM_RGAM_CONTROL_BASE_IDX 2 #define mmCM3_CM_RGAM_LUT_INDEX 0x103f #define mmCM3_CM_RGAM_LUT_INDEX_BASE_IDX 2 #define mmCM3_CM_RGAM_LUT_DATA 0x1040 #define mmCM3_CM_RGAM_LUT_DATA_BASE_IDX 2 #define mmCM3_CM_RGAM_LUT_WRITE_EN_MASK 0x1041 #define mmCM3_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_START_CNTL_B 0x1042 #define mmCM3_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_START_CNTL_G 0x1043 #define mmCM3_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_START_CNTL_R 0x1044 #define mmCM3_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B 0x1045 #define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G 0x1046 #define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R 0x1047 #define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_END_CNTL1_B 0x1048 #define mmCM3_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_END_CNTL2_B 0x1049 #define mmCM3_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_END_CNTL1_G 0x104a #define mmCM3_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_END_CNTL2_G 0x104b #define mmCM3_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_END_CNTL1_R 0x104c #define mmCM3_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_END_CNTL2_R 0x104d #define mmCM3_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_REGION_0_1 0x104e #define mmCM3_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_REGION_2_3 0x104f #define mmCM3_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_REGION_4_5 0x1050 #define mmCM3_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_REGION_6_7 0x1051 #define mmCM3_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_REGION_8_9 0x1052 #define mmCM3_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_REGION_10_11 0x1053 #define mmCM3_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_REGION_12_13 0x1054 #define mmCM3_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_REGION_14_15 0x1055 #define mmCM3_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_REGION_16_17 0x1056 #define mmCM3_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_REGION_18_19 0x1057 #define mmCM3_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_REGION_20_21 0x1058 #define mmCM3_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_REGION_22_23 0x1059 #define mmCM3_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_REGION_24_25 0x105a #define mmCM3_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_REGION_26_27 0x105b #define mmCM3_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_REGION_28_29 0x105c #define mmCM3_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_REGION_30_31 0x105d #define mmCM3_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMA_REGION_32_33 0x105e #define mmCM3_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_START_CNTL_B 0x105f #define mmCM3_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_START_CNTL_G 0x1060 #define mmCM3_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_START_CNTL_R 0x1061 #define mmCM3_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B 0x1062 #define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G 0x1063 #define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R 0x1064 #define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_END_CNTL1_B 0x1065 #define mmCM3_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_END_CNTL2_B 0x1066 #define mmCM3_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_END_CNTL1_G 0x1067 #define mmCM3_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_END_CNTL2_G 0x1068 #define mmCM3_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_END_CNTL1_R 0x1069 #define mmCM3_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_END_CNTL2_R 0x106a #define mmCM3_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_REGION_0_1 0x106b #define mmCM3_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_REGION_2_3 0x106c #define mmCM3_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_REGION_4_5 0x106d #define mmCM3_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_REGION_6_7 0x106e #define mmCM3_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_REGION_8_9 0x106f #define mmCM3_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_REGION_10_11 0x1070 #define mmCM3_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_REGION_12_13 0x1071 #define mmCM3_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_REGION_14_15 0x1072 #define mmCM3_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_REGION_16_17 0x1073 #define mmCM3_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_REGION_18_19 0x1074 #define mmCM3_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_REGION_20_21 0x1075 #define mmCM3_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_REGION_22_23 0x1076 #define mmCM3_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_REGION_24_25 0x1077 #define mmCM3_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_REGION_26_27 0x1078 #define mmCM3_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_REGION_28_29 0x1079 #define mmCM3_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_REGION_30_31 0x107a #define mmCM3_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2 #define mmCM3_CM_RGAM_RAMB_REGION_32_33 0x107b #define mmCM3_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2 #define mmCM3_CM_HDR_MULT_COEF 0x107c #define mmCM3_CM_HDR_MULT_COEF_BASE_IDX 2 #define mmCM3_CM_RANGE_CLAMP_CONTROL_R 0x107d #define mmCM3_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2 #define mmCM3_CM_RANGE_CLAMP_CONTROL_G 0x107e #define mmCM3_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2 #define mmCM3_CM_RANGE_CLAMP_CONTROL_B 0x107f #define mmCM3_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2 #define mmCM3_CM_DENORM_CONTROL 0x1080 #define mmCM3_CM_DENORM_CONTROL_BASE_IDX 2 --> -------------------- --> maximum size reached --> --------------------
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2026-06-09