Quelle  sc8280xp.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2021, The Linux Foundation. All rights reserved.
 * Copyright (c) 2022, Linaro Limited
 */

#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
#include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc8280xp.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/thermal/thermal.h>

/ {
 interrupt-parent = <&intc>;

 #address-cells = <2>;
 #size-cells = <2>;

 clocks {
  xo_board_clk: xo-board-clk {
   compatible = "fixed-clock";
   #clock-cells = <0>;
  };

  sleep_clk: sleep-clk {
   compatible = "fixed-clock";
   #clock-cells = <0>;
   clock-frequency = <32764>;
  };
 };

 cpus {
  #address-cells = <2>;
  #size-cells = <0>;

  cpu0: cpu@0 {
   device_type = "cpu";
   compatible = "arm,cortex-a78c";
   reg = <0x0 0x0>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   capacity-dmips-mhz = <981>;
   dynamic-power-coefficient = <549>;
   next-level-cache = <&l2_0>;
   power-domains = <&cpu_pd0>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 0>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
   #cooling-cells = <2>;
   l2_0: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
    l3_0: l3-cache {
     compatible = "cache";
     cache-level = <3>;
     cache-unified;
    };
   };
  };

  cpu1: cpu@100 {
   device_type = "cpu";
   compatible = "arm,cortex-a78c";
   reg = <0x0 0x100>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   capacity-dmips-mhz = <981>;
   dynamic-power-coefficient = <549>;
   next-level-cache = <&l2_100>;
   power-domains = <&cpu_pd1>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 0>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
   #cooling-cells = <2>;
   l2_100: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu2: cpu@200 {
   device_type = "cpu";
   compatible = "arm,cortex-a78c";
   reg = <0x0 0x200>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   capacity-dmips-mhz = <981>;
   dynamic-power-coefficient = <549>;
   next-level-cache = <&l2_200>;
   power-domains = <&cpu_pd2>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 0>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
   #cooling-cells = <2>;
   l2_200: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu3: cpu@300 {
   device_type = "cpu";
   compatible = "arm,cortex-a78c";
   reg = <0x0 0x300>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   capacity-dmips-mhz = <981>;
   dynamic-power-coefficient = <549>;
   next-level-cache = <&l2_300>;
   power-domains = <&cpu_pd3>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 0>;
   operating-points-v2 = <&cpu0_opp_table>;
   interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
   #cooling-cells = <2>;
   l2_300: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu4: cpu@400 {
   device_type = "cpu";
   compatible = "arm,cortex-x1c";
   reg = <0x0 0x400>;
   clocks = <&cpufreq_hw 1>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <590>;
   next-level-cache = <&l2_400>;
   power-domains = <&cpu_pd4>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 1>;
   operating-points-v2 = <&cpu4_opp_table>;
   interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
   #cooling-cells = <2>;
   l2_400: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu5: cpu@500 {
   device_type = "cpu";
   compatible = "arm,cortex-x1c";
   reg = <0x0 0x500>;
   clocks = <&cpufreq_hw 1>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <590>;
   next-level-cache = <&l2_500>;
   power-domains = <&cpu_pd5>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 1>;
   operating-points-v2 = <&cpu4_opp_table>;
   interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
   #cooling-cells = <2>;
   l2_500: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu6: cpu@600 {
   device_type = "cpu";
   compatible = "arm,cortex-x1c";
   reg = <0x0 0x600>;
   clocks = <&cpufreq_hw 1>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <590>;
   next-level-cache = <&l2_600>;
   power-domains = <&cpu_pd6>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 1>;
   operating-points-v2 = <&cpu4_opp_table>;
   interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
   #cooling-cells = <2>;
   l2_600: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu7: cpu@700 {
   device_type = "cpu";
   compatible = "arm,cortex-x1c";
   reg = <0x0 0x700>;
   clocks = <&cpufreq_hw 1>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <590>;
   next-level-cache = <&l2_700>;
   power-domains = <&cpu_pd7>;
   power-domain-names = "psci";
   qcom,freq-domain = <&cpufreq_hw 1>;
   operating-points-v2 = <&cpu4_opp_table>;
   interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
   #cooling-cells = <2>;
   l2_700: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu-map {
   cluster0 {
    core0 {
     cpu = <&cpu0>;
    };

    core1 {
     cpu = <&cpu1>;
    };

    core2 {
     cpu = <&cpu2>;
    };

    core3 {
     cpu = <&cpu3>;
    };

    core4 {
     cpu = <&cpu4>;
    };

    core5 {
     cpu = <&cpu5>;
    };

    core6 {
     cpu = <&cpu6>;
    };

    core7 {
     cpu = <&cpu7>;
    };
   };
  };

  idle-states {
   entry-method = "psci";

   little_cpu_sleep_0: cpu-sleep-0-0 {
    compatible = "arm,idle-state";
    idle-state-name = "little-rail-power-collapse";
    arm,psci-suspend-param = <0x40000004>;
    entry-latency-us = <355>;
    exit-latency-us = <909>;
    min-residency-us = <3934>;
    local-timer-stop;
   };

   big_cpu_sleep_0: cpu-sleep-1-0 {
    compatible = "arm,idle-state";
    idle-state-name = "big-rail-power-collapse";
    arm,psci-suspend-param = <0x40000004>;
    entry-latency-us = <241>;
    exit-latency-us = <1461>;
    min-residency-us = <4488>;
    local-timer-stop;
   };
  };

  domain-idle-states {
   cluster_sleep_0: cluster-sleep-0 {
    compatible = "domain-idle-state";
    arm,psci-suspend-param = <0x4100c344>;
    entry-latency-us = <3263>;
    exit-latency-us = <6562>;
    min-residency-us = <9987>;
   };
  };
 };

 firmware {
  scm: scm {
   compatible = "qcom,scm-sc8280xp", "qcom,scm";
   interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
   qcom,dload-mode = <&tcsr 0x13000>;
  };
 };

 aggre1_noc: interconnect-aggre1-noc {
  compatible = "qcom,sc8280xp-aggre1-noc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 aggre2_noc: interconnect-aggre2-noc {
  compatible = "qcom,sc8280xp-aggre2-noc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 clk_virt: interconnect-clk-virt {
  compatible = "qcom,sc8280xp-clk-virt";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 config_noc: interconnect-config-noc {
  compatible = "qcom,sc8280xp-config-noc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 dc_noc: interconnect-dc-noc {
  compatible = "qcom,sc8280xp-dc-noc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 gem_noc: interconnect-gem-noc {
  compatible = "qcom,sc8280xp-gem-noc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 lpass_noc: interconnect-lpass-ag-noc {
  compatible = "qcom,sc8280xp-lpass-ag-noc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 mc_virt: interconnect-mc-virt {
  compatible = "qcom,sc8280xp-mc-virt";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 mmss_noc: interconnect-mmss-noc {
  compatible = "qcom,sc8280xp-mmss-noc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 nspa_noc: interconnect-nspa-noc {
  compatible = "qcom,sc8280xp-nspa-noc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 nspb_noc: interconnect-nspb-noc {
  compatible = "qcom,sc8280xp-nspb-noc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 system_noc: interconnect-system-noc {
  compatible = "qcom,sc8280xp-system-noc";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 memory@80000000 {
  device_type = "memory";
  /* We expect the bootloader to fill in the size */
  reg = <0x0 0x80000000 0x0 0x0>;
 };

 cpu0_opp_table: opp-table-cpu0 {
  compatible = "operating-points-v2";
  opp-shared;

  opp-300000000 {
   opp-hz = /bits/ 64 <300000000>;
   opp-peak-kBps = <(300000 * 32)>;
  };
  opp-403200000 {
   opp-hz = /bits/ 64 <403200000>;
   opp-peak-kBps = <(384000 * 32)>;
  };
  opp-499200000 {
   opp-hz = /bits/ 64 <499200000>;
   opp-peak-kBps = <(480000 * 32)>;
  };
  opp-595200000 {
   opp-hz = /bits/ 64 <595200000>;
   opp-peak-kBps = <(576000 * 32)>;
  };
  opp-691200000 {
   opp-hz = /bits/ 64 <691200000>;
   opp-peak-kBps = <(672000 * 32)>;
  };
  opp-806400000 {
   opp-hz = /bits/ 64 <806400000>;
   opp-peak-kBps = <(768000 * 32)>;
  };
  opp-902400000 {
   opp-hz = /bits/ 64 <902400000>;
   opp-peak-kBps = <(864000 * 32)>;
  };
  opp-1017600000 {
   opp-hz = /bits/ 64 <1017600000>;
   opp-peak-kBps = <(960000 * 32)>;
  };
  opp-1113600000 {
   opp-hz = /bits/ 64 <1113600000>;
   opp-peak-kBps = <(1075200 * 32)>;
  };
  opp-1209600000 {
   opp-hz = /bits/ 64 <1209600000>;
   opp-peak-kBps = <(1171200 * 32)>;
  };
  opp-1324800000 {
   opp-hz = /bits/ 64 <1324800000>;
   opp-peak-kBps = <(1267200 * 32)>;
  };
  opp-1440000000 {
   opp-hz = /bits/ 64 <1440000000>;
   opp-peak-kBps = <(1363200 * 32)>;
  };
  opp-1555200000 {
   opp-hz = /bits/ 64 <1555200000>;
   opp-peak-kBps = <(1536000 * 32)>;
  };
  opp-1670400000 {
   opp-hz = /bits/ 64 <1670400000>;
   opp-peak-kBps = <(1612800 * 32)>;
  };
  opp-1785600000 {
   opp-hz = /bits/ 64 <1785600000>;
   opp-peak-kBps = <(1689600 * 32)>;
  };
  opp-1881600000 {
   opp-hz = /bits/ 64 <1881600000>;
   opp-peak-kBps = <(1689600 * 32)>;
  };
  opp-1996800000 {
   opp-hz = /bits/ 64 <1996800000>;
   opp-peak-kBps = <(1689600 * 32)>;
  };
  opp-2112000000 {
   opp-hz = /bits/ 64 <2112000000>;
   opp-peak-kBps = <(1689600 * 32)>;
  };
  opp-2227200000 {
   opp-hz = /bits/ 64 <2227200000>;
   opp-peak-kBps = <(1689600 * 32)>;
  };
  opp-2342400000 {
   opp-hz = /bits/ 64 <2342400000>;
   opp-peak-kBps = <(1689600 * 32)>;
  };
  opp-2438400000 {
   opp-hz = /bits/ 64 <2438400000>;
   opp-peak-kBps = <(1689600 * 32)>;
  };
 };

 cpu4_opp_table: opp-table-cpu4 {
  compatible = "operating-points-v2";
  opp-shared;

  opp-825600000 {
   opp-hz = /bits/ 64 <825600000>;
   opp-peak-kBps = <(768000 * 32)>;
  };
  opp-940800000 {
   opp-hz = /bits/ 64 <940800000>;
   opp-peak-kBps = <(864000 * 32)>;
  };
  opp-1056000000 {
   opp-hz = /bits/ 64 <1056000000>;
   opp-peak-kBps = <(960000 * 32)>;
  };
  opp-1171200000 {
   opp-hz = /bits/ 64 <1171200000>;
   opp-peak-kBps = <(1171200 * 32)>;
  };
  opp-1286400000 {
   opp-hz = /bits/ 64 <1286400000>;
   opp-peak-kBps = <(1267200 * 32)>;
  };
  opp-1401600000 {
   opp-hz = /bits/ 64 <1401600000>;
   opp-peak-kBps = <(1363200 * 32)>;
  };
  opp-1516800000 {
   opp-hz = /bits/ 64 <1516800000>;
   opp-peak-kBps = <(1459200 * 32)>;
  };
  opp-1632000000 {
   opp-hz = /bits/ 64 <1632000000>;
   opp-peak-kBps = <(1612800 * 32)>;
  };
  opp-1747200000 {
   opp-hz = /bits/ 64 <1747200000>;
   opp-peak-kBps = <(1689600 * 32)>;
  };
  opp-1862400000 {
   opp-hz = /bits/ 64 <1862400000>;
   opp-peak-kBps = <(1689600 * 32)>;
  };
  opp-1977600000 {
   opp-hz = /bits/ 64 <1977600000>;
   opp-peak-kBps = <(1689600 * 32)>;
  };
  opp-2073600000 {
   opp-hz = /bits/ 64 <2073600000>;
   opp-peak-kBps = <(1689600 * 32)>;
  };
  opp-2169600000 {
   opp-hz = /bits/ 64 <2169600000>;
   opp-peak-kBps = <(1689600 * 32)>;
  };
  opp-2284800000 {
   opp-hz = /bits/ 64 <2284800000>;
   opp-peak-kBps = <(1689600 * 32)>;
  };
  opp-2400000000 {
   opp-hz = /bits/ 64 <2400000000>;
   opp-peak-kBps = <(1689600 * 32)>;
  };
  opp-2496000000 {
   opp-hz = /bits/ 64 <2496000000>;
   opp-peak-kBps = <(1689600 * 32)>;
  };
  opp-2592000000 {
   opp-hz = /bits/ 64 <2592000000>;
   opp-peak-kBps = <(1689600 * 32)>;
  };
  opp-2688000000 {
   opp-hz = /bits/ 64 <2688000000>;
   opp-peak-kBps = <(1689600 * 32)>;
  };
  opp-2803200000 {
   opp-hz = /bits/ 64 <2803200000>;
   opp-peak-kBps = <(1689600 * 32)>;
  };
  opp-2899200000 {
   opp-hz = /bits/ 64 <2899200000>;
   opp-peak-kBps = <(1689600 * 32)>;
  };
  opp-2995200000 {
   opp-hz = /bits/ 64 <2995200000>;
   opp-peak-kBps = <(1689600 * 32)>;
  };
 };

 qup_opp_table_100mhz: opp-table-qup100mhz {
  compatible = "operating-points-v2";

  opp-75000000 {
   opp-hz = /bits/ 64 <75000000>;
   required-opps = <&rpmhpd_opp_low_svs>;
  };

  opp-100000000 {
   opp-hz = /bits/ 64 <100000000>;
   required-opps = <&rpmhpd_opp_svs>;
  };
 };

 pmu {
  compatible = "arm,armv8-pmuv3";
  interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 };

 psci {
  compatible = "arm,psci-1.0";
  method = "smc";

  cpu_pd0: power-domain-cpu0 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0>;
  };

  cpu_pd1: power-domain-cpu1 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0>;
  };

  cpu_pd2: power-domain-cpu2 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0>;
  };

  cpu_pd3: power-domain-cpu3 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0>;
  };

  cpu_pd4: power-domain-cpu4 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0>;
  };

  cpu_pd5: power-domain-cpu5 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0>;
  };

  cpu_pd6: power-domain-cpu6 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0>;
  };

  cpu_pd7: power-domain-cpu7 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0>;
  };

  cluster_pd: power-domain-cpu-cluster0 {
   #power-domain-cells = <0>;
   domain-idle-states = <&cluster_sleep_0>;
  };
 };

 reserved-memory {
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  reserved-region@80000000 {
   reg = <0 0x80000000 0 0x860000>;
   no-map;
  };

  cmd_db: cmd-db-region@80860000 {
   compatible = "qcom,cmd-db";
   reg = <0 0x80860000 0 0x20000>;
   no-map;
  };

  reserved-region@80880000 {
   reg = <0 0x80880000 0 0x80000>;
   no-map;
  };

  smem_mem: smem-region@80900000 {
   compatible = "qcom,smem";
   reg = <0 0x80900000 0 0x200000>;
   no-map;
   hwlocks = <&tcsr_mutex 3>;
  };

  reserved-region@80b00000 {
   reg = <0 0x80b00000 0 0x100000>;
   no-map;
  };

  reserved-region@83b00000 {
   reg = <0 0x83b00000 0 0x1700000>;
   no-map;
  };

  reserved-region@85b00000 {
   reg = <0 0x85b00000 0 0xc00000>;
   no-map;
  };

  pil_adsp_mem: adsp-region@86c00000 {
   reg = <0 0x86c00000 0 0x2000000>;
   no-map;
  };

  pil_slpi_mem: slpi-region@88c00000 {
   reg = <0 0x88c00000 0 0x1500000>;
   no-map;
  };

  pil_nsp0_mem: cdsp0-region@8a100000 {
   reg = <0 0x8a100000 0 0x1e00000>;
   no-map;
  };

  pil_nsp1_mem: cdsp1-region@8c600000 {
   reg = <0 0x8c600000 0 0x1e00000>;
   no-map;
  };

  reserved-region@aeb00000 {
   reg = <0 0xaeb00000 0 0x16600000>;
   no-map;
  };
 };

 smp2p-adsp {
  compatible = "qcom,smp2p";
  qcom,smem = <443>, <429>;
  interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
          IPCC_MPROC_SIGNAL_SMP2P
          IRQ_TYPE_EDGE_RISING>;
  mboxes = <&ipcc IPCC_CLIENT_LPASS
    IPCC_MPROC_SIGNAL_SMP2P>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <2>;

  smp2p_adsp_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  smp2p_adsp_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-nsp0 {
  compatible = "qcom,smp2p";
  qcom,smem = <94>, <432>;
  interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
          IPCC_MPROC_SIGNAL_SMP2P
          IRQ_TYPE_EDGE_RISING>;
  mboxes = <&ipcc IPCC_CLIENT_CDSP
    IPCC_MPROC_SIGNAL_SMP2P>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <5>;

  smp2p_nsp0_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  smp2p_nsp0_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-nsp1 {
  compatible = "qcom,smp2p";
  qcom,smem = <617>, <616>;
  interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
          IPCC_MPROC_SIGNAL_SMP2P
          IRQ_TYPE_EDGE_RISING>;
  mboxes = <&ipcc IPCC_CLIENT_NSP1
    IPCC_MPROC_SIGNAL_SMP2P>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <12>;

  smp2p_nsp1_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  smp2p_nsp1_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-slpi {
  compatible = "qcom,smp2p";
  qcom,smem = <481>, <430>;
  interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
          IPCC_MPROC_SIGNAL_SMP2P
          IRQ_TYPE_EDGE_RISING>;
  mboxes = <&ipcc IPCC_CLIENT_SLPI
    IPCC_MPROC_SIGNAL_SMP2P>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <3>;

  smp2p_slpi_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  smp2p_slpi_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 soc: soc@0 {
  compatible = "simple-bus";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges = <0 0 0 0 0x10 0>;
  dma-ranges = <0 0 0 0 0x10 0>;

  ethernet0: ethernet@20000 {
   compatible = "qcom,sc8280xp-ethqos";
   reg = <0x0 0x00020000 0x0 0x10000>,
         <0x0 0x00036000 0x0 0x100>;
   reg-names = "stmmaceth", "rgmii";

   clocks = <&gcc GCC_EMAC0_AXI_CLK>,
     <&gcc GCC_EMAC0_SLV_AHB_CLK>,
     <&gcc GCC_EMAC0_PTP_CLK>,
     <&gcc GCC_EMAC0_RGMII_CLK>;
   clock-names = "stmmaceth",
          "pclk",
          "ptp_ref",
          "rgmii";

   interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "macirq", "eth_lpi";

   iommus = <&apps_smmu 0x4c0 0xf>;
   power-domains = <&gcc EMAC_0_GDSC>;

   snps,tso;
   snps,pbl = <32>;
   rx-fifo-depth = <4096>;
   tx-fifo-depth = <4096>;

   status = "disabled";
  };

  gcc: clock-controller@100000 {
   compatible = "qcom,gcc-sc8280xp";
   reg = <0x0 0x00100000 0x0 0x1f0000>;
   #clock-cells = <1>;
   #reset-cells = <1>;
   #power-domain-cells = <1>;
   clocks = <&rpmhcc RPMH_CXO_CLK>,
     <&sleep_clk>,
     <0>,
     <0>,
     <0>,
     <0>,
     <0>,
     <0>,
     <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
     <0>,
     <0>,
     <0>,
     <0>,
     <0>,
     <0>,
     <0>,
     <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
     <0>,
     <0>,
     <0>,
     <0>,
     <0>,
     <0>,
     <0>,
     <0>,
     <0>,
     <&pcie2a_phy>,
     <&pcie2b_phy>,
     <&pcie3a_phy>,
     <&pcie3b_phy>,
     <&pcie4_phy>,
     <0>,
     <0>;
   power-domains = <&rpmhpd SC8280XP_CX>;
  };

  ipcc: mailbox@408000 {
   compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
   reg = <0 0x00408000 0 0x1000>;
   interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-controller;
   #interrupt-cells = <3>;
   #mbox-cells = <2>;
  };

  qfprom: efuse@784000 {
   compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom";
   reg = <0 0x00784000 0 0x3000>;
   #address-cells = <1>;
   #size-cells = <1>;

   gpu_speed_bin: gpu-speed-bin@18b {
    reg = <0x18b 0x1>;
    bits = <5 3>;
   };
  };

  qup2: geniqup@8c0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0 0x008c0000 0 0x2000>;
   clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
     <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
   clock-names = "m-ahb", "s-ahb";
   iommus = <&apps_smmu 0xa3 0>;

   #address-cells = <2>;
   #size-cells = <2>;
   ranges;

   status = "disabled";

   i2c16: i2c@880000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00880000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
                    <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi16: spi@880000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00880000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
                    <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   i2c17: i2c@884000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00884000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
                    <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi17: spi@884000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00884000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
                    <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   uart17: serial@884000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00884000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
    operating-points-v2 = <&qup_opp_table_100mhz>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c18: i2c@888000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00888000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
                    <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi18: spi@888000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00888000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
                    <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   uart18: serial@888000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00888000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
    operating-points-v2 = <&qup_opp_table_100mhz>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
    interconnect-names = "qup-core", "qup-config";

    pinctrl-0 = <&qup_uart18_default>;
    pinctrl-names = "default";

    status = "disabled";
   };

   i2c19: i2c@88c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x0088c000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
                    <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi19: spi@88c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x0088c000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
                    <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   i2c20: i2c@890000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00890000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
                    <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi20: spi@890000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00890000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
                    <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   i2c21: i2c@894000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00894000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
    interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
      <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi21: spi@894000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00894000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
                    <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   i2c22: i2c@898000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00898000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
    interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
      <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi22: spi@898000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00898000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
                    <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   i2c23: i2c@89c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x0089c000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
    interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
      <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi23: spi@89c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x0089c000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
                    <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };
  };

  qup0: geniqup@9c0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0 0x009c0000 0 0x6000>;
   clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
     <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
   clock-names = "m-ahb", "s-ahb";
   iommus = <&apps_smmu 0x563 0>;

   #address-cells = <2>;
   #size-cells = <2>;
   ranges;

   status = "disabled";

   i2c0: i2c@980000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00980000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi0: spi@980000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00980000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   i2c1: i2c@984000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00984000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
    interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi1: spi@984000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00984000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   i2c2: i2c@988000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00988000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
    interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi2: spi@988000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00988000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   uart2: serial@988000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00988000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
    operating-points-v2 = <&qup_opp_table_100mhz>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c3: i2c@98c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x0098c000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
    interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi3: spi@98c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x0098c000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   i2c4: i2c@990000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00990000 0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
    interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi4: spi@990000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00990000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   i2c5: i2c@994000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00994000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
    interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi5: spi@994000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00994000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   i2c6: i2c@998000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00998000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
    interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi6: spi@998000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00998000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   i2c7: i2c@99c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x0099c000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
    interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi7: spi@99c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x0099c000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };
  };

  qup1: geniqup@ac0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0 0x00ac0000 0 0x6000>;
   clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
     <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
   clock-names = "m-ahb", "s-ahb";
   iommus = <&apps_smmu 0x83 0>;

   #address-cells = <2>;
   #size-cells = <2>;
   ranges;

   status = "disabled";

   i2c8: i2c@a80000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a80000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
                    <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi8: spi@a80000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a80000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
                    <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   i2c9: i2c@a84000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a84000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
                    <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi9: spi@a84000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a84000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
                    <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   i2c10: i2c@a88000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a88000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
                    <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi10: spi@a88000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a88000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
                    <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   i2c11: i2c@a8c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a8c000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
                    <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi11: spi@a8c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a8c000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
                    <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   i2c12: i2c@a90000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a90000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
                    <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi12: spi@a90000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a90000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
                    <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   i2c13: i2c@a94000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a94000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
                    <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi13: spi@a94000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a94000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
                    <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   i2c14: i2c@a98000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a98000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
                    <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi14: spi@a98000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a98000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
                    <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   i2c15: i2c@a9c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a9c000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
                    <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };

   spi15: spi@a9c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a9c000 0 0x4000>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
    clock-names = "se";
    interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC8280XP_CX>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
                    <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
                    <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    status = "disabled";
   };
  };

  rng: rng@10d3000 {
   compatible = "qcom,prng-ee";
   reg = <0 0x010d3000 0 0x1000>;
   clocks = <&rpmhcc RPMH_HWKM_CLK>;
   clock-names = "core";
  };

  pcie4: pcie@1c00000 {
   device_type = "pci";
   compatible = "qcom,pcie-sc8280xp";
   reg = <0x0 0x01c00000 0x0 0x3000>,
         <0x0 0x30000000 0x0 0xf1d>,
         <0x0 0x30000f20 0x0 0xa8>,
         <0x0 0x30001000 0x0 0x1000>,
         <0x0 0x30100000 0x0 0x100000>,
         <0x0 0x01c03000 0x0 0x1000>;
   reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
   #address-cells = <3>;
   #size-cells = <2>;
   ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>,
     <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
   bus-range = <0x00 0xff>;

   dma-coherent;

   linux,pci-domain = <6>;
   num-lanes = <1>;

   msi-map = <0x0 &its 0xe0000 0x10000>;

   interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "msi0", "msi1", "msi2", "msi3";

   #interrupt-cells = <1>;
   interrupt-map-mask = <0 0 0 0x7>;
   interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
     <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
     <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
     <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;

   clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
     <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
     <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
     <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
     <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
     <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
     <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
     <&gcc GCC_CNOC_PCIE4_QX_CLK>;
   clock-names = "aux",
          "cfg",
          "bus_master",
          "bus_slave",
          "slave_q2a",
          "ddrss_sf_tbu",
          "noc_aggr_4",
          "noc_aggr_south_sf",
          "cnoc_qx";

   assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
   assigned-clock-rates = <19200000>;

   interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
     <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
   interconnect-names = "pcie-mem", "cpu-pcie";

   resets = <&gcc GCC_PCIE_4_BCR>;
   reset-names = "pci";

   power-domains = <&gcc PCIE_4_GDSC>;
   required-opps = <&rpmhpd_opp_nom>;

   phys = <&pcie4_phy>;
   phy-names = "pciephy";

   status = "disabled";

   pcie4_port0: pcie@0 {
    device_type = "pci";
    reg = <0x0 0x0 0x0 0x0 0x0>;
    bus-range = <0x01 0xff>;

    #address-cells = <3>;
    #size-cells = <2>;
    ranges;
   };
  };

  pcie4_phy: phy@1c06000 {
   compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
   reg = <0x0 0x01c06000 0x0 0x2000>;

   clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
     <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_4_CLKREF_CLK>,
     <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
     <&gcc GCC_PCIE_4_PIPE_CLK>,
     <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
   clock-names = "aux", "cfg_ahb", "ref", "rchng",
          "pipe", "pipediv2";

   assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
   assigned-clock-rates = <100000000>;

   power-domains = <&gcc PCIE_4_GDSC>;

   resets = <&gcc GCC_PCIE_4_PHY_BCR>;
   reset-names = "phy";

   #clock-cells = <0>;
   clock-output-names = "pcie_4_pipe_clk";

   #phy-cells = <0>;

   status = "disabled";
  };

  pcie3b: pcie@1c08000 {
   device_type = "pci";
   compatible = "qcom,pcie-sc8280xp";
   reg = <0x0 0x01c08000 0x0 0x3000>,
         <0x0 0x32000000 0x0 0xf1d>,
         <0x0 0x32000f20 0x0 0xa8>,
         <0x0 0x32001000 0x0 0x1000>,
         <0x0 0x32100000 0x0 0x100000>,
         <0x0 0x01c0b000 0x0 0x1000>;
   reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
   #address-cells = <3>;
   #size-cells = <2>;
   ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>,
     <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
   bus-range = <0x00 0xff>;

   dma-coherent;

   linux,pci-domain = <5>;
   num-lanes = <2>;

   msi-map = <0x0 &its 0xd0000 0x10000>;

   interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "msi0", "msi1", "msi2", "msi3";

   #interrupt-cells = <1>;
   interrupt-map-mask = <0 0 0 0x7>;
   interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
     <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
     <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
     <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;

   clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
     <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
     <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
     <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
     <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
     <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
     <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
   clock-names = "aux",
          "cfg",
          "bus_master",
          "bus_slave",
          "slave_q2a",
          "ddrss_sf_tbu",
          "noc_aggr_4",
          "noc_aggr_south_sf";

   assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
   assigned-clock-rates = <19200000>;

   interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
     <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
   interconnect-names = "pcie-mem", "cpu-pcie";

   resets = <&gcc GCC_PCIE_3B_BCR>;
   reset-names = "pci";

   power-domains = <&gcc PCIE_3B_GDSC>;
   required-opps = <&rpmhpd_opp_nom>;

   phys = <&pcie3b_phy>;
   phy-names = "pciephy";

   status = "disabled";

   pcie3b_port0: pcie@0 {
    device_type = "pci";
    reg = <0x0 0x0 0x0 0x0 0x0>;
    bus-range = <0x01 0xff>;

    #address-cells = <3>;
    #size-cells = <2>;
    ranges;
   };
  };

  pcie3b_phy: phy@1c0e000 {
   compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
   reg = <0x0 0x01c0e000 0x0 0x2000>;

   clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
     <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
     <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
     <&gcc GCC_PCIE_3B_PIPE_CLK>,
     <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
   clock-names = "aux", "cfg_ahb", "ref", "rchng",
          "pipe", "pipediv2";

   assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
   assigned-clock-rates = <100000000>;

   power-domains = <&gcc PCIE_3B_GDSC>;

   resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
   reset-names = "phy";

   #clock-cells = <0>;
   clock-output-names = "pcie_3b_pipe_clk";

   #phy-cells = <0>;

   status = "disabled";
  };

  pcie3a: pcie@1c10000 {
   device_type = "pci";
   compatible = "qcom,pcie-sc8280xp";
   reg = <0x0 0x01c10000 0x0 0x3000>,
         <0x0 0x34000000 0x0 0xf1d>,
         <0x0 0x34000f20 0x0 0xa8>,
         <0x0 0x34001000 0x0 0x1000>,
         <0x0 0x34100000 0x0 0x100000>,
         <0x0 0x01c13000 0x0 0x1000>;
   reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
   #address-cells = <3>;
   #size-cells = <2>;
   ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>,
     <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
   bus-range = <0x00 0xff>;

   dma-coherent;

   linux,pci-domain = <4>;
   num-lanes = <4>;

   msi-map = <0x0 &its 0xc0000 0x10000>;

   interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "msi0", "msi1", "msi2", "msi3";

   #interrupt-cells = <1>;
   interrupt-map-mask = <0 0 0 0x7>;
   interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
     <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
     <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
     <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;

   clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
     <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
     <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
     <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
     <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
     <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
     <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
   clock-names = "aux",
          "cfg",
          "bus_master",
          "bus_slave",
          "slave_q2a",
          "ddrss_sf_tbu",
          "noc_aggr_4",
          "noc_aggr_south_sf";

   assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
   assigned-clock-rates = <19200000>;

   interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
     <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
   interconnect-names = "pcie-mem", "cpu-pcie";

   resets = <&gcc GCC_PCIE_3A_BCR>;
   reset-names = "pci";

   power-domains = <&gcc PCIE_3A_GDSC>;
   required-opps = <&rpmhpd_opp_nom>;

   phys = <&pcie3a_phy>;
   phy-names = "pciephy";

   status = "disabled";

   pcie3a_port0: pcie@0 {
    device_type = "pci";
    reg = <0x0 0x0 0x0 0x0 0x0>;
    bus-range = <0x01 0xff>;

    #address-cells = <3>;
    #size-cells = <2>;
    ranges;
   };
  };

  pcie3a_phy: phy@1c14000 {
   compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
   reg = <0x0 0x01c14000 0x0 0x2000>,
         <0x0 0x01c16000 0x0 0x2000>;

   clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
     <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
     <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
     <&gcc GCC_PCIE_3A_PIPE_CLK>,
     <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
   clock-names = "aux", "cfg_ahb", "ref", "rchng",
          "pipe", "pipediv2";

   assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
   assigned-clock-rates = <100000000>;

   power-domains = <&gcc PCIE_3A_GDSC>;

   resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
   reset-names = "phy";

   qcom,4ln-config-sel = <&tcsr 0xa044 1>;

   #clock-cells = <0>;
   clock-output-names = "pcie_3a_pipe_clk";

   #phy-cells = <0>;

   status = "disabled";
  };

  pcie2b: pcie@1c18000 {
   device_type = "pci";
   compatible = "qcom,pcie-sc8280xp";
   reg = <0x0 0x01c18000 0x0 0x3000>,
         <0x0 0x38000000 0x0 0xf1d>,
         <0x0 0x38000f20 0x0 0xa8>,
         <0x0 0x38001000 0x0 0x1000>,
         <0x0 0x38100000 0x0 0x100000>,
         <0x0 0x01c1b000 0x0 0x1000>;
   reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
   #address-cells = <3>;
   #size-cells = <2>;
   ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>,
     <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
   bus-range = <0x00 0xff>;

   dma-coherent;

   linux,pci-domain = <3>;
   num-lanes = <2>;

   msi-map = <0x0 &its 0xb0000 0x10000>;

   interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "msi0", "msi1", "msi2", "msi3";

   #interrupt-cells = <1>;
   interrupt-map-mask = <0 0 0 0x7>;
   interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
     <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
     <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
     <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;

   clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
     <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
     <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
     <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
     <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
     <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
     <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
   clock-names = "aux",
          "cfg",
          "bus_master",
          "bus_slave",
          "slave_q2a",
          "ddrss_sf_tbu",
          "noc_aggr_4",
          "noc_aggr_south_sf";

   assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
   assigned-clock-rates = <19200000>;

--> --------------------

--> maximum size reached

--> --------------------