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# SPDX-License-Identifier: (GPL-
2.
0 OR BSD-
2-Clause)
# Copyright
2020-
21 Cadence
%YAML
1.
2
---
$id:
http://devicetree.org/schemas/spi/cdns,xspi.yaml#
$schema:
http://devicetree.org/meta-schemas/core.yaml#
title: Cadence XSPI Controller
maintainers:
- Parshuram Thombare <pthombar@cadence.com>
description: |
The XSPI controller allows SPI protocol communication in
single, dual, quad or octal wire transmission modes for
read/write access to slaves such as SPI-NOR flash.
properties:
compatible:
enum:
- cdns,xspi-nor
- marvell,cn10-xspi-nor
reg:
items:
- description: address and length of the controller register set
- description: address and length of the Slave DMA data port
- description: address and length of the auxiliary registers
- description: address and length of the xfer registers
minItems:
3
reg-names:
items:
- const: io
- const: sdma
- const: aux
- const: xfer
minItems:
3
interrupts:
maxItems:
1
required:
- compatible
- reg
- interrupts
allOf:
- $ref: spi-controller.yaml#
- if:
properties:
compatible:
contains:
enum:
- marvell,cn10-xspi-nor
then:
properties:
reg:
minItems:
4
reg-names:
minItems:
4
else:
properties:
reg:
maxItems:
3
reg-names:
maxItems:
3
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
bus {
#address-cells = <
2>;
#size-cells = <
2>;
xspi: spi@a0010000 {
#address-cells = <
1>;
#size-cells = <
0>;
compatible = "cdns,xspi-nor";
reg = <
0x0
0xa0010000
0x0
0x1040>,
<
0x0
0xb0000000
0x0
0x1000>,
<
0x0
0xa0020000
0x0
0x100>;
reg-names = "io", "sdma", "aux";
interrupts = <
0 90 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
flash@
0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <
75000000>;
reg = <
0>;
};
flash@
1 {
compatible = "jedec,spi-nor";
spi-max-frequency = <
75000000>;
reg = <
1>;
};
};
};