static LIR_Opr make_constant(BasicType type, jlong c) { switch (type) { case T_ADDRESS: case T_OBJECT: return LIR_OprFact::intptrConst(c); case T_LONG: return LIR_OprFact::longConst(c); case T_INT: return LIR_OprFact::intConst(c); default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
}
}
void LIRGenerator::add_large_constant(LIR_Opr src, int c, LIR_Opr dest) {
assert(c != 0, "must be"); // Find first non-zero bit int shift = 0; while ((c & (3 << shift)) == 0) {
shift += 2;
} // Add the least significant part of the constant int mask = 0xff << shift;
__ add(src, LIR_OprFact::intConst(c & mask), dest); // Add up to 3 other parts of the constant; // each of them can be represented as rotated_imm if (c & (mask << 8)) {
__ add(dest, LIR_OprFact::intConst(c & (mask << 8)), dest);
} if (c & (mask << 16)) {
__ add(dest, LIR_OprFact::intConst(c & (mask << 16)), dest);
} if (c & (mask << 24)) {
__ add(dest, LIR_OprFact::intConst(c & (mask << 24)), dest);
}
}
LIR_Address* LIRGenerator::generate_address(LIR_Opr base, LIR_Opr index, int shift, int disp, BasicType type) {
assert(base->is_register(), "must be");
if (index->is_constant()) {
disp += index->as_constant_ptr()->as_jint() << shift;
index = LIR_OprFact::illegalOpr;
}
if (base->type() == T_LONG) {
LIR_Opr tmp = new_register(T_INT);
__ convert(Bytecodes::_l2i, base, tmp);
base = tmp;
} if (index != LIR_OprFact::illegalOpr && index->type() == T_LONG) {
LIR_Opr tmp = new_register(T_INT);
__ convert(Bytecodes::_l2i, index, tmp);
index = tmp;
} // At this point base and index should be all ints and not constants
assert(base->is_single_cpu() && !base->is_constant(), "base should be an non-constant int");
assert(index->is_illegal() || (index->type() == T_INT && !index->is_constant()), "index should be an non-constant int");
int max_disp; bool disp_is_in_range; bool embedded_shift;
switch (type) { case T_BYTE: case T_SHORT: case T_CHAR:
max_disp = 256; // ldrh, ldrsb encoding has 8-bit offset
embedded_shift = false; break; case T_FLOAT: case T_DOUBLE:
max_disp = 1024; // flds, fldd have 8-bit offset multiplied by 4
embedded_shift = false; break; case T_LONG:
max_disp = 4096;
embedded_shift = false; break; default:
max_disp = 4096; // ldr, ldrb allow 12-bit offset
embedded_shift = true;
}
if (index->is_register()) {
LIR_Opr tmp = new_pointer_register(); if (!disp_is_in_range) {
add_large_constant(base, disp, tmp);
base = tmp;
disp = 0;
}
LIR_Address* addr = make_address(base, index, (LIR_Address::Scale)shift, type); if (disp == 0 && embedded_shift) { // can use ldr/str instruction with register index return addr;
} else {
LIR_Opr tmp = new_pointer_register();
__ add(base, LIR_OprFact::address(addr), tmp); // add with shifted/extended register returnnew LIR_Address(tmp, disp, type);
}
}
// If the displacement is too large to be inlined into LDR instruction, // generate large constant with additional sequence of ADD instructions int excess_disp = disp & ~(max_disp - 1); if (excess_disp != 0) {
LIR_Opr tmp = new_pointer_register();
add_large_constant(base, excess_disp, tmp);
base = tmp;
} returnnew LIR_Address(base, disp & (max_disp - 1), type);
}
LIR_Address* LIRGenerator::emit_array_address(LIR_Opr array_opr, LIR_Opr index_opr, BasicType type) { int base_offset = arrayOopDesc::base_offset_in_bytes(type); int elem_size = type2aelembytes(type);
void LIRGenerator::store_stack_parameter(LIR_Opr item, ByteSize offset_from_sp) {
assert(item->type() == T_INT, "other types are not expected");
__ store(item, new LIR_Address(FrameMap::SP_opr, in_bytes(offset_from_sp), item->type()));
}
void LIRGenerator::set_card(LIR_Opr value, LIR_Address* card_addr) {
assert(CardTable::dirty_card_val() == 0, "Cannot use the register containing the card table base address directly"); if((ci_card_table_address_as<intx>() & 0xff) == 0) { // If the card table base address is aligned to 256 bytes, we can use the register // that contains the card_table_base_address.
__ move(value, card_addr);
} else { // Otherwise we need to create a register containing that value.
LIR_Opr tmp_zero = new_register(T_INT);
__ move(LIR_OprFact::intConst(CardTable::dirty_card_val()), tmp_zero);
__ move(tmp_zero, card_addr);
}
}
void LIRGenerator::CardTableBarrierSet_post_barrier_helper(LIR_Opr addr, LIR_Const* card_table_base) {
assert(addr->is_register(), "must be a register at this point");
// Use unsigned type T_BOOLEAN here rather than (signed) T_BYTE since signed load // byte instruction does not support the addressing mode we need.
LIR_Address* card_addr = new LIR_Address(tmp, addr, (LIR_Address::Scale) -CardTable::card_shift(), 0, T_BOOLEAN); if (UseCondCardMark) {
LIR_Opr cur_value = new_register(T_INT);
__ move(card_addr, cur_value);
// We put arguments into the same registers which are used for a Java call. // Note: we used fixed registers for all arguments because all registers // are caller-saved, so register allocator treats them all as used.
src.load_item_force (FrameMap::R0_oop_opr);
src_pos.load_item_force(FrameMap::R1_opr);
dst.load_item_force (FrameMap::R2_oop_opr);
dst_pos.load_item_force(FrameMap::R3_opr);
length.load_item_force (FrameMap::R4_opr);
LIR_Opr tmp = (FrameMap::R5_opr);
set_no_result(x);
LIR_Opr result = rlock_result(x);
__ move(reg, result);
}
void LIRGenerator::do_NewTypeArray(NewTypeArray* x) { // Evaluate state_for() first, because it can emit code // with the same fixed registers that are used here (R1, R2)
CodeEmitInfo* info = state_for(x, x->state());
LIRItem length(x->length(), this);
length.load_item_force(FrameMap::R2_opr); // R2 is required by runtime call in NewTypeArrayStub::emit_code
LIR_Opr len = length.result();
LIR_Opr reg = result_register_for(x->type()); // R0 is required by runtime call in NewTypeArrayStub::emit_code
LIR_Opr klass_reg = FrameMap::R1_metadata_opr; // R1 is required by runtime call in NewTypeArrayStub::emit_code
LIR_Opr result = rlock_result(x);
__ move(reg, result);
}
void LIRGenerator::do_NewObjectArray(NewObjectArray* x) { // Evaluate state_for() first, because it can emit code // with the same fixed registers that are used here (R1, R2)
CodeEmitInfo* info = state_for(x, x->state());
LIRItem length(x->length(), this);
length.load_item_force(FrameMap::R2_opr); // R2 is required by runtime call in NewObjectArrayStub::emit_code
LIR_Opr len = length.result();
LIR_Opr reg = result_register_for(x->type()); // R0 is required by runtime call in NewObjectArrayStub::emit_code
LIR_Opr klass_reg = FrameMap::R1_metadata_opr; // R1 is required by runtime call in NewObjectArrayStub::emit_code
CodeStub* slow_path = new NewObjectArrayStub(klass_reg, len, reg, info);
ciMetadata* obj = ciObjArrayKlass::make(x->klass()); if (obj == ciEnv::unloaded_ciobjarrayklass()) {
BAILOUT("encountered unloaded_ciobjarrayklass due to out of memory error");
}
klass2reg_with_patching(klass_reg, obj, patching_info);
__ allocate_array(reg, len, tmp1, tmp2, tmp3, tmp4, T_OBJECT, klass_reg, slow_path);
LIR_Opr result = rlock_result(x);
__ move(reg, result);
}
void LIRGenerator::do_NewMultiArray(NewMultiArray* x) {
Values* dims = x->dims(); int i = dims->length();
LIRItemList* items = new LIRItemList(i, i, NULL); while (i-- > 0) {
LIRItem* size = new LIRItem(dims->at(i), this);
items->at_put(i, size);
}
// Need to get the info before, as the items may become invalid through item_free
CodeEmitInfo* patching_info = NULL; if (!x->klass()->is_loaded() || PatchALot) {
patching_info = state_for(x, x->state_before());
// Cannot re-use same xhandlers for multiple CodeEmitInfos, so // clone all handlers (NOTE: Usually this is handled transparently // by the CodeEmitInfo cloning logic in CodeStub constructors but // is done explicitly here because a stub isn't being used).
x->set_exception_handlers(new XHandlers(x->exception_handlers()));
}
xin->load_item();
LIR_Opr left = xin->result();
LIR_Opr right;
if (tag == longTag && yin->is_constant() && yin->get_jlong_constant() == 0 &&
(cond == If::eql || cond == If::neq)) { // inline long zero
right = LIR_OprFact::value_type(yin->value()->type());
} else {
yin->load_nonconstant();
right = yin->result();
}
set_no_result(x);
// add safepoint before generating condition code so it can be recomputed if (x->is_safepoint()) {
increment_backedge_counter_conditionally(lir_cond(cond), left, right, state_for(x, x->state_before()),
x->tsux()->bci(), x->fsux()->bci(), x->profiled_bci());
__ safepoint(LIR_OprFact::illegalOpr, state_for(x, x->state_before()));
}
void LIRGenerator::volatile_field_store(LIR_Opr value, LIR_Address* address,
CodeEmitInfo* info) { if (value->is_double_cpu()) {
assert(address->index()->is_illegal(), "should have a constant displacement");
LIR_Address* store_addr = NULL; if (address->disp() != 0) {
LIR_Opr tmp = new_pointer_register();
add_large_constant(address->base(), address->disp(), tmp);
store_addr = new LIR_Address(tmp, (intx)0, address->type());
} else { // address->disp() can be 0, if the address is referenced using the unsafe intrinsic
store_addr = address;
}
__ volatile_store_mem_reg(value, store_addr, info); return;
}
__ store(value, address, info, lir_patch_none);
}
void LIRGenerator::volatile_field_load(LIR_Address* address, LIR_Opr result,
CodeEmitInfo* info) { if (result->is_double_cpu()) {
assert(address->index()->is_illegal(), "should have a constant displacement");
LIR_Address* load_addr = NULL; if (address->disp() != 0) {
LIR_Opr tmp = new_pointer_register();
add_large_constant(address->base(), address->disp(), tmp);
load_addr = new LIR_Address(tmp, (intx)0, address->type());
} else { // address->disp() can be 0, if the address is referenced using the unsafe intrinsic
load_addr = address;
}
__ volatile_load_mem_reg(load_addr, result, info); return;
}
__ load(address, result, info, lir_patch_none);
}
Messung V0.5 in Prozent
¤ Diese beiden folgenden Angebotsgruppen bietet das Unternehmen0.8Angebot
(Wie Sie bei der Firma Beratungs- und Dienstleistungen beauftragen können 2026-06-10)
¤
Die Informationen auf dieser Webseite wurden
nach bestem Wissen sorgfältig zusammengestellt. Es wird jedoch weder Vollständigkeit, noch Richtigkeit,
noch Qualität der bereit gestellten Informationen zugesichert.
Bemerkung:
Die farbliche Syntaxdarstellung und die Messung sind noch experimentell.