Quelle  lnl-metrics.json   Sprache: unbekannt

[
    {
        "BriefDescription": "C10 residency percent per package",
        "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC",
        "MetricGroup": "Power",
        "MetricName": "C10_Pkg_Residency",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "C1 residency percent per core",
        "MetricExpr": "cstate_core@c1\\-residency@ / TSC",
        "MetricGroup": "Power",
        "MetricName": "C1_Core_Residency",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "C2 residency percent per package",
        "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",
        "MetricGroup": "Power",
        "MetricName": "C2_Pkg_Residency",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "C3 residency percent per package",
        "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",
        "MetricGroup": "Power",
        "MetricName": "C3_Pkg_Residency",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "C6 residency percent per core",
        "MetricExpr": "cstate_core@c6\\-residency@ / TSC",
        "MetricGroup": "Power",
        "MetricName": "C6_Core_Residency",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "C6 residency percent per package",
        "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",
        "MetricGroup": "Power",
        "MetricName": "C6_Pkg_Residency",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "C7 residency percent per core",
        "MetricExpr": "cstate_core@c7\\-residency@ / TSC",
        "MetricGroup": "Power",
        "MetricName": "C7_Core_Residency",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "C7 residency percent per package",
        "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",
        "MetricGroup": "Power",
        "MetricName": "C7_Pkg_Residency",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "C8 residency percent per package",
        "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC",
        "MetricGroup": "Power",
        "MetricName": "C8_Pkg_Residency",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "C9 residency percent per package",
        "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC",
        "MetricGroup": "Power",
        "MetricName": "C9_Pkg_Residency",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "Percentage of cycles spent in System Management Interrupts.",
        "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)",
        "MetricGroup": "smi",
        "MetricName": "smi_cycles",
        "MetricThreshold": "smi_cycles > 0.1",
        "ScaleUnit": "100%"
    },
    {
        "BriefDescription": "Number of SMI interrupts.",
        "MetricExpr": "msr@smi@",
        "MetricGroup": "smi",
        "MetricName": "smi_num",
        "ScaleUnit": "1SMI#"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions",
        "MetricExpr": "tma_core_bound",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group",
        "MetricName": "tma_allocation_restriction",
        "MetricThreshold": "tma_allocation_restriction > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.1)",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls",
        "DefaultMetricgroupName": "TopdownL1",
        "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.ALL_P@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "Default;TopdownL1;tma_L1_group",
        "MetricName": "tma_backend_bound",
        "MetricThreshold": "tma_backend_bound > 0.1",
        "MetricgroupNoGroup": "TopdownL1;Default",
        "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear",
        "DefaultMetricgroupName": "TopdownL1",
        "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.ALL_P@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "Default;TopdownL1;tma_L1_group",
        "MetricName": "tma_bad_speculation",
        "MetricThreshold": "tma_bad_speculation > 0.15",
        "MetricgroupNoGroup": "TopdownL1;Default",
        "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend",
        "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.BRANCH_DETECT@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group",
        "MetricName": "tma_branch_detect",
        "MetricThreshold": "tma_branch_detect > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2)",
        "PublicDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to branch mispredicts",
        "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.MISPREDICT@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group",
        "MetricName": "tma_branch_mispredicts",
        "MetricThreshold": "tma_branch_mispredicts > 0.05 & tma_bad_speculation > 0.15",
        "MetricgroupNoGroup": "TopdownL2",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
        "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.BRANCH_RESTEER@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group",
        "MetricName": "tma_branch_resteer",
        "MetricThreshold": "tma_branch_resteer > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2)",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS).",
        "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.CISC@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group",
        "MetricName": "tma_cisc",
        "MetricThreshold": "tma_cisc > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2)",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles due to backend bound stalls that are bounded by core restrictions and not attributed to an outstanding load or stores, or resource limitation",
        "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group",
        "MetricName": "tma_core_bound",
        "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.1",
        "MetricgroupNoGroup": "TopdownL2",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.",
        "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.DECODE@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group",
        "MetricName": "tma_decode",
        "MetricThreshold": "tma_decode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2)",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear that does not require the use of microcode, classified as a fast nuke, due to memory ordering, memory disambiguation and memory renaming",
        "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.FASTNUKE@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group",
        "MetricName": "tma_fast_nuke",
        "MetricThreshold": "tma_fast_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15)",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.",
        "DefaultMetricgroupName": "TopdownL1",
        "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ALL@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "Default;TopdownL1;tma_L1_group",
        "MetricName": "tma_frontend_bound",
        "MetricThreshold": "tma_frontend_bound > 0.2",
        "MetricgroupNoGroup": "TopdownL1;Default",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses.",
        "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ICACHE@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group",
        "MetricName": "tma_icache_misses",
        "MetricThreshold": "tma_icache_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2)",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.",
        "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group",
        "MetricName": "tma_ifetch_bandwidth",
        "MetricThreshold": "tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2",
        "MetricgroupNoGroup": "TopdownL2",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend latency restrictions due to icache misses, itlb misses, branch detection, and resteer limitations.",
        "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_LATENCY@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group",
        "MetricName": "tma_ifetch_latency",
        "MetricThreshold": "tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2",
        "MetricgroupNoGroup": "TopdownL2",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions per Floating Point (FP) Operation",
        "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@FP_FLOPS_RETIRED.ALL@",
        "MetricGroup": "Flops",
        "MetricName": "tma_info_arith_inst_mix_ipflop",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions per FP Arithmetic instruction",
        "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@FP_INST_RETIRED.ALL@",
        "MetricGroup": "Flops",
        "MetricName": "tma_info_arith_inst_mix_ipfparith",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction",
        "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / (cpu_atom@FP_INST_RETIRED.128B_DP@ + cpu_atom@FP_INST_RETIRED.128B_SP@)",
        "MetricGroup": "Flops",
        "MetricName": "tma_info_arith_inst_mix_ipfparith_avx128",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions per FP Arithmetic AVX 256-bit instruction",
        "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / (cpu_atom@FP_INST_RETIRED.256B_DP@ + cpu_atom@FP_INST_RETIRED.256B_SP@)",
        "MetricGroup": "Flops",
        "MetricName": "tma_info_arith_inst_mix_ipfparith_avx256",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction",
        "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@FP_INST_RETIRED.64B_DP@",
        "MetricGroup": "Flops",
        "MetricName": "tma_info_arith_inst_mix_ipfparith_scalar_dp",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction",
        "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@FP_INST_RETIRED.32B_SP@",
        "MetricGroup": "Flops",
        "MetricName": "tma_info_arith_inst_mix_ipfparith_scalar_sp",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of time that retirement is stalled due to a first level data TLB miss",
        "MetricExpr": "100 * (cpu_atom@LD_HEAD.DTLB_MISS_AT_RET@ + cpu_atom@LD_HEAD.PGWALK_AT_RET@) / cpu_atom@CPU_CLK_UNHALTED.CORE@",
        "MetricName": "tma_info_bottleneck_%_dtlb_miss_bound_cycles",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss",
        "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@ / cpu_atom@CPU_CLK_UNHALTED.CORE@",
        "MetricGroup": "Ifetch",
        "MetricName": "tma_info_bottleneck_%_ifetch_miss_bound_cycles",
        "PublicDescription": "Percentage of time that allocation and retirement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icache or ITLB Miss. See Info.Ifetch_Bound",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of time that retirement is stalled due to an L1 miss",
        "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@ / cpu_atom@CPU_CLK_UNHALTED.CORE@",
        "MetricGroup": "Load_Store_Miss",
        "MetricName": "tma_info_bottleneck_%_load_miss_bound_cycles",
        "PublicDescription": "Percentage of time that retirement is stalled due to an L1 miss. See Info.Load_Miss_Bound",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall",
        "MetricExpr": "100 * cpu_atom@LD_HEAD.ANY_AT_RET@ / cpu_atom@CPU_CLK_UNHALTED.CORE@",
        "MetricGroup": "Mem_Exec",
        "MetricName": "tma_info_bottleneck_%_mem_exec_bound_cycles",
        "PublicDescription": "Percentage of time that retirement is stalled by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
        "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_INST_RETIRED.ALL_BRANCHES@",
        "MetricName": "tma_info_br_inst_mix_ipbranch",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instruction per (near) call (lower number means higher occurrence rate)",
        "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_INST_RETIRED.NEAR_CALL@",
        "MetricName": "tma_info_br_inst_mix_ipcall",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
        "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_INST_RETIRED.FAR_BRANCH@u",
        "MetricName": "tma_info_br_inst_mix_ipfarbranch",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was not taken",
        "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / (cpu_atom@BR_MISP_RETIRED.COND@ - cpu_atom@BR_MISP_RETIRED.COND_TAKEN@)",
        "MetricName": "tma_info_br_inst_mix_ipmisp_cond_ntaken",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions per retired conditional Branch Misprediction where the branch was taken",
        "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_MISP_RETIRED.COND_TAKEN@",
        "MetricName": "tma_info_br_inst_mix_ipmisp_cond_taken",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions per retired indirect call or jump Branch Misprediction",
        "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_MISP_RETIRED.INDIRECT@",
        "MetricName": "tma_info_br_inst_mix_ipmisp_indirect",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions per retired return Branch Misprediction",
        "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_MISP_RETIRED.RETURN@",
        "MetricName": "tma_info_br_inst_mix_ipmisp_ret",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions per retired Branch Misprediction",
        "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@",
        "MetricName": "tma_info_br_inst_mix_ipmispredict",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Ratio of all branches which mispredict",
        "MetricExpr": "cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ / cpu_atom@BR_INST_RETIRED.ALL_BRANCHES@",
        "MetricName": "tma_info_br_mispredict_bound_branch_mispredict_ratio",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Ratio between Mispredicted branches and unknown branches",
        "MetricExpr": "cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ / cpu_atom@BACLEARS.ANY@",
        "MetricName": "tma_info_br_mispredict_bound_branch_mispredict_to_unknown_branch_ratio",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of time that allocation is stalled due to load buffer full",
        "MetricExpr": "100 * cpu_atom@MEM_SCHEDULER_BLOCK.LD_BUF@ / cpu_atom@CPU_CLK_UNHALTED.CORE@",
        "MetricName": "tma_info_buffer_stalls_%_load_buffer_stall_cycles",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of time that allocation is stalled due to memory reservation stations full",
        "MetricExpr": "100 * cpu_atom@MEM_SCHEDULER_BLOCK.RSV@ / cpu_atom@CPU_CLK_UNHALTED.CORE@",
        "MetricName": "tma_info_buffer_stalls_%_mem_rsv_stall_cycles",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of time that allocation is stalled due to store buffer full",
        "MetricExpr": "100 * cpu_atom@MEM_SCHEDULER_BLOCK.ST_BUF@ / cpu_atom@CPU_CLK_UNHALTED.CORE@",
        "MetricName": "tma_info_buffer_stalls_%_store_buffer_stall_cycles",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Cycles Per Instruction",
        "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE@ / cpu_atom@INST_RETIRED.ANY@",
        "MetricName": "tma_info_core_cpi",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Floating Point Operations Per Cycle",
        "MetricExpr": "cpu_atom@FP_FLOPS_RETIRED.ALL@ / cpu_atom@CPU_CLK_UNHALTED.CORE@",
        "MetricGroup": "Flops",
        "MetricName": "tma_info_core_flopc",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions Per Cycle",
        "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@CPU_CLK_UNHALTED.CORE@",
        "MetricName": "tma_info_core_ipc",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Uops Per Instruction",
        "MetricExpr": "cpu_atom@TOPDOWN_RETIRING.ALL@ / cpu_atom@INST_RETIRED.ANY@",
        "MetricName": "tma_info_core_upi",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of ifetch miss bound stalls, where the ifetch miss hits in the L2",
        "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS_IFETCH.L2_HIT@ / cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@",
        "MetricName": "tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l2hit",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of ifetch miss bound stalls, where the ifetch miss doesn't hit in the L2",
        "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS_IFETCH.L2_MISS@ / cpu_atom@MEM_BOUND_STALLS_IFETCH.ALL@",
        "MetricName": "tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l2miss",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 miss that hit the L2",
        "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS_LOAD.L2_HIT@ / cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@",
        "MetricGroup": "load_store_bound",
        "MetricName": "tma_info_load_miss_bound_%_loadmissbound_with_l2hit",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of memory bound stalls where retirement is stalled due to an L1 miss that subsequently misses in the L2",
        "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS_LOAD.L2_MISS@ / cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@",
        "MetricGroup": "load_store_bound",
        "MetricName": "tma_info_load_miss_bound_%_loadmissbound_with_l2miss",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a pipeline block",
        "MetricExpr": "100 * cpu_atom@LD_HEAD.L1_BOUND_AT_RET@ / cpu_atom@CPU_CLK_UNHALTED.CORE@",
        "MetricGroup": "load_store_bound",
        "MetricName": "tma_info_load_store_bound_l1_bound",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement",
        "MetricExpr": "100 * (cpu_atom@LD_HEAD.L1_BOUND_AT_RET@ + cpu_atom@MEM_BOUND_STALLS_LOAD.ALL@) / cpu_atom@CPU_CLK_UNHALTED.CORE@",
        "MetricGroup": "load_store_bound",
        "MetricName": "tma_info_load_store_bound_load_bound",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full",
        "MetricExpr": "100 * (cpu_atom@MEM_SCHEDULER_BLOCK.ST_BUF@ / cpu_atom@MEM_SCHEDULER_BLOCK.ALL@) * tma_mem_scheduler",
        "MetricGroup": "load_store_bound",
        "MetricName": "tma_info_load_store_bound_store_bound",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to memory disambiguation",
        "MetricExpr": "1e3 * cpu_atom@MACHINE_CLEARS.DISAMBIGUATION@ / cpu_atom@INST_RETIRED.ANY@",
        "MetricName": "tma_info_machine_clear_bound_machine_clears_disamb_pki",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to floating point assists",
        "MetricExpr": "1e3 * cpu_atom@MACHINE_CLEARS.FP_ASSIST@ / cpu_atom@INST_RETIRED.ANY@",
        "MetricName": "tma_info_machine_clear_bound_machine_clears_fp_assist_pki",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to memory ordering",
        "MetricExpr": "1e3 * cpu_atom@MACHINE_CLEARS.MEMORY_ORDERING@ / cpu_atom@INST_RETIRED.ANY@",
        "MetricName": "tma_info_machine_clear_bound_machine_clears_monuke_pki",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to memory renaming",
        "MetricExpr": "1e3 * cpu_atom@MACHINE_CLEARS.MRN_NUKE@ / cpu_atom@INST_RETIRED.ANY@",
        "MetricName": "tma_info_machine_clear_bound_machine_clears_mrn_pki",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of machine clears relative to thousands of instructions retired, due to page faults",
        "MetricExpr": "1e3 * cpu_atom@MACHINE_CLEARS.PAGE_FAULT@ / cpu_atom@INST_RETIRED.ANY@",
        "MetricName": "tma_info_machine_clear_bound_machine_clears_page_fault_pki",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of total non-speculative loads with an address aliasing block",
        "MetricExpr": "100 * cpu_atom@LD_BLOCKS.ADDRESS_ALIAS@ / cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@",
        "MetricName": "tma_info_mem_exec_blocks_%_loads_with_adressaliasing",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of total non-speculative loads with a store forward or unknown store address block",
        "MetricExpr": "100 * cpu_atom@LD_BLOCKS.DATA_UNKNOWN@ / cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@",
        "MetricName": "tma_info_mem_exec_blocks_%_loads_with_storefwdblk",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of Memory Execution Bound due to a first level data cache miss",
        "MetricExpr": "100 * cpu_atom@LD_HEAD.L1_MISS_AT_RET@ / cpu_atom@LD_HEAD.ANY_AT_RET@",
        "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_l1miss",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of Memory Execution Bound due to other block cases, such as pipeline conflicts, fences, etc",
        "MetricExpr": "100 * cpu_atom@LD_HEAD.OTHER_AT_RET@ / cpu_atom@LD_HEAD.ANY_AT_RET@",
        "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_otherpipelineblks",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of Memory Execution Bound due to a pagewalk",
        "MetricExpr": "100 * cpu_atom@LD_HEAD.PGWALK_AT_RET@ / cpu_atom@LD_HEAD.ANY_AT_RET@",
        "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_pagewalk",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of Memory Execution Bound due to a second level TLB miss",
        "MetricExpr": "100 * cpu_atom@LD_HEAD.DTLB_MISS_AT_RET@ / cpu_atom@LD_HEAD.ANY_AT_RET@",
        "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_stlbhit",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of Memory Execution Bound due to a store forward address match",
        "MetricExpr": "100 * cpu_atom@LD_HEAD.ST_ADDR_AT_RET@ / cpu_atom@LD_HEAD.ANY_AT_RET@",
        "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_storefwding",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions per Load",
        "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@",
        "MetricName": "tma_info_mem_mix_ipload",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Instructions per Store",
        "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@MEM_UOPS_RETIRED.ALL_STORES@",
        "MetricName": "tma_info_mem_mix_ipstore",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of total non-speculative loads that perform one or more locks",
        "MetricExpr": "100 * cpu_atom@MEM_UOPS_RETIRED.LOCK_LOADS@ / cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@",
        "MetricName": "tma_info_mem_mix_load_locks_ratio",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of total non-speculative loads that are splits",
        "MetricExpr": "100 * cpu_atom@MEM_UOPS_RETIRED.SPLIT_LOADS@ / cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@",
        "MetricName": "tma_info_mem_mix_load_splits_ratio",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Ratio of mem load uops to all uops",
        "MetricExpr": "1e3 * cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@ / cpu_atom@TOPDOWN_RETIRING.ALL@",
        "MetricName": "tma_info_mem_mix_memload_ratio",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of time that the core is stalled due to a TPAUSE or UMWAIT instruction",
        "MetricExpr": "100 * cpu_atom@SERIALIZATION.C01_MS_SCB@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricName": "tma_info_serialization_%_tpause_cycles",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Average CPU Utilization",
        "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.REF_TSC@ / TSC",
        "MetricName": "tma_info_system_cpu_utilization",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Giga Floating Point Operations Per Second",
        "MetricExpr": "cpu_atom@FP_FLOPS_RETIRED.ALL@ / (duration_time * 1e9)",
        "MetricGroup": "Flops",
        "MetricName": "tma_info_system_gflops",
        "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Fraction of cycles spent in Kernel mode",
        "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE_P@k / cpu_atom@CPU_CLK_UNHALTED.CORE@",
        "MetricGroup": "Summary",
        "MetricName": "tma_info_system_kernel_utilization",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "PerfMon Event Multiplexing accuracy indicator",
        "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE_P@ / cpu_atom@CPU_CLK_UNHALTED.CORE@",
        "MetricName": "tma_info_system_mux",
        "MetricThreshold": "tma_info_system_mux > 1.1 | tma_info_system_mux < 0.9",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Average Frequency Utilization relative nominal frequency",
        "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE@ / cpu_atom@CPU_CLK_UNHALTED.REF_TSC@",
        "MetricGroup": "Power",
        "MetricName": "tma_info_system_turbo_utilization",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of all uops which are FPDiv uops",
        "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.FPDIV@ / cpu_atom@TOPDOWN_RETIRING.ALL@",
        "MetricName": "tma_info_uop_mix_fpdiv_uop_ratio",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of all uops which are IDiv uops",
        "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.IDIV@ / cpu_atom@TOPDOWN_RETIRING.ALL@",
        "MetricName": "tma_info_uop_mix_idiv_uop_ratio",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of all uops which are microcode ops",
        "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.MS@ / cpu_atom@TOPDOWN_RETIRING.ALL@",
        "MetricName": "tma_info_uop_mix_microcode_uop_ratio",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Percentage of all uops which are x87 uops",
        "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.X87@ / cpu_atom@TOPDOWN_RETIRING.ALL@",
        "MetricName": "tma_info_uop_mix_x87_uop_ratio",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.",
        "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ITLB_MISS@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group",
        "MetricName": "tma_itlb_misses",
        "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_ifetch_latency > 0.15 & tma_frontend_bound > 0.2)",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation",
        "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group",
        "MetricName": "tma_machine_clears",
        "MetricThreshold": "tma_machine_clears > 0.05 & tma_bad_speculation > 0.15",
        "MetricgroupNoGroup": "TopdownL2",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops",
        "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.MEM_SCHEDULER@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
        "MetricName": "tma_mem_scheduler",
        "MetricThreshold": "tma_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1)",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops",
        "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
        "MetricName": "tma_non_mem_scheduler",
        "MetricThreshold": "tma_non_mem_scheduler > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1)",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear that requires the use of microcode (slow nuke)",
        "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.NUKE@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group",
        "MetricName": "tma_nuke",
        "MetricThreshold": "tma_nuke > 0.05 & (tma_machine_clears > 0.05 & tma_bad_speculation > 0.15)",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized.",
        "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.OTHER@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group",
        "MetricName": "tma_other_fb",
        "MetricThreshold": "tma_other_fb > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2)",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes.",
        "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.PREDECODE@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group",
        "MetricName": "tma_predecode",
        "MetricThreshold": "tma_predecode > 0.05 & (tma_ifetch_bandwidth > 0.1 & tma_frontend_bound > 0.2)",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls)",
        "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.REGISTER@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
        "MetricName": "tma_register",
        "MetricThreshold": "tma_register > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1)",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls)",
        "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.REORDER_BUFFER@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
        "MetricName": "tma_reorder_buffer",
        "MetricThreshold": "tma_reorder_buffer > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1)",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to a resource limitation",
        "MetricExpr": "tma_backend_bound - tma_core_bound",
        "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group",
        "MetricName": "tma_resource_bound",
        "MetricThreshold": "tma_resource_bound > 0.2 & tma_backend_bound > 0.1",
        "MetricgroupNoGroup": "TopdownL2",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that result in retirement slots",
        "DefaultMetricgroupName": "TopdownL1",
        "MetricExpr": "cpu_atom@TOPDOWN_RETIRING.ALL@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "Default;TopdownL1;tma_L1_group",
        "MetricName": "tma_retiring",
        "MetricThreshold": "tma_retiring > 0.75",
        "MetricgroupNoGroup": "TopdownL1;Default",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS)",
        "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.SERIALIZATION@ / (8 * cpu_atom@CPU_CLK_UNHALTED.CORE@)",
        "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group",
        "MetricName": "tma_serialization",
        "MetricThreshold": "tma_serialization > 0.1 & (tma_resource_bound > 0.2 & tma_backend_bound > 0.1)",
        "ScaleUnit": "100%",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "This metric represents Core fraction of cycles CPU dispatched uops on execution ports for ALU operations.",
        "MetricExpr": "cpu_core@UOPS_DISPATCHED.ALU@ / (6 * tma_info_thread_clks)",
        "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group",
        "MetricName": "tma_alu_op_utilization",
        "MetricThreshold": "tma_alu_op_utilization > 0.4",
        "ScaleUnit": "100%",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists",
        "MetricExpr": "78 * cpu_core@ASSISTS.ANY@ / tma_info_thread_slots",
        "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
        "MetricName": "tma_assists",
        "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)",
        "PublicDescription": "This metric estimates fraction of slots the CPU retired uops delivered by the Microcode_Sequencer as a result of Assists. Assists are long sequences of uops that are required in certain corner-cases for operations that cannot be handled natively by the execution pipeline. For example; when working with very small floating point values (so-called Denormals); the FP units are not set up to perform these operations natively. Instead; a sequence of instructions to perform the computation on the Denormals is injected into the pipeline. Since these microcode sequences might be dozens of uops long; Assists can be extremely deleterious to performance and they can be avoided in many cases. Sample with: ASSISTS.ANY",
        "ScaleUnit": "100%",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This metric estimates fraction of slots the CPU retired uops as a result of handing SSE to AVX* or AVX* to SSE transition Assists.",
        "MetricExpr": "63 * cpu_core@ASSISTS.SSE_AVX_MIX@ / tma_info_thread_slots",
        "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group",
        "MetricName": "tma_avx_assists",
        "MetricThreshold": "tma_avx_assists > 0.1",
        "ScaleUnit": "100%",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
        "DefaultMetricgroupName": "TopdownL1",
        "MetricExpr": "cpu_core@topdown\\-be\\-bound@ / (cpu_core@topdown\\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiring@ + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_thread_slots",
        "MetricGroup": "BvOB;Default;TmaL1;TopdownL1;tma_L1_group",
        "MetricName": "tma_backend_bound",
        "MetricThreshold": "tma_backend_bound > 0.2",
        "MetricgroupNoGroup": "TopdownL1;Default",
        "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS",
        "ScaleUnit": "100%",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
        "DefaultMetricgroupName": "TopdownL1",
        "MetricExpr": "cpu_core@topdown\\-bad\\-spec@ / (cpu_core@topdown\\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiring@ + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_thread_slots",
        "MetricGroup": "Default;TmaL1;TopdownL1;tma_L1_group",
        "MetricName": "tma_bad_speculation",
        "MetricThreshold": "tma_bad_speculation > 0.15",
        "MetricgroupNoGroup": "TopdownL1;Default",
        "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example.",
        "ScaleUnit": "100%",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Total pipeline cost of instruction fetch related bottlenecks by large code footprint programs (i-side cache; TLB and BTB misses)",
        "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_icache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)",
        "MetricGroup": "BigFootprint;BvBC;Fed;Frontend;IcMiss;MemoryTLB",
        "MetricName": "tma_bottleneck_big_code",
        "MetricThreshold": "tma_bottleneck_big_code > 20",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA",
        "MetricExpr": "100 * ((cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ + 2 * cpu_core@BR_INST_RETIRED.NEAR_CALL@ + cpu_core@INST_RETIRED.NOP@) / tma_info_thread_slots)",
        "MetricGroup": "BvBO;Ret",
        "MetricName": "tma_bottleneck_branching_overhead",
        "MetricThreshold": "tma_bottleneck_branching_overhead > 5",
        "PublicDescription": "Total pipeline cost of instructions used for program control-flow - a subset of the Retiring category in TMA. Examples include function calls; loops and alignments. (A lower bound)",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks",
        "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_l1_latency_capacity + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))",
        "MetricGroup": "BvMB;Mem;MemoryBW;Offcore;tma_issueBW",
        "MetricName": "tma_bottleneck_cache_memory_bandwidth",
        "MetricThreshold": "tma_bottleneck_cache_memory_bandwidth > 20",
        "PublicDescription": "Total pipeline cost of external Memory- or Cache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks",
        "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l1_latency_dependency / (tma_dtlb_load + tma_fb_full + tma_l1_latency_capacity + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l1_latency_capacity / (tma_dtlb_load + tma_fb_full + tma_l1_latency_capacity + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_lock_latency / (tma_dtlb_load + tma_fb_full + tma_l1_latency_capacity + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_split_loads / (tma_dtlb_load + tma_fb_full + tma_l1_latency_capacity + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_split_stores / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))",
        "MetricGroup": "BvML;Mem;MemoryLat;Offcore;tma_issueLat",
        "MetricName": "tma_bottleneck_cache_memory_latency",
        "MetricThreshold": "tma_bottleneck_cache_memory_latency > 20",
        "PublicDescription": "Total pipeline cost of external Memory- or Cache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_mem_latency",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Total pipeline cost when the execution is compute-bound - an estimation",
        "MetricExpr": "100 * (tma_core_bound * tma_divider / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * (tma_ports_utilization / (tma_divider + tma_ports_utilization + tma_serializing_operation)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m)))",
        "MetricGroup": "BvCB;Cor;tma_issueComp",
        "MetricName": "tma_bottleneck_compute_bound_est",
        "MetricThreshold": "tma_bottleneck_compute_bound_est > 20",
        "PublicDescription": "Total pipeline cost when the execution is compute-bound - an estimation. Covers Core Bound when High ILP as well as when long-latency execution units are busy. Related metrics: ",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Total pipeline cost of instruction fetch bandwidth related bottlenecks (when the front-end could not sustain operations delivery to the back-end)",
        "MetricExpr": "100 * (tma_frontend_bound - (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - (1 - cpu_core@INST_RETIRED.REP_ITERATION@ / cpu_core@UOPS_RETIRED.MS\\,cmask\\=1@) * (tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_ms / (tma_dsb + tma_lsd + tma_mite + tma_ms))) - tma_bottleneck_big_code",
        "MetricGroup": "BvFB;Fed;FetchBW;Frontend",
        "MetricName": "tma_bottleneck_instruction_fetch_bw",
        "MetricThreshold": "tma_bottleneck_instruction_fetch_bw > 20",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Total pipeline cost of irregular execution (e.g",
        "MetricExpr": "100 * ((1 - cpu_core@INST_RETIRED.REP_ITERATION@ / cpu_core@UOPS_RETIRED.MS\\,cmask\\=1@) * (tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_ms / (tma_dsb + tma_lsd + tma_mite + tma_ms)) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes / tma_other_nukes + tma_core_bound * (tma_serializing_operation + cpu_core@RS.EMPTY_RESOURCE@ / tma_info_thread_clks * tma_ports_utilized_0) / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_microcode_sequencer / (tma_microcode_sequencer + tma_few_uops_instructions) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)",
        "MetricGroup": "Bad;BvIO;Cor;Ret;tma_issueMS",
        "MetricName": "tma_bottleneck_irregular_overhead",
        "MetricThreshold": "tma_bottleneck_irregular_overhead > 10",
        "PublicDescription": "Total pipeline cost of irregular execution (e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloads, overhead in system services or virtualized environments). Related metrics: tma_microcode_sequencer, tma_ms_switches",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs)",
        "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_load / (tma_dtlb_load + tma_fb_full + tma_l1_latency_capacity + tma_l1_latency_dependency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores)))",
        "MetricGroup": "BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB",
        "MetricName": "tma_bottleneck_memory_data_tlbs",
        "MetricThreshold": "tma_bottleneck_memory_data_tlbs > 20",
        "PublicDescription": "Total pipeline cost of Memory Address Translation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load, tma_dtlb_store",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors)",
        "MetricExpr": "100 * (tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_other_nukes))",
        "MetricGroup": "BvMS;LockCont;Mem;Offcore;tma_issueSyncxn",
        "MetricName": "tma_bottleneck_memory_synchronization",
        "MetricThreshold": "tma_bottleneck_memory_synchronization > 10",
        "PublicDescription": "Total pipeline cost of Memory Synchronization related bottlenecks (data transfers and coherency updates across processors). Related metrics: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote_cache",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Total pipeline cost of Branch Misprediction related bottlenecks",
        "MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetch_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))",
        "MetricGroup": "Bad;BadSpec;BrMispredicts;BvMP;tma_issueBM",
        "MetricName": "tma_bottleneck_mispredictions",
        "MetricThreshold": "tma_bottleneck_mispredictions > 20",
        "PublicDescription": "Total pipeline cost of Branch Misprediction related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Total pipeline cost of remaining bottlenecks in the back-end",
        "MetricExpr": "100 - (tma_bottleneck_big_code + tma_bottleneck_instruction_fetch_bw + tma_bottleneck_mispredictions + tma_bottleneck_cache_memory_bandwidth + tma_bottleneck_cache_memory_latency + tma_bottleneck_memory_data_tlbs + tma_bottleneck_memory_synchronization + tma_bottleneck_compute_bound_est + tma_bottleneck_irregular_overhead + tma_bottleneck_branching_overhead + tma_bottleneck_useful_work)",
        "MetricGroup": "BvOB;Cor;Offcore",
        "MetricName": "tma_bottleneck_other_bottlenecks",
        "MetricThreshold": "tma_bottleneck_other_bottlenecks > 20",
        "PublicDescription": "Total pipeline cost of remaining bottlenecks in the back-end. Examples include data-dependencies (Core Bound when Low ILP) and other unlisted memory-related stalls.",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Total pipeline cost of \"useful operations\" - the portion of Retiring category not covered by Branching_Overhead nor Irregular_Overhead.",
        "MetricExpr": "100 * (tma_retiring - (cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ + 2 * cpu_core@BR_INST_RETIRED.NEAR_CALL@ + cpu_core@INST_RETIRED.NOP@) / tma_info_thread_slots - tma_microcode_sequencer / (tma_microcode_sequencer + tma_few_uops_instructions) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)",
        "MetricGroup": "BvUW;Ret",
        "MetricName": "tma_bottleneck_useful_work",
        "MetricThreshold": "tma_bottleneck_useful_work > 20",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction",
        "MetricExpr": "cpu_core@topdown\\-br\\-mispredict@ / (cpu_core@topdown\\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiring@ + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_thread_slots",
        "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_group;tma_bad_speculation_group;tma_issueBM",
        "MetricName": "tma_branch_mispredicts",
        "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_speculation > 0.15",
        "MetricgroupNoGroup": "TopdownL2",
        "PublicDescription": "This metric represents fraction of slots the CPU has wasted due to Branch Misprediction.  These slots are either wasted by uops fetched from an incorrectly speculated program path; or stalls when the out-of-order part of the machine needs to recover its state from a speculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: tma_bottleneck_mispredictions, tma_info_bad_spec_branch_misprediction_cost, tma_mispredicts_resteers",
        "ScaleUnit": "100%",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers",
        "MetricExpr": "cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_thread_clks + tma_unknown_branches",
        "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_group",
        "MetricName": "tma_branch_resteers",
        "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15)",
        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers. Branch Resteers estimates the Frontend delay in fetching operations from corrected path; following all sorts of miss-predicted branches. For example; branchy code with lots of miss-predictions might get categorized under Branch Resteers. Note the value of this node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRANCHES",
        "ScaleUnit": "100%",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.1 power-performance optimized state (Faster wakeup time; Smaller power savings).",
        "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.C01@ / tma_info_thread_clks",
        "MetricGroup": "C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group",
        "MetricName": "tma_c01_wait",
        "MetricThreshold": "tma_c01_wait > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))",
        "ScaleUnit": "100%",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due staying in C0.2 power-performance optimized state (Slower wakeup time; Larger power savings).",
        "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.C02@ / tma_info_thread_clks",
        "MetricGroup": "C0Wait;TopdownL4;tma_L4_group;tma_serializing_operation_group",
        "MetricName": "tma_c02_wait",
        "MetricThreshold": "tma_c02_wait > 0.05 & (tma_serializing_operation > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))",
        "ScaleUnit": "100%",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction",
        "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)",
        "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_group",
        "MetricName": "tma_cisc",
        "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.05 & tma_heavy_operations > 0.1)",
        "PublicDescription": "This metric estimates fraction of cycles the CPU retired uops originated from CISC (complex instruction set computer) instruction. A CISC instruction has multiple uops that are required to perform the instruction's functionality as in the case of read-modify-write as an example. Since these instructions require multiple uops they may or may not imply sub-optimal use of machine resources.",
        "ScaleUnit": "100%",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears",
        "MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) * cpu_core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_thread_clks",
        "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_branch_resteers_group;tma_issueMC",
        "MetricName": "tma_clears_resteers",
        "MetricThreshold": "tma_clears_resteers > 0.05 & (tma_branch_resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))",
        "PublicDescription": "This metric represents fraction of cycles the CPU was stalled due to Branch Resteers as a result of Machine Clears. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma_machine_clears, tma_microcode_sequencer, tma_ms_switches",
        "ScaleUnit": "100%",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This metric estimates fraction of cycles the CPU was stalled due to instruction cache misses that hit in the L2 cache.",
        "MetricExpr": "max(0, cpu_core@FRONTEND_RETIRED.L1I_MISS@ * cpu_core@FRONTEND_RETIRED.L1I_MISS@R / tma_info_thread_clks - tma_code_l2_miss)",
        "MetricGroup": "FetchLat;IcMiss;Offcore;TopdownL4;tma_L4_group;tma_icache_misses_group",
        "MetricName": "tma_code_l2_hit",
        "MetricThreshold": "tma_code_l2_hit > 0.05 & (tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))",
        "ScaleUnit": "100%",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This metric estimates fraction of cycles the CPU was stalled due to instruction cache misses that miss in the L2 cache.",
        "MetricExpr": "cpu_core@FRONTEND_RETIRED.L2_MISS@ * cpu_core@FRONTEND_RETIRED.L2_MISS@R / tma_info_thread_clks",
        "MetricGroup": "FetchLat;IcMiss;Offcore;TopdownL4;tma_L4_group;tma_icache_misses_group",
        "MetricName": "tma_code_l2_miss",
        "MetricThreshold": "tma_code_l2_miss > 0.05 & (tma_icache_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))",
        "ScaleUnit": "100%",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This metric roughly estimates the fraction of cycles where the (first level) ITLB was missed by instructions fetches, that later on hit in second-level TLB (STLB)",
        "MetricExpr": "max(0, cpu_core@FRONTEND_RETIRED.ITLB_MISS@ * cpu_core@FRONTEND_RETIRED.ITLB_MISS@R / tma_info_thread_clks - tma_code_stlb_miss)",
        "MetricGroup": "FetchLat;MemoryTLB;TopdownL4;tma_L4_group;tma_itlb_misses_group",
        "MetricName": "tma_code_stlb_hit",
        "MetricThreshold": "tma_code_stlb_hit > 0.05 & (tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))",
        "ScaleUnit": "100%",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This metric estimates the fraction of cycles where the Second-level TLB (STLB) was missed by instruction fetches, performing a hardware page walk",
        "MetricExpr": "cpu_core@FRONTEND_RETIRED.STLB_MISS@ * cpu_core@FRONTEND_RETIRED.STLB_MISS@R / tma_info_thread_clks",
        "MetricGroup": "FetchLat;MemoryTLB;TopdownL4;tma_L4_group;tma_itlb_misses_group",
        "MetricName": "tma_code_stlb_miss",
        "MetricThreshold": "tma_code_stlb_miss > 0.05 & (tma_itlb_misses > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))",
        "ScaleUnit": "100%",
        "Unit": "cpu_core"
    },
    {
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