/* get regmaps */
pllctrl_regs = syscon_regmap_lookup_by_phandle_args(np, "ti,syscon-pll", 1, &rspll_offset); if (IS_ERR(pllctrl_regs)) return PTR_ERR(pllctrl_regs);
devctrl_regs = syscon_regmap_lookup_by_phandle_args(np, "ti,syscon-dev", 1, &rsmux_offset); if (IS_ERR(devctrl_regs)) return PTR_ERR(devctrl_regs);
/* set soft/hard reset */
val = of_property_read_bool(np, "ti,soft-reset");
val = val ? RSCFG_RSTYPE_SOFT : RSCFG_RSTYPE_HARD;
ret = rsctrl_enable_rspll_write(); if (ret) return ret;
ret = regmap_write(pllctrl_regs, rspll_offset + RSCFG_RG, val); if (ret) return ret;
/* disable a reset isolation for all module clocks */
ret = regmap_write(pllctrl_regs, rspll_offset + RSISO_RG, 0); if (ret) return ret;
/* enable a reset for watchdogs from wdt-list */ for (i = 0; i < WDT_MUX_NUMBER; i++) {
ret = of_property_read_u32_index(np, "ti,wdt-list", i, &val); if (ret == -EOVERFLOW && !i) {
dev_err(dev, "ti,wdt-list property has to contain at" "least one entry\n"); return -EINVAL;
} elseif (ret) { break;
}
if (val >= WDT_MUX_NUMBER) {
dev_err(dev, "ti,wdt-list property can contain " "only numbers < 4\n"); return -EINVAL;
}
rg = rsmux_offset + val * 4;
ret = regmap_update_bits(devctrl_regs, rg, RSMUX_OMODE_MASK,
RSMUX_OMODE_RESET_ON |
RSMUX_LOCK_SET); if (ret) return ret;
}
ret = register_restart_handler(&rsctrl_restart_nb); if (ret)
dev_err(dev, "cannot register restart handler (err=%d)\n", ret);
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