/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
*/
#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_H_
#define QCOM_PHY_QMP_PCS_PCIE_V4_H_
/* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */
#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_STATUS 0 x00
#define QPHY_V4_PCS_PCIE_OSC_DTCT_STATUS 0 x04
#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG1 0 x08
#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0 x0c
#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG3 0 x10
#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0 x14
#define QPHY_V4_PCS_PCIE_PCS_TX_RX_CONFIG 0 x18
#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0 x1c
#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0 x20
#define QPHY_V4_PCS_PCIE_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0 x24
#define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_L 0 x28
#define QPHY_V4_PCS_PCIE_EPCLK_DLY_COUNT_VAL_H 0 x2c
#define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL1 0 x30
#define QPHY_V4_PCS_PCIE_RX_IDLE_DTCT_CNTRL2 0 x34
#define QPHY_V4_PCS_PCIE_SIGDET_CNTRL 0 x38
#define QPHY_V4_PCS_PCIE_SIGDET_LOW_2_IDLE_TIME 0 x3c
#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0 x40
#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0 x44
#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0 x48
#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0 x4c
#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0 x50
#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG2 0 x54
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG1 0 x58
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2 0 x5c
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG3 0 x60
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG4 0 x64
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG5 0 x68
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG6 0 x6c
#define QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG7 0 x70
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG1 0 x74
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0 x78
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG3 0 x7c
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0 x80
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0 x84
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6 0 x88
#define QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG7 0 x8c
#define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0 x90
#define QPHY_V4_PCS_PCIE_LOCAL_FS 0 x94
#define QPHY_V4_PCS_PCIE_LOCAL_LF 0 x98
#define QPHY_V4_PCS_PCIE_LOCAL_FS_RS 0 x9c
#define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0 xa0
#define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0 xa4
#define QPHY_V4_PCS_PCIE_PRESET_P0_P1_PRE 0 xa8
#define QPHY_V4_PCS_PCIE_PRESET_P2_P3_PRE 0 xac
#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE 0 xb0
#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0 xb4
#define QPHY_V4_PCS_PCIE_PRESET_P8_P9_PRE 0 xb8
#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0 xbc
#define QPHY_V4_PCS_PCIE_PRESET_P1_P3_PRE_RS 0 xc0
#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_PRE_RS 0 xc4
#define QPHY_V4_PCS_PCIE_PRESET_P6_P9_PRE_RS 0 xc8
#define QPHY_V4_PCS_PCIE_PRESET_P0_P1_POST 0 xcc
#define QPHY_V4_PCS_PCIE_PRESET_P2_P3_POST 0 xd0
#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST 0 xd4
#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_POST 0 xd8
#define QPHY_V4_PCS_PCIE_PRESET_P8_P9_POST 0 xdc
#define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0 xe0
#define QPHY_V4_PCS_PCIE_PRESET_P1_P3_POST_RS 0 xe4
#define QPHY_V4_PCS_PCIE_PRESET_P4_P5_POST_RS 0 xe8
#define QPHY_V4_PCS_PCIE_PRESET_P6_P9_POST_RS 0 xec
#define QPHY_V4_PCS_PCIE_RXEQEVAL_TIME 0 xf0
#endif
Messung V0.5 in Prozent C=96 H=95 G=95
¤ Dauer der Verarbeitung: 0.12 Sekunden
(vorverarbeitet am 2026-06-07)
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