/** *phy_speed_to_str-ReturnastringrepresentingthePHYlinkspeed * *@speed:Speedofthelink
*/ constchar *phy_speed_to_str(int speed)
{
BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 121, "Enum ethtool_link_mode_bit_indices and phylib are out of sync. " "If a speed or mode has been added please update phy_speed_to_str " "and the PHY settings array.\n");
switch (speed) { case SPEED_10: return"10Mbps"; case SPEED_100: return"100Mbps"; case SPEED_1000: return"1Gbps"; case SPEED_2500: return"2.5Gbps"; case SPEED_5000: return"5Gbps"; case SPEED_10000: return"10Gbps"; case SPEED_14000: return"14Gbps"; case SPEED_20000: return"20Gbps"; case SPEED_25000: return"25Gbps"; case SPEED_40000: return"40Gbps"; case SPEED_50000: return"50Gbps"; case SPEED_56000: return"56Gbps"; case SPEED_100000: return"100Gbps"; case SPEED_200000: return"200Gbps"; case SPEED_400000: return"400Gbps"; case SPEED_800000: return"800Gbps"; case SPEED_UNKNOWN: return"Unknown"; default: return"Unsupported (update phy-core.c)";
}
}
EXPORT_SYMBOL_GPL(phy_speed_to_str);
/** *phy_duplex_to_str-Returnstringdescribingtheduplex * *@duplex:Duplexsettingtodescribe
*/ constchar *phy_duplex_to_str(unsignedint duplex)
{ if (duplex == DUPLEX_HALF) return"Half"; if (duplex == DUPLEX_FULL) return"Full"; if (duplex == DUPLEX_UNKNOWN) return"Unknown"; return"Unsupported (update phy-core.c)";
}
EXPORT_SYMBOL_GPL(phy_duplex_to_str);
/** *phy_rate_matching_to_str-Returnastringdescribingtheratematching * *@rate_matching:Typeofratematchingtodescribe
*/ constchar *phy_rate_matching_to_str(int rate_matching)
{ switch (rate_matching) { case RATE_MATCH_NONE: return"none"; case RATE_MATCH_PAUSE: return"pause"; case RATE_MATCH_CRS: return"crs"; case RATE_MATCH_OPEN_LOOP: return"open-loop";
} return"Unsupported (update phy-core.c)";
}
EXPORT_SYMBOL_GPL(phy_rate_matching_to_str);
/** *phy_interface_num_ports-Returnthenumberoflinksthatcanbecarriedby *agivenMAC-PHYphysicallink.Returns0ifthisis *unknown,thenumberoflinkselse. * *@interface:Theinterfacemodewewanttogetthenumberofports
*/ int phy_interface_num_ports(phy_interface_t interface)
{ switch (interface) { case PHY_INTERFACE_MODE_NA: return0; case PHY_INTERFACE_MODE_INTERNAL: case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_MIILITE: case PHY_INTERFACE_MODE_GMII: case PHY_INTERFACE_MODE_TBI: case PHY_INTERFACE_MODE_REVMII: case PHY_INTERFACE_MODE_RMII: case PHY_INTERFACE_MODE_REVRMII: case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_TXID: case PHY_INTERFACE_MODE_RTBI: case PHY_INTERFACE_MODE_XGMII: case PHY_INTERFACE_MODE_XLGMII: case PHY_INTERFACE_MODE_MOCA: case PHY_INTERFACE_MODE_TRGMII: case PHY_INTERFACE_MODE_USXGMII: case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_SMII: case PHY_INTERFACE_MODE_1000BASEX: case PHY_INTERFACE_MODE_2500BASEX: case PHY_INTERFACE_MODE_5GBASER: case PHY_INTERFACE_MODE_10GBASER: case PHY_INTERFACE_MODE_25GBASER: case PHY_INTERFACE_MODE_10GKR: case PHY_INTERFACE_MODE_100BASEX: case PHY_INTERFACE_MODE_RXAUI: case PHY_INTERFACE_MODE_XAUI: case PHY_INTERFACE_MODE_1000BASEKX: case PHY_INTERFACE_MODE_50GBASER: case PHY_INTERFACE_MODE_LAUI: case PHY_INTERFACE_MODE_100GBASEP: return1; case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_QUSGMII: case PHY_INTERFACE_MODE_10G_QXGMII: return4; case PHY_INTERFACE_MODE_PSGMII: return5; case PHY_INTERFACE_MODE_MAX:
WARN_ONCE(1, "PHY_INTERFACE_MODE_MAX isn't a valid interface mode"); return0;
} return0;
}
EXPORT_SYMBOL_GPL(phy_interface_num_ports);
c = phy_caps_lookup_by_linkmode(common); if (c)
speed = c->speed;
if (speed == SPEED_UNKNOWN || phydev->speed >= speed) return;
phydev_warn(phydev, "Downshift occurred from negotiated speed %s to actual speed %s, check cabling!\n",
phy_speed_to_str(speed), phy_speed_to_str(phydev->speed));
/* Select the Function : DATA with no post increment */
__mdiobus_write(bus, phy_addr, MII_MMD_CTRL,
devad | MII_MMD_CTRL_NOINCR);
}
int mmd_phy_read(struct mii_bus *bus, int phy_addr, bool is_c45, int devad, u32 regnum)
{ if (is_c45) return __mdiobus_c45_read(bus, phy_addr, devad, regnum);
mmd_phy_indirect(bus, phy_addr, devad, regnum); /* Read the content of the MMD's selected register */ return __mdiobus_read(bus, phy_addr, MII_MMD_DATA);
}
EXPORT_SYMBOL_GPL(mmd_phy_read);
int mmd_phy_write(struct mii_bus *bus, int phy_addr, bool is_c45, int devad, u32 regnum, u16 val)
{ if (is_c45) return __mdiobus_c45_write(bus, phy_addr, devad, regnum, val);
mmd_phy_indirect(bus, phy_addr, devad, regnum); /* Write the data into MMD's selected register */ return __mdiobus_write(bus, phy_addr, MII_MMD_DATA, val);
}
EXPORT_SYMBOL_GPL(mmd_phy_write);
/** *__phy_read_mmd-Conveniencefunctionforreadingaregister *fromanMMDonagivenPHY. *@phydev:Thephy_devicestruct *@devad:TheMMDtoreadfrom(0..31) *@regnum:TheregisterontheMMDtoread(0..65535) * *Samerulesasfor__phy_read();
*/ int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum)
{ if (regnum > (u16)~0 || devad > 32) return -EINVAL;
if (phydev->drv && phydev->drv->read_mmd) return phydev->drv->read_mmd(phydev, devad, regnum);
/** *__phy_modify_mmd-ConveniencefunctionformodifyingaregisteronMMD *@phydev:thephy_devicestruct *@devad:theMMDcontainingregistertomodify *@regnum:registernumbertomodify *@mask:bitmaskofbitstoclear *@set:newvalueofbitssetinmasktowriteto@regnum * *NOTE:MUSTNOTbecalledfrominterruptcontext, *becausethebusread/writefunctionsmaywaitforaninterrupt *toconcludetheoperation.
*/ int __phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
u16 mask, u16 set)
{ int ret;
ret = __phy_modify_mmd_changed(phydev, devad, regnum, mask, set);
return ret < 0 ? ret : 0;
}
EXPORT_SYMBOL_GPL(__phy_modify_mmd);
/** *phy_modify_mmd-ConveniencefunctionformodifyingaregisteronMMD *@phydev:thephy_devicestruct *@devad:theMMDcontainingregistertomodify *@regnum:registernumbertomodify *@mask:bitmaskofbitstoclear *@set:newvalueofbitssetinmasktowriteto@regnum * *NOTE:MUSTNOTbecalledfrominterruptcontext, *becausethebusread/writefunctionsmaywaitforaninterrupt *toconcludetheoperation.
*/ int phy_modify_mmd(struct phy_device *phydev, int devad, u32 regnum,
u16 mask, u16 set)
{ int ret;
phy_lock_mdio_bus(phydev);
ret = __phy_modify_mmd(phydev, devad, regnum, mask, set);
phy_unlock_mdio_bus(phydev);
return ret;
}
EXPORT_SYMBOL_GPL(phy_modify_mmd);
staticint __phy_read_page(struct phy_device *phydev)
{ if (WARN_ONCE(!phydev->drv->read_page, "read_page callback not available, PHY driver not loaded?\n")) return -EOPNOTSUPP;
return phydev->drv->read_page(phydev);
}
staticint __phy_write_page(struct phy_device *phydev, int page)
{ if (WARN_ONCE(!phydev->drv->write_page, "write_page callback not available, PHY driver not loaded?\n")) return -EOPNOTSUPP;
/** *phy_restore_page()-restorethepageregisterandreleasethebuslock *@phydev:apointertoa&structphy_device *@oldpage:theoldpage,returnvaluefromphy_save_page()orphy_select_page() *@ret:operation'sreturncode * *ReleasetheMDIObuslock,restoring@oldpageifitisavalidpage. *Thisfunctionpropagatestheearliesterrorcodefromthegroupof *operations. * *Returns: *@oldpageifitwasanegativevalue,otherwise *@retifitwasanegativeerrnovalue,otherwise *phy_write_page()'snegativevalueifitwereinerror,otherwise *@ret.
*/ int phy_restore_page(struct phy_device *phydev, int oldpage, int ret)
{ int r;
if (oldpage >= 0) {
r = __phy_write_page(phydev, oldpage);
/* Propagate the operation return code if the page write *wassuccessful.
*/ if (ret >= 0 && r < 0)
ret = r;
} else { /* Propagate the phy page selection error code */
ret = oldpage;
}
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