struct gsi_ring { void *virt; /* ring array base address */
dma_addr_t addr; /* primarily low 32 bits used */
u32 count; /* number of elements in ring */
/* The ring index value indicates the next "open" entry in the ring. * *AchannelringconsistsofTREentriesfilledbytheAPandpassed *tothehardwareforprocessing.Forachannelring,theringindex *identifiesthenextunusedentrytobefilledbytheAP.Inthis *casetheinitialvalueisassumedbyhardwaretobe0. * *Aneventringconsistsofeventstructuresfilledbythehardware *andpassedtotheAP.Foreventrings,theringindexidentifies *thenextringentrythatisnotknowntohavebeenfilledbythe *hardware.Theinitialvalueusedisarbitrary(soweuse0).
*/
u32 index;
};
/* Transactions use several resources that can be allocated dynamically *buttakenfromafixed-sizepool.Thenumberofelementsrequiredfor *thepoolislimitedbythetotalnumberofTREsthatcanbeoutstanding. * *IfsufficientTREsareavailabletoreserveforatransaction, *allocationfromthesepoolsisguaranteedtosucceed.Furthermore, *theseresourcesareimplicitlyfreedwhenevertheTREsinthe *transactionthey'reassociatedwitharereleased. * *Theresultofapoolallocationofmultipleelementsisalways *contiguous.
*/ struct gsi_trans_pool { void *base; /* base address of element pool */
u32 count; /* # elements in the pool */
u32 free; /* next free element in pool (modulo) */
u32 size; /* size (bytes) of an element */
u32 max_alloc; /* max allocation request */
dma_addr_t addr; /* DMA address if DMA pool (or 0) */
};
struct gsi_trans_info {
atomic_t tre_avail; /* TREs available for allocation */
u16 free_id; /* first free trans in array */
u16 allocated_id; /* first allocated transaction */
u16 committed_id; /* first committed transaction */
u16 pending_id; /* first pending transaction */
u16 completed_id; /* first completed transaction */
u16 polled_id; /* first polled transaction */ struct gsi_trans *trans; /* transaction array */ struct gsi_trans **map; /* TRE -> transaction map */
struct gsi_trans_pool sg_pool; /* scatterlist pool */ struct gsi_trans_pool cmd_pool; /* command payload DMA pool */
};
/* Hardware values signifying the state of a channel */ enum gsi_channel_state {
GSI_CHANNEL_STATE_NOT_ALLOCATED = 0x0,
GSI_CHANNEL_STATE_ALLOCATED = 0x1,
GSI_CHANNEL_STATE_STARTED = 0x2,
GSI_CHANNEL_STATE_STOPPED = 0x3,
GSI_CHANNEL_STATE_STOP_IN_PROC = 0x4,
GSI_CHANNEL_STATE_FLOW_CONTROLLED = 0x5, /* IPA v4.2-v4.9 */
GSI_CHANNEL_STATE_ERROR = 0xf,
};
/* We only care about channels between IPA and AP */ struct gsi_channel { struct gsi *gsi; bool toward_ipa; bool command; /* AP command TX channel or not */
u8 trans_tre_max; /* max TREs in a transaction */
u16 tre_count;
u16 event_count;
struct gsi_ring tre_ring;
u32 evt_ring_id;
/* The following counts are used only for TX endpoints */
u64 byte_count; /* total # bytes transferred */
u64 trans_count; /* total # transactions */
u64 queued_byte_count; /* last reported queued byte count */
u64 queued_trans_count; /* ...and queued trans count */
u64 compl_byte_count; /* last reported completed byte count */
u64 compl_trans_count; /* ...and completed trans count */
struct gsi_trans_info trans_info;
struct napi_struct napi;
};
/* Hardware values signifying the state of an event ring */ enum gsi_evt_ring_state {
GSI_EVT_RING_STATE_NOT_ALLOCATED = 0x0,
GSI_EVT_RING_STATE_ALLOCATED = 0x1,
GSI_EVT_RING_STATE_ERROR = 0xf,
};
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