/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright(c) 1999 - 2018 Intel Corporation. */
#ifndef _IXGBEVF_REGS_H_
#define _IXGBEVF_REGS_H_
#define IXGBE_VFCTRL 0 x00000
#define IXGBE_VFSTATUS 0 x00008
#define IXGBE_VFLINKS 0 x00010
#define IXGBE_VFFRTIMER 0 x00048
#define IXGBE_VFRXMEMWRAP 0 x03190
#define IXGBE_VTEICR 0 x00100
#define IXGBE_VTEICS 0 x00104
#define IXGBE_VTEIMS 0 x00108
#define IXGBE_VTEIMC 0 x0010C
#define IXGBE_VTEIAC 0 x00110
#define IXGBE_VTEIAM 0 x00114
#define IXGBE_VTEITR(x) (0 x00820 + (4 * (x)))
#define IXGBE_VTIVAR(x) (0 x00120 + (4 * (x)))
#define IXGBE_VTIVAR_MISC 0 x00140
#define IXGBE_VTRSCINT(x) (0 x00180 + (4 * (x)))
#define IXGBE_VFRDBAL(x) (0 x01000 + (0 x40 * (x)))
#define IXGBE_VFRDBAH(x) (0 x01004 + (0 x40 * (x)))
#define IXGBE_VFRDLEN(x) (0 x01008 + (0 x40 * (x)))
#define IXGBE_VFRDH(x) (0 x01010 + (0 x40 * (x)))
#define IXGBE_VFRDT(x) (0 x01018 + (0 x40 * (x)))
#define IXGBE_VFRXDCTL(x) (0 x01028 + (0 x40 * (x)))
#define IXGBE_VFSRRCTL(x) (0 x01014 + (0 x40 * (x)))
#define IXGBE_VFRSCCTL(x) (0 x0102C + (0 x40 * (x)))
#define IXGBE_VFPSRTYPE 0 x00300
#define IXGBE_VFTDBAL(x) (0 x02000 + (0 x40 * (x)))
#define IXGBE_VFTDBAH(x) (0 x02004 + (0 x40 * (x)))
#define IXGBE_VFTDLEN(x) (0 x02008 + (0 x40 * (x)))
#define IXGBE_VFTDH(x) (0 x02010 + (0 x40 * (x)))
#define IXGBE_VFTDT(x) (0 x02018 + (0 x40 * (x)))
#define IXGBE_VFTXDCTL(x) (0 x02028 + (0 x40 * (x)))
#define IXGBE_VFTDWBAL(x) (0 x02038 + (0 x40 * (x)))
#define IXGBE_VFTDWBAH(x) (0 x0203C + (0 x40 * (x)))
#define IXGBE_VFDCA_RXCTRL(x) (0 x0100C + (0 x40 * (x)))
#define IXGBE_VFDCA_TXCTRL(x) (0 x0200c + (0 x40 * (x)))
#define IXGBE_VFGPRC 0 x0101C
#define IXGBE_VFGPTC 0 x0201C
#define IXGBE_VFGORC_LSB 0 x01020
#define IXGBE_VFGORC_MSB 0 x01024
#define IXGBE_VFGOTC_LSB 0 x02020
#define IXGBE_VFGOTC_MSB 0 x02024
#define IXGBE_VFMPRC 0 x01034
#define IXGBE_VFMRQC 0 x3000
#define IXGBE_VFRSSRK(x) (0 x3100 + ((x) * 4 ))
#define IXGBE_VFRETA(x) (0 x3200 + ((x) * 4 ))
/* VFMRQC bits */
#define IXGBE_VFMRQC_RSSEN 0 x00000001 /* RSS Enable */
#define IXGBE_VFMRQC_RSS_FIELD_IPV4_TCP 0 x00010000
#define IXGBE_VFMRQC_RSS_FIELD_IPV4 0 x00020000
#define IXGBE_VFMRQC_RSS_FIELD_IPV6 0 x00100000
#define IXGBE_VFMRQC_RSS_FIELD_IPV6_TCP 0 x00200000
#define IXGBE_WRITE_FLUSH(a) (IXGBE_READ_REG(a, IXGBE_VFSTATUS))
#endif /* _IXGBEVF_REGS_H_ */
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(vorverarbeitet am 2026-06-07)
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