/* SPDX-License-Identifier: GPL-2.0 */
/* DMA controller registers */
#define REG8_1(a0) ((const u16[8 ]) { a0, a0 + 1 , a0 + 2 , a0 + 3 , \
a0 + 4 , a0 + 5 , a0 + 6 , a0 + 7 })
#define REG8_2(a0) ((const u16[8 ]) { a0, a0 + 2 , a0 + 4 , a0 + 6 , \
a0 + 8 , a0 + 0 xa, a0 + 0 xc, a0 + 0 xe})
#define REG8_8(a0) ((const u16[8 ]) { a0, a0 + 8 , a0 + 0 x10, a0 + 0 x18, \
a0 + 0 x20, a0 + 0 x28, a0 + 0 x30, \
a0 + 0 x38})
#define INT_STATUS 0 x00
#define PB_STATUS 0 x01
#define DMA_CMD 0 x02
#define VIDEO_FIFO_STATUS 0 x03
#define VIDEO_CHANNEL_ID 0 x04
#define VIDEO_PARSER_STATUS 0 x05
#define SYS_SOFT_RST 0 x06
#define DMA_PAGE_TABLE0_ADDR ((const u16[8 ]) { 0 x08, 0 xd0, 0 xd2, 0 xd4, \
0 xd6, 0 xd8, 0 xda, 0 xdc })
#define DMA_PAGE_TABLE1_ADDR ((const u16[8 ]) { 0 x09, 0 xd1, 0 xd3, 0 xd5, \
0 xd7, 0 xd9, 0 xdb, 0 xdd })
#define DMA_CHANNEL_ENABLE 0 x0a
#define DMA_CONFIG 0 x0b
#define DMA_TIMER_INTERVAL 0 x0c
#define DMA_CHANNEL_TIMEOUT 0 x0d
#define VDMA_CHANNEL_CONFIG REG8_1(0 x10)
#define ADMA_P_ADDR REG8_2(0 x18)
#define ADMA_B_ADDR REG8_2(0 x19)
#define DMA10_P_ADDR 0 x28
#define DMA10_B_ADDR 0 x29
#define VIDEO_CONTROL1 0 x2a
#define VIDEO_CONTROL2 0 x2b
#define AUDIO_CONTROL1 0 x2c
#define AUDIO_CONTROL2 0 x2d
#define PHASE_REF 0 x2e
#define GPIO_REG 0 x2f
#define INTL_HBAR_CTRL REG8_1(0 x30)
#define AUDIO_CONTROL3 0 x38
#define VIDEO_FIELD_CTRL REG8_1(0 x39)
#define HSCALER_CTRL REG8_1(0 x42)
#define VIDEO_SIZE REG8_1(0 x4A)
#define VIDEO_SIZE_F2 REG8_1(0 x52)
#define MD_CONF REG8_1(0 x60)
#define MD_INIT REG8_1(0 x68)
#define MD_MAP0 REG8_1(0 x70)
#define VDMA_P_ADDR REG8_8(0 x80) /* not used in DMA SG mode */
#define VDMA_WHP REG8_8(0 x81)
#define VDMA_B_ADDR REG8_8(0 x82)
#define VDMA_F2_P_ADDR REG8_8(0 x84)
#define VDMA_F2_WHP REG8_8(0 x85)
#define VDMA_F2_B_ADDR REG8_8(0 x86)
#define EP_REG_ADDR 0 xfe
#define EP_REG_DATA 0 xff
/* Video decoder registers */
#define VDREG8(a0) ((const u16[8 ]) { \
a0 + 0 x000, a0 + 0 x010, a0 + 0 x020, a0 + 0 x030, \
a0 + 0 x100, a0 + 0 x110, a0 + 0 x120, a0 + 0 x130})
#define VIDSTAT VDREG8(0 x100)
#define BRIGHT VDREG8(0 x101)
#define CONTRAST VDREG8(0 x102)
#define SHARPNESS VDREG8(0 x103)
#define SAT_U VDREG8(0 x104)
#define SAT_V VDREG8(0 x105)
#define HUE VDREG8(0 x106)
#define CROP_HI VDREG8(0 x107)
#define VDELAY_LO VDREG8(0 x108)
#define VACTIVE_LO VDREG8(0 x109)
#define HDELAY_LO VDREG8(0 x10a)
#define HACTIVE_LO VDREG8(0 x10b)
#define MVSN VDREG8(0 x10c)
#define STATUS2 VDREG8(0 x10d)
#define SDT VDREG8(0 x10e)
#define SDT_EN VDREG8(0 x10f)
#define VSCALE_LO VDREG8(0 x144)
#define SCALE_HI VDREG8(0 x145)
#define HSCALE_LO VDREG8(0 x146)
#define F2CROP_HI VDREG8(0 x147)
#define F2VDELAY_LO VDREG8(0 x148)
#define F2VACTIVE_LO VDREG8(0 x149)
#define F2HDELAY_LO VDREG8(0 x14a)
#define F2HACTIVE_LO VDREG8(0 x14b)
#define F2VSCALE_LO VDREG8(0 x14c)
#define F2SCALE_HI VDREG8(0 x14d)
#define F2HSCALE_LO VDREG8(0 x14e)
#define F2CNT VDREG8(0 x14f)
#define VDREG2(a0) ((const u16[2 ]) { a0, a0 + 0 x100 })
#define SRST VDREG2(0 x180)
#define ACNTL VDREG2(0 x181)
#define ACNTL2 VDREG2(0 x182)
#define CNTRL1 VDREG2(0 x183)
#define CKHY VDREG2(0 x184)
#define SHCOR VDREG2(0 x185)
#define CORING VDREG2(0 x186)
#define CLMPG VDREG2(0 x187)
#define IAGC VDREG2(0 x188)
#define VCTRL1 VDREG2(0 x18f)
#define MISC1 VDREG2(0 x194)
#define LOOP VDREG2(0 x195)
#define MISC2 VDREG2(0 x196)
#define CLMD VDREG2(0 x197)
#define ANPWRDOWN VDREG2(0 x1ce)
#define AIGAIN ((const u16[8 ]) { 0 x1d0, 0 x1d1, 0 x1d2, 0 x1d3, \
0 x2d0, 0 x2d1, 0 x2d2, 0 x2d3 })
#define SYS_MODE_DMA_SHIFT 13
#define AUDIO_DMA_SIZE_SHIFT 19
#define AUDIO_DMA_SIZE_MIN SZ_512
#define AUDIO_DMA_SIZE_MAX SZ_4K
#define AUDIO_DMA_SIZE_MASK (SZ_8K - 1 )
#define DMA_CMD_ENABLE BIT(31 )
#define INT_STATUS_DMA_TOUT BIT(17 )
#define TW686X_VIDSTAT_HLOCK BIT(6 )
#define TW686X_VIDSTAT_VDLOSS BIT(7 )
#define TW686X_STD_NTSC_M 0
#define TW686X_STD_PAL 1
#define TW686X_STD_SECAM 2
#define TW686X_STD_NTSC_443 3
#define TW686X_STD_PAL_M 4
#define TW686X_STD_PAL_CN 5
#define TW686X_STD_PAL_60 6
#define TW686X_FIELD_MODE 0 x3
#define TW686X_FRAME_MODE 0 x2
/* 0x1 is reserved */
#define TW686X_SG_MODE 0 x0
#define TW686X_FIFO_ERROR(x) (x & ~(0 xff))
Messung V0.5 in Prozent C=94 H=93 G=93
¤ Dauer der Verarbeitung: 0.1 Sekunden
(vorverarbeitet am 2026-06-07)
¤
*© Formatika GbR, Deutschland