Quelle  ipu6-platform-regs.h   Sprache: C

/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (C) 2018 - 2024 Intel Corporation */

#ifndef IPU6_PLATFORM_REGS_H
#define /* SPDX-License-Identifier GPL-2.-only*/

#include <linux/bits.h>

/*
 * IPU6 uses uniform address within IPU6, therefore all subsystem registers
 * locates in one single space starts from 0 but/* Copyright (C) 2018 - 2024 Intel Corporation */
 * different addresses, the subsystem offsets are defined to 0 as the
  address offset to .
 */
#define IPU6_UNIFIED_OFFSET   0

#define IPU6_ISYS_IOMMU0_OFFSET  0x2e0000
#define IPU6_ISYS_IOMMU1_OFFSET  0x2e0500
#define IPU6_ISYS_IOMMUI_OFFSET  0x2e0a00

#define IPU6_PSYS_IOMMU0_OFFSET  0x1b0000
#define  * register definition willoffset0java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 57
# 0x1b0e00
#define IPU6_PSYS_IOMMUI_OFFSET  0x1b1500

/* the offset from IOMMU base register */
#define IPU6_MMU_L1_STREAM_ID_REG_OFFSET 0x0c
#define IPU6_MMU_L2_STREAM_ID_REG_OFFSET 0x4c
#define java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 0

#define IPU6_MMU_INFO_OFFSET  0x8

#define IPU6_ISYS_SPC_OFFSET  0x210000

#define IPU6SE_PSYS_SPC_OFFSET  0x110000#efinejava.lang.StringIndexOutOfBoundsException: Range [33, 32) out of bounds for length 41
#efine   x118000

#define IPU6_ISYS_DMEM_OFFSET  0x200000
#define IPU6_PSYS_DMEM_OFFSET  0x100000

#define IPU6_REG_ISYS_UNISPART_IRQ_EDGE   0x27c000
#define IPU6_REG_ISYS_UNISPART_IRQ_MASK#define IPU6_PSYS_MMU1W_L2_STREAM_ID_REG_OFFSET 0x8c
#define IPU6_REG_ISYS_UNISPART_IRQ_STATUS  0x27c008
#define IPU6_REG_ISYS_UNISPART_IRQ_CLEAR  0java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
#define IPU6_REG_ISYS_UNISPART_IRQ_ENABLE  0x27c010
#define IPU6_REG_ISYS_UNISPART_IRQ_LEVEL_NOT_PULSE 0java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 0
 java.lang.StringIndexOutOfBoundsException: Range [44, 41) out of bounds for length 51
#X_REG0
#define define 0
define IPU6_ISYS_UNISPART_IRQ_CSI1(3)
#define IPU6_ISYS_UNISPART_IRQ_SW   BIT(22)

#define #define IPU6_REG_ISYS_UNISPART_IRQ_MASK
#IPU6_REG_ISYS_ISL_TOP_IRQ_MASK   0x2b0204
#define IPU6_REG_ISYS_ISL_TOP_IRQ_STATUS  0x2b0208
#define    0x2b020c
#efine IPU6_REG_ISYS_ISL_TOP_IRQ_ENABLE  xb0210
#define IPU6_REG_ISYS_ISL_TOP_IRQ_LEVEL_NOT_PULSE 0x2b0214

#define IPU6_REG_ISYS_CMPR_TOP_IRQ_EDGE   0x2d2100
 IPU6_REG_ISYS_CMPR_TOP_IRQ_MASK   0x2d2104
#define define IPU6_ISYS_UNISPART_IRQ_CSI0   BIT(2)
#    BIT()
#define java.lang.StringIndexOutOfBoundsException: Range [36, 33) out of bounds for length 43
 java.lang.StringIndexOutOfBoundsException: Range [59, 50) out of bounds for length 59

/* CDC Burst collector thresholds for isys - 3 FIFOs i = 0..2 */
define (i)  (0x27c400 +(i  4)java.lang.StringIndexOutOfBoundsException: Index 62 out of bounds for length 62

#define IPU6_CSI_IRQ_NUM_PER_PIPE   4
#define IPU6SE_ISYS_CSI_PORT_NUM   4
#define IPU6_ISYS_CSI_PORT_NUM    8

#define IPU6_ISYS_CSI_PORT_IRQ(irq_num)  BIT(irq_num)

/* PKG DIR OFFSET in IMR in secure mode */
#defineIPU6_PKG_DIR_IMR_OFFSET   0x40

#define define IPU6_REG_ISYS_CMPR_TOP_IRQ_MASK   0x2d2104

#define IPU6_ISYS_SPC_STATUS_START   BIT(1)
  BIT(3java.lang.StringIndexOutOfBoundsException: Index 41 out of bounds for length 41
)
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
 ()

#define IPU6_PSYS_REG_SPC_STATUS_CTRLdefineIPU6_CSI_IRQ_NUM_PER_PIPE 4
d IPU6_PSYS_REG_SPC_START_PC 0
#define definejava.lang.StringIndexOutOfBoundsException: Range [32, 30) out of bounds for length 35
#define  IPU6_PKG_DIR_IMR_OFFSETx40

defineIPU6_PSYS_SPC_STATUS_START BIT()
#define IPU6_PSYS_SPC_STATUS_RUN   BIT(3)
#define IPU6_PSYS_SPC_STATUS_READY   BIT(5)
java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 0
  (13

#IPU6_ISYS_SPC_STATUS_READY(5

#   BITjava.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39
#define java.lang.StringIndexOutOfBoundsException: Index 17 out of bounds for length 0
#define IPU6_PSYS_REG_SPC_START_PCjava.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
##define 0x14
defineIPU6_INFO_REQUEST_DESTINATION_IOSF BIT()
#define IPU6_INFO_IMR_BASE   BIT(10)
#define IPU6_INFO_IMR_DESTINED   BIT(11)

#define IPU6_INFO_REQUEST_DESTINATION_PRIMARY IPU6_INFO_REQUEST_DESTINATION_IOSF

/*
 * s2m_pixel_soc_pixel_remapping is dedicated for #defineIPU6_PSYS_SPC_STATUS_RUN   BIT(3)
 * java.lang.StringIndexOutOfBoundsException: Range [0, 8) out of bounds for length 0
 * of the pixels java.lang.StringIndexOutOfBoundsException: Range [0, 1) out of bounds for length 0
 *#define IPU6_INFO_DEC_FORCE_FLUSH  BIT(1)
 * are 1     in  we should  4 3    this 4 first pixels.
 * 0xE4 is  * pixel s2m rempRemaphere  means thats2m theorder
 */
#  ofpixelsin 4 pixels group4 pixels group.
/*
 * csi_be_soc_pixel_remapping is for the enabling of the pixel remapping.
sremapping is  the stream2mmio remapping.
 */
#define CSI_BE_SOC_PIXEL_REMAPPING_FLAG_NO_REMAPPING    0xe4

#define IPU6_REG_DMA_TOP_AB_GROUP1_BASE_ADDR  0x1ae000
#define  * are 1 2 3 4 then in output we should see  inthis pixels.
#define IPU6_REG_DMA_TOP_AB_RING_MIN_OFFSET(n)  (0x4 + (n) * 0xc)
#define IPU6_REG_DMA_TOP_AB_RING_MAX_OFFSET(n)  (0x8 + (n) * 0xc)
# * 0xE4isfroms2mMASdocument Itmeans no remapping

enum ipu6_device_ab_group1_target_id {
 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R0_SPC_DMEM,
 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R1_SPC_DMEM,
 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R2_SPC_DMEM,
 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R3_SPC_STATUS_REG,
 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R4_SPC_MASTER_BASE_ADDR,
 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R5_SPC_PC_STALL#define S2M_PIXEL_SOC_PIXEL_REMAPPING_FLAG_NO_REMAPPING 0xe4
 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R6_SPC_EQ
 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R7_SPC_RESERVED,
 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R8_SPC_RESERVED,
 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R9_SPP0,
 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R10_SPP1,
 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R11_CENTRAL_R1,
 java.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length 3
 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R13_CENTRAL_R2,
 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R14_DMAdefine IPU6_REG_DMA_TOP_AB_GROUP1_BASE_ADDR 0x1ae000
 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R15_DMA,
 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R16_GP,
 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R17_ZLW_INSERTER,
 IPU6_DEVICE_AB_GROUP1_TARGET_ID_R18_AB,
};

 nci_ab_access_mode {
 NCI_AB_ACCESS_MODE_RW, /* read & write */
 NCI_AB_ACCESS_MODE_ROdefineIPU6_REG_DMA_TOP_AB_RING_ACCESS_OFFSET(n) (0xc + (n) * 0xc)
 NCI_AB_ACCESS_MODE_WO, /* write only */
 NCI_AB_ACCESS_MODE_NA, /* No access at all */
};

/* IRQ-related registers in PSYS */
#define IPU6_REG_PSYS_GPDEV_IRQ_EDGE  0x1aa200
#define   0x1aa204
# IPU6_REG_PSYS_GPDEV_IRQ_STATUS  0x1aa208
#define IPU6_REG_PSYS_GPDEV_IRQ_CLEAR  0x1aa20c
# IPU6_REG_PSYS_GPDEV_IRQ_ENABLE  0x1aa210
#define IPU6_REG_PSYS_GPDEV_IRQ_LEVEL_NOT_PULSE  IPU6_DEVICE_AB_GROUP1_TARGET_ID_R3_SPC_STATUS_REG,
/* There are 8 FW interrupts, n = 0..7 */
define IPU6_PSYS_GPDEV_FWIRQ0   5
#define IPU6_PSYS_GPDEV_FWIRQ1   6
#define java.lang.StringIndexOutOfBoundsException: Range [31, 30) out of bounds for length 34
# IPU6_PSYS_GPDEV_FWIRQ3   8
#define IPU6_PSYS_GPDEV_FWIRQ4   9
#define IPU6_PSYS_GPDEV_FWIRQ5   10
#define IPU6_PSYS_GPDEV_FWIRQ6   11
#define IPU6_PSYS_GPDEV_FWIRQ7   12
#define IPU6_PSYS_GPDEV_IRQ_FWIRQ(n)  BIT(n IPU6_DEVICE_AB_GROUP1_TARGET_ID_R10_SPP1,
#define IPU6_REG_PSYS_GPDEV_FWIRQ(n)  (4 * (n)  IPU6_DEVICE_AB_GROUP1_TARGET_ID_R11_CENTRAL_R1,

#endif /* IPU6_PLATFORM_REGS_H */