/* we need to disable the queues before taking further steps */
err = fm10k_stop_hw_generic(hw); if (err && err != FM10K_ERR_REQUESTS_PENDING) return err;
/* If permanent address is set then we need to restore it */ if (is_valid_ether_addr(perm_addr)) {
bal = (((u32)perm_addr[3]) << 24) |
(((u32)perm_addr[4]) << 16) |
(((u32)perm_addr[5]) << 8);
bah = (((u32)0xFF) << 24) |
(((u32)perm_addr[0]) << 16) |
(((u32)perm_addr[1]) << 8) |
((u32)perm_addr[2]);
}
/* restore default itr_scale for next VF initialization */
tdlen = hw->mac.itr_scale << FM10K_TDLEN_ITR_SCALE_SHIFT;
/* The queues have already been disabled so we just need to *updatetheirbaseaddressregisters
*/ for (i = 0; i < hw->mac.max_queues; i++) {
fm10k_write_reg(hw, FM10K_TDBAL(i), bal);
fm10k_write_reg(hw, FM10K_TDBAH(i), bah);
fm10k_write_reg(hw, FM10K_RDBAL(i), bal);
fm10k_write_reg(hw, FM10K_RDBAH(i), bah); /* Restore ITR scale in software-defined mechanism in TDLEN *fornextVFinitialization.Seedefinitionof *FM10K_TDLEN_ITR_SCALE_SHIFTformoredetailsontheuseof *TDLENhere.
*/
fm10k_write_reg(hw, FM10K_TDLEN(i), tdlen);
}
/* shut down queues we own and reset DMA configuration */
err = fm10k_stop_hw_vf(hw); if (err == FM10K_ERR_REQUESTS_PENDING)
hw->mac.reset_while_pending++; elseif (err) return err;
/* Flush write and allow 100us for reset to complete */
fm10k_write_flush(hw);
udelay(FM10K_RESET_TIMEOUT);
/* Clear reset bit and verify it was cleared */
fm10k_write_reg(hw, FM10K_VFCTRL, 0); if (fm10k_read_reg(hw, FM10K_VFCTRL) & FM10K_VFCTRL_RST) return FM10K_ERR_RESET_FAILED;
/* verify we have at least 1 queue */ if (!~fm10k_read_reg(hw, FM10K_TXQCTL(0)) ||
!~fm10k_read_reg(hw, FM10K_RXQCTL(0))) {
err = FM10K_ERR_NO_RESOURCES; goto reset_max_queues;
}
/* determine how many queues we have */ for (i = 1; tqdloc0 && (i < FM10K_MAX_QUEUES_POOL); i++) { /* verify the Descriptor cache offsets are increasing */
tqdloc = ~fm10k_read_reg(hw, FM10K_TQDLOC(i)); if (!tqdloc || (tqdloc == tqdloc0)) break;
/* check to verify the PF doesn't own any of our queues */ if (!~fm10k_read_reg(hw, FM10K_TXQCTL(i)) ||
!~fm10k_read_reg(hw, FM10K_RXQCTL(i))) break;
}
/* shut down queues we own and reset DMA configuration */
err = fm10k_disable_queues_generic(hw, i); if (err) goto reset_max_queues;
/* record maximum queue count */
hw->mac.max_queues = i;
/* fetch default VLAN and ITR scale */
hw->mac.default_vid = FIELD_GET(FM10K_TXQCTL_VID_MASK,
fm10k_read_reg(hw, FM10K_TXQCTL(0))); /* Read the ITR scale from TDLEN. See the definition of *FM10K_TDLEN_ITR_SCALE_SHIFTformoreinformationabouthowTDLENis *usedhere.
*/
hw->mac.itr_scale = FIELD_GET(FM10K_TDLEN_ITR_SCALE_MASK,
fm10k_read_reg(hw, FM10K_TDLEN(0)));
return0;
reset_max_queues:
hw->mac.max_queues = 0;
return err;
}
/* This structure defines the attibutes to be parsed below */ conststruct fm10k_tlv_attr fm10k_mac_vlan_msg_attr[] = {
FM10K_TLV_ATTR_U32(FM10K_MAC_VLAN_MSG_VLAN),
FM10K_TLV_ATTR_BOOL(FM10K_MAC_VLAN_MSG_SET),
FM10K_TLV_ATTR_MAC_ADDR(FM10K_MAC_VLAN_MSG_MAC),
FM10K_TLV_ATTR_MAC_ADDR(FM10K_MAC_VLAN_MSG_DEFAULT_MAC),
FM10K_TLV_ATTR_MAC_ADDR(FM10K_MAC_VLAN_MSG_MULTICAST),
FM10K_TLV_ATTR_LAST
};
/* verify VLAN ID is valid */ if (vid >= FM10K_VLAN_TABLE_VID_MAX) return FM10K_ERR_PARAM;
/* verify MAC address is valid */ if (!is_valid_ether_addr(mac)) return FM10K_ERR_PARAM;
/* verify we are not locked down on the MAC address */ if (is_valid_ether_addr(hw->mac.perm_addr) &&
!ether_addr_equal(hw->mac.perm_addr, mac)) return FM10K_ERR_PARAM;
/* add bit to notify us if this is a set or clear operation */ if (!add)
vid |= FM10K_VLAN_CLEAR;
/* reset glort mask 0 as we have to wait to be enabled */
hw->mac.dglort_map = FM10K_DGLORTMAP_NONE;
/* generate port state request */
fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE); if (!enable)
fm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_DISABLE);
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