/* * Copyright 2023 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * Authors: AMD *
*/
/* FILE POLICY AND INTENDED USAGE: * This file owns timing validation against various link limitations. (ex. * link bandwidth, receiver capability or our hardware capability) It also * provides helper functions exposing bandwidth formulas used in validation.
*/ #include"link_validation.h" #include"protocols/link_dp_capability.h" #include"protocols/link_dp_dpia_bw.h" #include"resource.h"
switch (dpcd_caps->dongle_type) { case DISPLAY_DONGLE_DP_VGA_CONVERTER: case DISPLAY_DONGLE_DP_DVI_CONVERTER: case DISPLAY_DONGLE_DP_DVI_DONGLE: if (timing->pixel_encoding == PIXEL_ENCODING_RGB) returntrue; else returnfalse; default: break;
}
if (dpcd_caps->dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER &&
dongle_caps->extendedCapValid == true) { /* Check Pixel Encoding */ switch (timing->pixel_encoding) { case PIXEL_ENCODING_RGB: case PIXEL_ENCODING_YCBCR444: break; case PIXEL_ENCODING_YCBCR422: if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through) returnfalse; break; case PIXEL_ENCODING_YCBCR420: if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through) returnfalse; break; case PIXEL_ENCODING_UNDEFINED: /* These color depths are currently not supported */
ASSERT(false); break; default: /* Invalid Pixel Encoding*/ returnfalse;
}
switch (timing->display_color_depth) { case COLOR_DEPTH_666: case COLOR_DEPTH_888: /*888 and 666 should always be supported*/ break; case COLOR_DEPTH_101010: if (dongle_caps->dp_hdmi_max_bpc < 10) returnfalse; break; case COLOR_DEPTH_121212: if (dongle_caps->dp_hdmi_max_bpc < 12) returnfalse; break; case COLOR_DEPTH_UNDEFINED: /* These color depths are currently not supported */
ASSERT(false); break; case COLOR_DEPTH_141414: case COLOR_DEPTH_161616: default: /* These color depths are currently not supported */ returnfalse;
}
/* Check 3D format */ switch (timing->timing_3d_format) { case TIMING_3D_FORMAT_NONE: case TIMING_3D_FORMAT_FRAME_ALTERNATE: /*Only frame alternate 3D is supported on active dongle*/ break; default: /*other 3D formats are not supported due to bad infoframe translation */ returnfalse;
}
if (dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps > 0) { // DP to HDMI FRL converter struct dc_crtc_timing outputTiming = *timing;
if (timing->flags.DSC && !timing->dsc_cfg.is_frl) /* DP input has DSC, HDMI FRL output doesn't have DSC, remove DSC from output timing */
outputTiming.flags.DSC = 0; if (dc_bandwidth_in_kbps_from_timing(&outputTiming, DC_LINK_ENCODING_HDMI_FRL) >
dongle_caps->dp_hdmi_frl_max_link_bw_in_kbps) returnfalse;
} else { // DP to HDMI TMDS converter if (get_tmds_output_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10)) returnfalse;
}
}
switch (link_dp_get_encoding_format(link_settings)) { case DP_8b_10b_ENCODING: /* For 8b/10b encoding: * link rate is defined in the unit of LINK_RATE_REF_FREQ_IN_KHZ per DP byte per lane. * data bandwidth efficiency is 80% with additional 3% overhead if FEC is supported.
*/
link_rate_per_lane_kbps = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000; if (dp_should_enable_fec(link)) {
total_data_bw_efficiency_x10000 /= 100;
total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
} break; case DP_128b_132b_ENCODING: /* For 128b/132b encoding: * link rate is defined in the unit of 10mbps per lane. * total data bandwidth efficiency is always 96.71%.
*/
link_rate_per_lane_kbps = link_settings->link_rate * 10000;
total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000; break; default: break;
}
/* overall effective link bandwidth = link rate per lane * lane count * total data bandwidth efficiency */ return link_rate_per_lane_kbps * link_settings->lane_count / 10000 * total_data_bw_efficiency_x10000;
}
/* According to spec, VSC SDP should be used if pixel format is YCbCr420 */ if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
!link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL) returnfalse;
if (is_max_uncompressed_pixel_rate_exceeded && !timing->flags.DSC) { returnfalse;
}
if (req_bw <= max_bw) { /* remember the biggest mode here, during * initial link training (to get * verified_link_cap), LS sends event about * cannot train at reported cap to upper * layer and upper layer will re-enumerate modes. * this is not necessary if the lower * verified_link_cap is enough to drive
* all the modes */
/* TODO: DYNAMIC_VALIDATION needs to be implemented */ /* if (flags.DYNAMIC_VALIDATION == 1) dpsst->max_req_bw_for_verified_linkcap = dal_max(
dpsst->max_req_bw_for_verified_linkcap, req_bw); */ returntrue;
} else returnfalse;
}
/* A hack to avoid failing any modes for EDID override feature on * topology change such as lower quality cable for DP or different dongle
*/ if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL) return DC_OK;
/* Active Dongle*/ if (!dp_active_dongle_validate_timing(timing, dpcd_caps)) return DC_EXCEED_DONGLE_CAP;
switch (stream->signal) { case SIGNAL_TYPE_EDP: case SIGNAL_TYPE_DISPLAY_PORT: if (!dp_validate_mode_timing(
link,
timing)) return DC_NO_DP_LINK_BANDWIDTH; break;
for (i = 0; i < MAX_PIPES; i++) { if (context->res_ctx.pipe_ctx[i].stream && (context->res_ctx.pipe_ctx[i].stream == stream)) {
dp_tunnel_settings = &context->res_ctx.pipe_ctx[i].link_config.dp_tunnel_settings; break;
}
}
return dp_tunnel_settings;
}
/* * Calculates the DP tunneling bandwidth required for the stream timing * and aggregates the stream bandwidth for the respective DP tunneling link * * return: dc_status
*/ enum dc_status link_validate_dp_tunnel_bandwidth(conststruct dc *dc, conststruct dc_state *new_ctx)
{ struct dc_validation_dpia_set dpia_link_sets[MAX_DPIA_NUM] = { 0 };
uint8_t link_count = 0; enum dc_status result = DC_OK;
// Iterate through streams in the new context for (uint8_t i = 0; (i < MAX_PIPES && i < new_ctx->stream_count); i++) { conststruct dc_stream_state *stream = new_ctx->streams[i]; conststruct dc_link *link; conststruct dc_tunnel_settings *dp_tunnel_settings;
uint32_t timing_bw;
/* Current calculation only applicable for 8b/10b MST and 128b/132b SST/MST.
*/ static uint32_t calculate_overhead_hblank_bw_in_symbols(
uint32_t max_slice_h)
{
uint32_t overhead_hblank_bw = 0; /* in stream symbols */
overhead_hblank_bw += max_slice_h * 4; /* EOC overhead */
overhead_hblank_bw += 12; /* Main link overhead (VBID, BS/BE) */
return overhead_hblank_bw;
}
uint32_t dp_required_hblank_size_bytes( conststruct dc_link *link, struct dp_audio_bandwidth_params *audio_params)
{ /* Main logic from dce_audio is duplicated here, with the main * difference being: * - Pre-determined lane count of 4 * - Assumed 16 dsc slices for worst case * - Assumed SDP split disabled for worst case * TODO: Unify logic from dce_audio to prevent duplicated logic.
*/
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