// SPDX-License-Identifier: GPL-2.0-or-later /* * spu_save.c * * (C) Copyright IBM Corp. 2005 * * SPU-side context save sequence outlined in * Synergistic Processor Element Book IV * * Author: Mark Nutter <mnutter@us.ibm.com>
*/
/* Save, Step 2: * Read the SPU_RdEventMsk channel and save to the LSCSA.
*/
offset = LSCSA_QW_OFFSET(event_mask);
regs_spill[offset].slot[0] = spu_readch(SPU_RdEventMask);
}
/* Save, Step 3: * Read the SPU_RdTagMsk channel and save to the LSCSA.
*/
offset = LSCSA_QW_OFFSET(tag_mask);
regs_spill[offset].slot[0] = spu_readch(MFC_RdTagMask);
}
/* Save, Step 7: * Enqueue the PUTL command (tag 0) to the MFC SPU command * queue to transfer the remaining 240 kb of LS to CSA.
*/
spu_writech(MFC_LSA, ls);
spu_writech(MFC_EAH, lscsa_ea.ui[0]);
spu_writech(MFC_EAL, list);
spu_writech(MFC_Size, size);
spu_writech(MFC_TagID, tag_id);
spu_writech(MFC_Cmd, cmd);
}
staticinlinevoid save_fpcr(void)
{ // vector unsigned int fpcr; unsignedint offset;
/* Save, Step 9: * Issue the floating-point status and control register * read instruction, and save to the LSCSA.
*/
offset = LSCSA_QW_OFFSET(fpcr);
regs_spill[offset].v = spu_mffpscr();
}
/* Save, Step 10: * Read and save the SPU_RdDec channel data to * the LSCSA.
*/
offset = LSCSA_QW_OFFSET(decr);
regs_spill[offset].slot[0] = spu_readch(SPU_RdDec);
}
/* Save, Step 11: * Read and save the SPU_WSRR0 channel data to * the LSCSA.
*/
offset = LSCSA_QW_OFFSET(srr0);
regs_spill[offset].slot[0] = spu_readch(SPU_RdSRR0);
}
staticinlinevoid save_complete(void)
{ /* Save, Step 18: * Issue a stop-and-signal instruction indicating * "save complete". Note: This function will not * return!!
*/
spu_stop(SPU_SAVE_COMPLETE);
}
/** * main - entry point for SPU-side context save. * * This code deviates from the documented sequence as follows: * * 1. The EA for LSCSA is passed from PPE in the * signal notification channels. * 2. All 128 registers are saved by crt0.o.
*/ int main()
{
addr64 lscsa_ea;
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