// SPDX-License-Identifier: GPL-2.0
/*
* Copyright ( C ) 1993 Hamish Macdonald
* Copyright ( C ) 1999 D . Jeff Dionne
* Copyright ( C ) 2001 Georges Menie , Ken Desmet
*
* This file is subject to the terms and conditions of the GNU General Public
* License . See the file COPYING in the main directory of this archive
* for more details .
*/
#include <linux/init.h>
#include <asm /machdep.h>
#include <asm /MC68VZ328.h>
#include "m68328.h"
#include "screen.h"
/***************************************************************************/
/* Init Dragon Engine II hardware */
/***************************************************************************/
static void dragen2_reset(void )
{
local_irq_disable();
#ifdef CONFIG_INIT_LCD
PBDATA |= 0 x20; /* disable CCFL light */
PKDATA |= 0 x4; /* disable LCD controller */
LCKCON = 0 ;
#endif
__asm__ __volatile__(
"reset\n\t"
"moveal #0x04000000, %a0\n\t"
"moveal 0(%a0), %sp\n\t"
"moveal 4(%a0), %a0\n\t"
"jmp (%a0)"
);
}
void __init init_dragen2(char *command, int size)
{
mach_reset = dragen2_reset;
#ifdef CONFIG_DIRECT_IO_ACCESS
SCR = 0 x10; /* allow user access to internal registers */
#endif
/* CSGB Init */
CSGBB = 0 x4000;
CSB = 0 x1a1;
/* CS8900 init */
/* PK3: hardware sleep function pin, active low */
PKSEL |= PK(3 ); /* select pin as I/O */
PKDIR |= PK(3 ); /* select pin as output */
PKDATA |= PK(3 ); /* set pin high */
/* PF5: hardware reset function pin, active high */
PFSEL |= PF(5 ); /* select pin as I/O */
PFDIR |= PF(5 ); /* select pin as output */
PFDATA &= ~PF(5 ); /* set pin low */
/* cs8900 hardware reset */
PFDATA |= PF(5 );
{ int i; for (i = 0 ; i < 32000 ; ++i); }
PFDATA &= ~PF(5 );
/* INT1 enable (cs8900 IRQ) */
PDPOL &= ~PD(1 ); /* active high signal */
PDIQEG &= ~PD(1 );
PDIRQEN |= PD(1 ); /* IRQ enabled */
#ifdef CONFIG_INIT_LCD
/* initialize LCD controller */
LSSA = (long ) screen_bits;
LVPW = 0 x14;
LXMAX = 0 x140;
LYMAX = 0 xef;
LRRA = 0 ;
LPXCD = 3 ;
LPICF = 0 x08;
LPOLCF = 0 ;
LCKCON = 0 x80;
PCPDEN = 0 xff;
PCSEL = 0 ;
/* Enable LCD controller */
PKDIR |= 0 x4;
PKSEL |= 0 x4;
PKDATA &= ~0 x4;
/* Enable CCFL backlighting circuit */
PBDIR |= 0 x20;
PBSEL |= 0 x20;
PBDATA &= ~0 x20;
/* contrast control register */
PFDIR |= 0 x1;
PFSEL &= ~0 x1;
PWMR = 0 x037F;
#endif
}
Messung V0.5 in Prozent C=73 H=75 G=73
¤ Dauer der Verarbeitung: 0.14 Sekunden
(vorverarbeitet am 2026-09-28)
¤
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