Quelle  r9a08g045.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Device Tree Source for the RZ/G3S SoC
 *
 * Copyright (C) 2023 Renesas Electronics Corp.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a08g045-cpg.h>
#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>

/ {
 compatible = "renesas,r9a08g045";
 #address-cells = <2>;
 #size-cells = <2>;

 audio_clk1: audio1-clk {
  compatible = "fixed-clock";
  #clock-cells = <0>;
  /* This value must be overridden by boards that provide it. */
  clock-frequency = <0>;
 };

 audio_clk2: audio2-clk {
  compatible = "fixed-clock";
  #clock-cells = <0>;
  /* This value must be overridden by boards that provide it. */
  clock-frequency = <0>;
 };

 cluster0_opp: opp-table-0 {
  compatible = "operating-points-v2";
  opp-shared;

  opp-137500000 {
   opp-hz = /bits/ 64 <137500000>;
   opp-microvolt = <940000>;
   clock-latency-ns = <300000>;
  };
  opp-275000000 {
   opp-hz = /bits/ 64 <275000000>;
   opp-microvolt = <940000>;
   clock-latency-ns = <300000>;
  };
  opp-550000000 {
   opp-hz = /bits/ 64 <550000000>;
   opp-microvolt = <940000>;
   clock-latency-ns = <300000>;
  };
  opp-1100000000 {
   opp-hz = /bits/ 64 <1100000000>;
   opp-microvolt = <940000>;
   clock-latency-ns = <300000>;
   opp-suspend;
  };
 };

 cpus {
  #address-cells = <1>;
  #size-cells = <0>;

  cpu0: cpu@0 {
   compatible = "arm,cortex-a55";
   reg = <0>;
   device_type = "cpu";
   #cooling-cells = <2>;
   next-level-cache = <&L3_CA55>;
   enable-method = "psci";
   clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
   operating-points-v2 = <&cluster0_opp>;
  };

  L3_CA55: cache-controller-0 {
   compatible = "cache";
   cache-level = <3>;
   cache-unified;
   cache-size = <0x40000>;
  };
 };

 extal_clk: extal-clk {
  compatible = "fixed-clock";
  #clock-cells = <0>;
  /* This value must be overridden by the board. */
  clock-frequency = <0>;
 };

 psci {
  compatible = "arm,psci-1.0", "arm,psci-0.2";
  method = "smc";
 };

 soc: soc {
  compatible = "simple-bus";
  interrupt-parent = <&gic>;
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  scif0: serial@1004b800 {
   compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
   reg = <0 0x1004b800 0 0x400>;
   interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "eri", "rxi", "txi",
       "bri", "dri", "tei";
   clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
   clock-names = "fck";
   power-domains = <&cpg>;
   resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
   status = "disabled";
  };

  scif1: serial@1004bc00 {
   compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
   reg = <0 0x1004bc00 0 0x400>;
   interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "eri", "rxi", "txi",
       "bri", "dri", "tei";
   clocks = <&cpg CPG_MOD R9A08G045_SCIF1_CLK_PCK>;
   clock-names = "fck";
   power-domains = <&cpg>;
   resets = <&cpg R9A08G045_SCIF1_RST_SYSTEM_N>;
   status = "disabled";
  };

  scif2: serial@1004c000 {
   compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
   reg = <0 0x1004c000 0 0x400>;
   interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "eri", "rxi", "txi",
       "bri", "dri", "tei";
   clocks = <&cpg CPG_MOD R9A08G045_SCIF2_CLK_PCK>;
   clock-names = "fck";
   power-domains = <&cpg>;
   resets = <&cpg R9A08G045_SCIF2_RST_SYSTEM_N>;
   status = "disabled";
  };

  scif3: serial@1004c400 {
   compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
   reg = <0 0x1004c400 0 0x400>;
   interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "eri", "rxi", "txi",
       "bri", "dri", "tei";
   clocks = <&cpg CPG_MOD R9A08G045_SCIF3_CLK_PCK>;
   clock-names = "fck";
   power-domains = <&cpg>;
   resets = <&cpg R9A08G045_SCIF3_RST_SYSTEM_N>;
   status = "disabled";
  };

  scif4: serial@1004c800 {
   compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
   reg = <0 0x1004c800 0 0x400>;
   interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "eri", "rxi", "txi",
       "bri", "dri", "tei";
   clocks = <&cpg CPG_MOD R9A08G045_SCIF4_CLK_PCK>;
   clock-names = "fck";
   power-domains = <&cpg>;
   resets = <&cpg R9A08G045_SCIF4_RST_SYSTEM_N>;
   status = "disabled";
  };

  scif5: serial@1004e000 {
   compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
   reg = <0 0x1004e000 0 0x400>;
   interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "eri", "rxi", "txi",
       "bri", "dri", "tei";
   clocks = <&cpg CPG_MOD R9A08G045_SCIF5_CLK_PCK>;
   clock-names = "fck";
   power-domains = <&cpg>;
   resets = <&cpg R9A08G045_SCIF5_RST_SYSTEM_N>;
   status = "disabled";
  };

  rtc: rtc@1004ec00 {
   compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3";
   reg = <0 0x1004ec00 0 0x400>;
   interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "alarm", "period", "carry";
   clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>;
   clock-names = "bus", "counter";
   power-domains = <&cpg>;
   resets = <&cpg R9A08G045_VBAT_BRESETN>;
   status = "disabled";
  };

  adc: adc@10058000 {
   compatible = "renesas,r9a08g045-adc";
   reg = <0 0x10058000 0 0x1000>;
   interrupts = <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>;
   clocks = <&cpg CPG_MOD R9A08G045_ADC_ADCLK>,
     <&cpg CPG_MOD R9A08G045_ADC_PCLK>;
   clock-names = "adclk", "pclk";
   resets = <&cpg R9A08G045_ADC_PRESETN>,
     <&cpg R9A08G045_ADC_ADRST_N>;
   reset-names = "presetn", "adrst-n";
   power-domains = <&cpg>;
   #address-cells = <1>;
   #size-cells = <0>;
   #io-channel-cells = <1>;
   status = "disabled";

   channel@0 {
    reg = <0>;
   };

   channel@1 {
    reg = <1>;
   };

   channel@2 {
    reg = <2>;
   };

   channel@3 {
    reg = <3>;
   };

   channel@4 {
    reg = <4>;
   };

   channel@5 {
    reg = <5>;
   };

   channel@6 {
    reg = <6>;
   };

   channel@7 {
    reg = <7>;
   };

   channel@8 {
    reg = <8>;
   };
  };

  vbattb: clock-controller@1005c000 {
   compatible = "renesas,r9a08g045-vbattb";
   reg = <0 0x1005c000 0 0x1000>;
   interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
   clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
   clock-names = "bclk", "rtx";
   #clock-cells = <1>;
   power-domains = <&cpg>;
   resets = <&cpg R9A08G045_VBAT_BRESETN>;
   status = "disabled";
  };

  i2c0: i2c@10090000 {
   compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
   reg = <0 0x10090000 0 0x400>;
   interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "tei", "ri", "ti", "spi", "sti",
       "naki", "ali", "tmoi";
   clocks = <&cpg CPG_MOD R9A08G045_I2C0_PCLK>;
   clock-frequency = <100000>;
   resets = <&cpg R9A08G045_I2C0_MRST>;
   power-domains = <&cpg>;
   #address-cells = <1>;
   #size-cells = <0>;
   status = "disabled";
  };

  i2c1: i2c@10090400 {
   compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
   reg = <0 0x10090400 0 0x400>;
   interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "tei", "ri", "ti", "spi", "sti",
       "naki", "ali", "tmoi";
   clocks = <&cpg CPG_MOD R9A08G045_I2C1_PCLK>;
   clock-frequency = <100000>;
   resets = <&cpg R9A08G045_I2C1_MRST>;
   power-domains = <&cpg>;
   #address-cells = <1>;
   #size-cells = <0>;
   status = "disabled";
  };

  i2c2: i2c@10090800 {
   compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
   reg = <0 0x10090800 0 0x400>;
   interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "tei", "ri", "ti", "spi", "sti",
       "naki", "ali", "tmoi";
   clocks = <&cpg CPG_MOD R9A08G045_I2C2_PCLK>;
   clock-frequency = <100000>;
   resets = <&cpg R9A08G045_I2C2_MRST>;
   power-domains = <&cpg>;
   #address-cells = <1>;
   #size-cells = <0>;
   status = "disabled";
  };

  i2c3: i2c@10090c00 {
   compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
   reg = <0 0x10090c00 0 0x400>;
   interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "tei", "ri", "ti", "spi", "sti",
       "naki", "ali", "tmoi";
   clocks = <&cpg CPG_MOD R9A08G045_I2C3_PCLK>;
   clock-frequency = <100000>;
   resets = <&cpg R9A08G045_I2C3_MRST>;
   power-domains = <&cpg>;
   #address-cells = <1>;
   #size-cells = <0>;
   status = "disabled";
  };

  ssi0: ssi@100a8000 {
   compatible = "renesas,r9a08g045-ssi",
         "renesas,rz-ssi";
   reg = <0 0x100a8000 0 0x400>;
   interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>;
   interrupt-names = "int_req", "dma_rx", "dma_tx";
   clocks = <&cpg CPG_MOD R9A08G045_SSI0_PCLK2>,
     <&cpg CPG_MOD R9A08G045_SSI0_PCLK_SFR>,
     <&audio_clk1>, <&audio_clk2>;
   clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
   resets = <&cpg R9A08G045_SSI0_RST_M2_REG>;
   dmas = <&dmac 0x2665>, <&dmac 0x2666>;
   dma-names = "tx", "rx";
   power-domains = <&cpg>;
   #sound-dai-cells = <0>;
   status = "disabled";
  };

  ssi1: ssi@100a8400 {
   compatible = "renesas,r9a08g045-ssi",
         "renesas,rz-ssi";
   reg = <0 0x100a8400 0 0x400>;
   interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>;
   interrupt-names = "int_req", "dma_rx", "dma_tx";
   clocks = <&cpg CPG_MOD R9A08G045_SSI1_PCLK2>,
     <&cpg CPG_MOD R9A08G045_SSI1_PCLK_SFR>,
     <&audio_clk1>, <&audio_clk2>;
   clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
   resets = <&cpg R9A08G045_SSI1_RST_M2_REG>;
   dmas = <&dmac 0x2669>, <&dmac 0x266a>;
   dma-names = "tx", "rx";
   power-domains = <&cpg>;
   #sound-dai-cells = <0>;
   status = "disabled";
  };

  ssi2: ssi@100a8800 {
   compatible = "renesas,r9a08g045-ssi",
         "renesas,rz-ssi";
   reg = <0 0x100a8800 0 0x400>;
   interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>;
   interrupt-names = "int_req", "dma_rx", "dma_tx";
   clocks = <&cpg CPG_MOD R9A08G045_SSI2_PCLK2>,
     <&cpg CPG_MOD R9A08G045_SSI2_PCLK_SFR>,
     <&audio_clk1>, <&audio_clk2>;
   clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
   resets = <&cpg R9A08G045_SSI2_RST_M2_REG>;
   dmas = <&dmac 0x266d>, <&dmac 0x266e>;
   dma-names = "tx", "rx";
   power-domains = <&cpg>;
   #sound-dai-cells = <0>;
   status = "disabled";
  };

  ssi3: ssi@100a8c00 {
   compatible = "renesas,r9a08g045-ssi",
         "renesas,rz-ssi";
   reg = <0 0x100a8c00 0 0x400>;
   interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>;
   interrupt-names = "int_req", "dma_rx", "dma_tx";
   clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>,
     <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>,
     <&audio_clk1>, <&audio_clk2>;
   clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
   resets = <&cpg R9A08G045_SSI3_RST_M2_REG>;
   dmas = <&dmac 0x2671>, <&dmac 0x2672>;
   dma-names = "tx", "rx";
   power-domains = <&cpg>;
   #sound-dai-cells = <0>;
   status = "disabled";
  };

  cpg: clock-controller@11010000 {
   compatible = "renesas,r9a08g045-cpg";
   reg = <0 0x11010000 0 0x10000>;
   clocks = <&extal_clk>;
   clock-names = "extal";
   #clock-cells = <2>;
   #reset-cells = <1>;
   #power-domain-cells = <0>;
  };

  sysc: system-controller@11020000 {
   compatible = "renesas,r9a08g045-sysc";
   reg = <0 0x11020000 0 0x10000>;
   interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "lpm_int", "ca55stbydone_int",
       "cm33stbyr_int", "ca55_deny";
  };

  pinctrl: pinctrl@11030000 {
   compatible = "renesas,r9a08g045-pinctrl";
   reg = <0 0x11030000 0 0x10000>;
   gpio-controller;
   #gpio-cells = <2>;
   interrupt-controller;
   #interrupt-cells = <2>;
   interrupt-parent = <&irqc>;
   gpio-ranges = <&pinctrl 0 0 152>;
   clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
   power-domains = <&cpg>;
   resets = <&cpg R9A08G045_GPIO_RSTN>,
     <&cpg R9A08G045_GPIO_PORT_RESETN>,
     <&cpg R9A08G045_GPIO_SPARE_RESETN>;
  };

  irqc: interrupt-controller@11050000 {
   compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc";
   #interrupt-cells = <2>;
   #address-cells = <0>;
   interrupt-controller;
   reg = <0 0x11050000 0 0x10000>;
   interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "nmi",
       "irq0", "irq1", "irq2", "irq3",
       "irq4", "irq5", "irq6", "irq7",
       "tint0", "tint1", "tint2", "tint3",
       "tint4", "tint5", "tint6", "tint7",
       "tint8", "tint9", "tint10", "tint11",
       "tint12", "tint13", "tint14", "tint15",
       "tint16", "tint17", "tint18", "tint19",
       "tint20", "tint21", "tint22", "tint23",
       "tint24", "tint25", "tint26", "tint27",
       "tint28", "tint29", "tint30", "tint31",
       "bus-err", "ec7tie1-0", "ec7tie2-0",
       "ec7tiovf-0";
   clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
     <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
   clock-names = "clk", "pclk";
   power-domains = <&cpg>;
   resets = <&cpg R9A08G045_IA55_RESETN>;
  };

  dmac: dma-controller@11820000 {
   compatible = "renesas,r9a08g045-dmac",
         "renesas,rz-dmac";
   reg = <0 0x11820000 0 0x10000>,
         <0 0x11830000 0 0x10000>;
   interrupts = <GIC_SPI 111 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 112 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 119 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>;
   interrupt-names = "error",
       "ch0", "ch1", "ch2", "ch3",
       "ch4", "ch5", "ch6", "ch7",
       "ch8", "ch9", "ch10", "ch11",
       "ch12", "ch13", "ch14", "ch15";
   clocks = <&cpg CPG_MOD R9A08G045_DMAC_ACLK>,
     <&cpg CPG_MOD R9A08G045_DMAC_PCLK>;
   clock-names = "main", "register";
   power-domains = <&cpg>;
   resets = <&cpg R9A08G045_DMAC_ARESETN>,
     <&cpg R9A08G045_DMAC_RST_ASYNC>;
   reset-names = "arst", "rst_async";
   #dma-cells = <1>;
   dma-channels = <16>;
  };

  sdhi0: mmc@11c00000  {
   compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
   reg = <0x0 0x11c00000 0 0x10000>;
   interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
   clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>,
     <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>,
     <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>,
     <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
   clock-names = "core", "clkh", "cd", "aclk";
   resets = <&cpg R9A08G045_SDHI0_IXRST>;
   power-domains = <&cpg>;
   status = "disabled";
  };

  sdhi1: mmc@11c10000 {
   compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
   reg = <0x0 0x11c10000 0 0x10000>;
   interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
   clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>,
     <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>,
     <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>,
     <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
   clock-names = "core", "clkh", "cd", "aclk";
   resets = <&cpg R9A08G045_SDHI1_IXRST>;
   power-domains = <&cpg>;
   status = "disabled";
  };

  sdhi2: mmc@11c20000 {
   compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
   reg = <0x0 0x11c20000 0 0x10000>;
   interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
   clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>,
     <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>,
     <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>,
     <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
   clock-names = "core", "clkh", "cd", "aclk";
   resets = <&cpg R9A08G045_SDHI2_IXRST>;
   power-domains = <&cpg>;
   status = "disabled";
  };

  eth0: ethernet@11c30000 {
   compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
   reg = <0 0x11c30000 0 0x10000>;
   interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "mux", "fil", "arp_ns";
   phy-mode = "rgmii";
   clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
     <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
     <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
   clock-names = "axi", "chi", "refclk";
   resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
   power-domains = <&cpg>;
   #address-cells = <1>;
   #size-cells = <0>;
   status = "disabled";
  };

  eth1: ethernet@11c40000 {
   compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
   reg = <0 0x11c40000 0 0x10000>;
   interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "mux", "fil", "arp_ns";
   phy-mode = "rgmii";
   clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>,
     <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>,
     <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
   clock-names = "axi", "chi", "refclk";
   resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
   power-domains = <&cpg>;
   #address-cells = <1>;
   #size-cells = <0>;
   status = "disabled";
  };

  gic: interrupt-controller@12400000 {
   compatible = "arm,gic-v3";
   #interrupt-cells = <3>;
   #address-cells = <0>;
   interrupt-controller;
   reg = <0x0 0x12400000 0 0x20000>,
         <0x0 0x12440000 0 0x40000>;
   interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
  };

  wdt0: watchdog@12800800 {
   compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt";
   reg = <0 0x12800800 0 0x400>;
   clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>,
     <&cpg CPG_MOD R9A08G045_WDT0_CLK>;
   clock-names = "pclk", "oscclk";
   interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "wdt", "perrout";
   resets = <&cpg R9A08G045_WDT0_PRESETN>;
   power-domains = <&cpg>;
   status = "disabled";
  };
 };

 timer {
  compatible = "arm,armv8-timer";
  interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
          <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
          <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
          <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
          <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
  interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
      "hyp-virt";
 };

 vbattb_xtal: vbattb-xtal {
  compatible = "fixed-clock";
  #clock-cells = <0>;
  /* This value must be overridden by the board. */
  clock-frequency = <0>;
 };
};