Quelle  sc7280.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: BSD-3-Clause
/*
 * sc7280 SoC device tree source
 *
 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
 */
#include <dt-bindings/clock/qcom,camcc-sc7280.h>
#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,gpucc-sc7280.h>
#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-sc7280.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/reset/qcom,sdm845-aoss.h>
#include <dt-bindings/reset/qcom,sdm845-pdc.h>
#include <dt-bindings/soc/qcom,apr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,lpass.h>
#include <dt-bindings/sound/qcom,q6asm.h>
#include <dt-bindings/thermal/thermal.h>

/ {
 interrupt-parent = <&intc>;

 #address-cells = <2>;
 #size-cells = <2>;

 chosen { };

 aliases {
  i2c0 = &i2c0;
  i2c1 = &i2c1;
  i2c2 = &i2c2;
  i2c3 = &i2c3;
  i2c4 = &i2c4;
  i2c5 = &i2c5;
  i2c6 = &i2c6;
  i2c7 = &i2c7;
  i2c8 = &i2c8;
  i2c9 = &i2c9;
  i2c10 = &i2c10;
  i2c11 = &i2c11;
  i2c12 = &i2c12;
  i2c13 = &i2c13;
  i2c14 = &i2c14;
  i2c15 = &i2c15;
  mmc1 = &sdhc_1;
  mmc2 = &sdhc_2;
  spi0 = &spi0;
  spi1 = &spi1;
  spi2 = &spi2;
  spi3 = &spi3;
  spi4 = &spi4;
  spi5 = &spi5;
  spi6 = &spi6;
  spi7 = &spi7;
  spi8 = &spi8;
  spi9 = &spi9;
  spi10 = &spi10;
  spi11 = &spi11;
  spi12 = &spi12;
  spi13 = &spi13;
  spi14 = &spi14;
  spi15 = &spi15;
 };

 clocks {
  xo_board: xo-board {
   compatible = "fixed-clock";
   clock-frequency = <76800000>;
   #clock-cells = <0>;
  };

  sleep_clk: sleep-clk {
   compatible = "fixed-clock";
   clock-frequency = <32764>;
   #clock-cells = <0>;
  };
 };

 reserved-memory {
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  wlan_ce_mem: wlan-ce@4cd000 {
   no-map;
   reg = <0x0 0x004cd000 0x0 0x1000>;
  };

  hyp_mem: hyp@80000000 {
   reg = <0x0 0x80000000 0x0 0x600000>;
   no-map;
  };

  xbl_mem: xbl@80600000 {
   reg = <0x0 0x80600000 0x0 0x200000>;
   no-map;
  };

  aop_mem: aop@80800000 {
   reg = <0x0 0x80800000 0x0 0x60000>;
   no-map;
  };

  aop_cmd_db_mem: aop-cmd-db@80860000 {
   reg = <0x0 0x80860000 0x0 0x20000>;
   compatible = "qcom,cmd-db";
   no-map;
  };

  reserved_xbl_uefi_log: xbl-uefi-res@80880000 {
   reg = <0x0 0x80884000 0x0 0x10000>;
   no-map;
  };

  sec_apps_mem: sec-apps@808ff000 {
   reg = <0x0 0x808ff000 0x0 0x1000>;
   no-map;
  };

  smem_mem: smem@80900000 {
   reg = <0x0 0x80900000 0x0 0x200000>;
   no-map;
  };

  cpucp_mem: cpucp@80b00000 {
   no-map;
   reg = <0x0 0x80b00000 0x0 0x100000>;
  };

  wlan_fw_mem: wlan-fw@80c00000 {
   reg = <0x0 0x80c00000 0x0 0xc00000>;
   no-map;
  };

  adsp_mem: adsp@86700000 {
   reg = <0x0 0x86700000 0x0 0x2800000>;
   no-map;
  };

  video_mem: video@8b200000 {
   reg = <0x0 0x8b200000 0x0 0x500000>;
   no-map;
  };

  cdsp_mem: cdsp@88f00000 {
   reg = <0x0 0x88f00000 0x0 0x1e00000>;
   no-map;
  };

  ipa_fw_mem: ipa-fw@8b700000 {
   reg = <0 0x8b700000 0 0x10000>;
   no-map;
  };

  gpu_zap_mem: zap@8b71a000 {
   reg = <0 0x8b71a000 0 0x2000>;
   no-map;
  };

  mpss_mem: mpss@8b800000 {
   reg = <0x0 0x8b800000 0x0 0xf600000>;
   no-map;
  };

  wpss_mem: wpss@9ae00000 {
   reg = <0x0 0x9ae00000 0x0 0x1900000>;
   no-map;
  };

  rmtfs_mem: rmtfs@9c900000 {
   compatible = "qcom,rmtfs-mem";
   reg = <0x0 0x9c900000 0x0 0x280000>;
   no-map;

   qcom,client-id = <1>;
   qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>;
  };
 };

 cpus {
  #address-cells = <2>;
  #size-cells = <0>;

  cpu0: cpu@0 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x0>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   power-domains = <&cpu_pd0>;
   power-domain-names = "psci";
   next-level-cache = <&l2_0>;
   operating-points-v2 = <&cpu0_opp_table>;
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <100>;
   interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
     <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   #cooling-cells = <2>;
   l2_0: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
    l3_0: l3-cache {
     compatible = "cache";
     cache-level = <3>;
     cache-unified;
    };
   };
  };

  cpu1: cpu@100 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x100>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   power-domains = <&cpu_pd1>;
   power-domain-names = "psci";
   next-level-cache = <&l2_100>;
   operating-points-v2 = <&cpu0_opp_table>;
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <100>;
   interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
     <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   #cooling-cells = <2>;
   l2_100: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu2: cpu@200 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x200>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   power-domains = <&cpu_pd2>;
   power-domain-names = "psci";
   next-level-cache = <&l2_200>;
   operating-points-v2 = <&cpu0_opp_table>;
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <100>;
   interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
     <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   #cooling-cells = <2>;
   l2_200: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu3: cpu@300 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x300>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   power-domains = <&cpu_pd3>;
   power-domain-names = "psci";
   next-level-cache = <&l2_300>;
   operating-points-v2 = <&cpu0_opp_table>;
   capacity-dmips-mhz = <1024>;
   dynamic-power-coefficient = <100>;
   interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
     <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   #cooling-cells = <2>;
   l2_300: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu4: cpu@400 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x400>;
   clocks = <&cpufreq_hw 1>;
   enable-method = "psci";
   power-domains = <&cpu_pd4>;
   power-domain-names = "psci";
   next-level-cache = <&l2_400>;
   operating-points-v2 = <&cpu4_opp_table>;
   capacity-dmips-mhz = <1946>;
   dynamic-power-coefficient = <520>;
   interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
     <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
   qcom,freq-domain = <&cpufreq_hw 1>;
   #cooling-cells = <2>;
   l2_400: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu5: cpu@500 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x500>;
   clocks = <&cpufreq_hw 1>;
   enable-method = "psci";
   power-domains = <&cpu_pd5>;
   power-domain-names = "psci";
   next-level-cache = <&l2_500>;
   operating-points-v2 = <&cpu4_opp_table>;
   capacity-dmips-mhz = <1946>;
   dynamic-power-coefficient = <520>;
   interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
     <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
   qcom,freq-domain = <&cpufreq_hw 1>;
   #cooling-cells = <2>;
   l2_500: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu6: cpu@600 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x600>;
   clocks = <&cpufreq_hw 1>;
   enable-method = "psci";
   power-domains = <&cpu_pd6>;
   power-domain-names = "psci";
   next-level-cache = <&l2_600>;
   operating-points-v2 = <&cpu4_opp_table>;
   capacity-dmips-mhz = <1946>;
   dynamic-power-coefficient = <520>;
   interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
     <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
   qcom,freq-domain = <&cpufreq_hw 1>;
   #cooling-cells = <2>;
   l2_600: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu7: cpu@700 {
   device_type = "cpu";
   compatible = "qcom,kryo";
   reg = <0x0 0x700>;
   clocks = <&cpufreq_hw 2>;
   enable-method = "psci";
   power-domains = <&cpu_pd7>;
   power-domain-names = "psci";
   next-level-cache = <&l2_700>;
   operating-points-v2 = <&cpu7_opp_table>;
   capacity-dmips-mhz = <1985>;
   dynamic-power-coefficient = <552>;
   interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
     <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
   qcom,freq-domain = <&cpufreq_hw 2>;
   #cooling-cells = <2>;
   l2_700: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu-map {
   cluster0 {
    core0 {
     cpu = <&cpu0>;
    };

    core1 {
     cpu = <&cpu1>;
    };

    core2 {
     cpu = <&cpu2>;
    };

    core3 {
     cpu = <&cpu3>;
    };

    core4 {
     cpu = <&cpu4>;
    };

    core5 {
     cpu = <&cpu5>;
    };

    core6 {
     cpu = <&cpu6>;
    };

    core7 {
     cpu = <&cpu7>;
    };
   };
  };

  idle-states {
   entry-method = "psci";

   little_cpu_sleep_0: cpu-sleep-0-0 {
    compatible = "arm,idle-state";
    idle-state-name = "little-power-down";
    arm,psci-suspend-param = <0x40000003>;
    entry-latency-us = <549>;
    exit-latency-us = <901>;
    min-residency-us = <1774>;
    local-timer-stop;
   };

   little_cpu_sleep_1: cpu-sleep-0-1 {
    compatible = "arm,idle-state";
    idle-state-name = "little-rail-power-down";
    arm,psci-suspend-param = <0x40000004>;
    entry-latency-us = <702>;
    exit-latency-us = <915>;
    min-residency-us = <4001>;
    local-timer-stop;
   };

   big_cpu_sleep_0: cpu-sleep-1-0 {
    compatible = "arm,idle-state";
    idle-state-name = "big-power-down";
    arm,psci-suspend-param = <0x40000003>;
    entry-latency-us = <523>;
    exit-latency-us = <1244>;
    min-residency-us = <2207>;
    local-timer-stop;
   };

   big_cpu_sleep_1: cpu-sleep-1-1 {
    compatible = "arm,idle-state";
    idle-state-name = "big-rail-power-down";
    arm,psci-suspend-param = <0x40000004>;
    entry-latency-us = <526>;
    exit-latency-us = <1854>;
    min-residency-us = <5555>;
    local-timer-stop;
   };
  };

  domain_idle_states: domain-idle-states {
   cluster_sleep_apss_off: cluster-sleep-0 {
    compatible = "domain-idle-state";
    arm,psci-suspend-param = <0x41000044>;
    entry-latency-us = <2752>;
    exit-latency-us = <3048>;
    min-residency-us = <6118>;
   };

   cluster_sleep_cx_ret: cluster-sleep-1 {
    compatible = "domain-idle-state";
    arm,psci-suspend-param = <0x41001344>;
    entry-latency-us = <3263>;
    exit-latency-us = <4562>;
    min-residency-us = <8467>;
   };

   cluster_sleep_llcc_off: cluster-sleep-2 {
    compatible = "domain-idle-state";
    arm,psci-suspend-param = <0x4100b344>;
    entry-latency-us = <3638>;
    exit-latency-us = <6562>;
    min-residency-us = <9826>;
   };
  };
 };

 cpu0_opp_table: opp-table-cpu0 {
  compatible = "operating-points-v2";
  opp-shared;

  cpu0_opp_300mhz: opp-300000000 {
   opp-hz = /bits/ 64 <300000000>;
   opp-peak-kBps = <800000 9600000>;
  };

  cpu0_opp_691mhz: opp-691200000 {
   opp-hz = /bits/ 64 <691200000>;
   opp-peak-kBps = <800000 17817600>;
  };

  cpu0_opp_806mhz: opp-806400000 {
   opp-hz = /bits/ 64 <806400000>;
   opp-peak-kBps = <800000 20889600>;
  };

  cpu0_opp_941mhz: opp-940800000 {
   opp-hz = /bits/ 64 <940800000>;
   opp-peak-kBps = <1804000 24576000>;
  };

  cpu0_opp_1152mhz: opp-1152000000 {
   opp-hz = /bits/ 64 <1152000000>;
   opp-peak-kBps = <2188000 27033600>;
  };

  cpu0_opp_1325mhz: opp-1324800000 {
   opp-hz = /bits/ 64 <1324800000>;
   opp-peak-kBps = <2188000 33792000>;
  };

  cpu0_opp_1517mhz: opp-1516800000 {
   opp-hz = /bits/ 64 <1516800000>;
   opp-peak-kBps = <3072000 38092800>;
  };

  cpu0_opp_1651mhz: opp-1651200000 {
   opp-hz = /bits/ 64 <1651200000>;
   opp-peak-kBps = <3072000 41779200>;
  };

  cpu0_opp_1805mhz: opp-1804800000 {
   opp-hz = /bits/ 64 <1804800000>;
   opp-peak-kBps = <4068000 48537600>;
  };

  cpu0_opp_1958mhz: opp-1958400000 {
   opp-hz = /bits/ 64 <1958400000>;
   opp-peak-kBps = <4068000 48537600>;
  };

  cpu0_opp_2016mhz: opp-2016000000 {
   opp-hz = /bits/ 64 <2016000000>;
   opp-peak-kBps = <6220000 48537600>;
  };
 };

 cpu4_opp_table: opp-table-cpu4 {
  compatible = "operating-points-v2";
  opp-shared;

  cpu4_opp_691mhz: opp-691200000 {
   opp-hz = /bits/ 64 <691200000>;
   opp-peak-kBps = <1804000 9600000>;
  };

  cpu4_opp_941mhz: opp-940800000 {
   opp-hz = /bits/ 64 <940800000>;
   opp-peak-kBps = <2188000 17817600>;
  };

  cpu4_opp_1229mhz: opp-1228800000 {
   opp-hz = /bits/ 64 <1228800000>;
   opp-peak-kBps = <4068000 24576000>;
  };

  cpu4_opp_1344mhz: opp-1344000000 {
   opp-hz = /bits/ 64 <1344000000>;
   opp-peak-kBps = <4068000 24576000>;
  };

  cpu4_opp_1517mhz: opp-1516800000 {
   opp-hz = /bits/ 64 <1516800000>;
   opp-peak-kBps = <4068000 24576000>;
  };

  cpu4_opp_1651mhz: opp-1651200000 {
   opp-hz = /bits/ 64 <1651200000>;
   opp-peak-kBps = <6220000 38092800>;
  };

  cpu4_opp_1901mhz: opp-1900800000 {
   opp-hz = /bits/ 64 <1900800000>;
   opp-peak-kBps = <6220000 44851200>;
  };

  cpu4_opp_2054mhz: opp-2054400000 {
   opp-hz = /bits/ 64 <2054400000>;
   opp-peak-kBps = <6220000 44851200>;
  };

  cpu4_opp_2112mhz: opp-2112000000 {
   opp-hz = /bits/ 64 <2112000000>;
   opp-peak-kBps = <6220000 44851200>;
  };

  cpu4_opp_2131mhz: opp-2131200000 {
   opp-hz = /bits/ 64 <2131200000>;
   opp-peak-kBps = <6220000 44851200>;
  };

  cpu4_opp_2208mhz: opp-2208000000 {
   opp-hz = /bits/ 64 <2208000000>;
   opp-peak-kBps = <6220000 44851200>;
  };

  cpu4_opp_2400mhz: opp-2400000000 {
   opp-hz = /bits/ 64 <2400000000>;
   opp-peak-kBps = <8532000 48537600>;
  };

  cpu4_opp_2611mhz: opp-2611200000 {
   opp-hz = /bits/ 64 <2611200000>;
   opp-peak-kBps = <8532000 48537600>;
  };
 };

 cpu7_opp_table: opp-table-cpu7 {
  compatible = "operating-points-v2";
  opp-shared;

  cpu7_opp_806mhz: opp-806400000 {
   opp-hz = /bits/ 64 <806400000>;
   opp-peak-kBps = <1804000 9600000>;
  };

  cpu7_opp_1056mhz: opp-1056000000 {
   opp-hz = /bits/ 64 <1056000000>;
   opp-peak-kBps = <2188000 17817600>;
  };

  cpu7_opp_1325mhz: opp-1324800000 {
   opp-hz = /bits/ 64 <1324800000>;
   opp-peak-kBps = <4068000 24576000>;
  };

  cpu7_opp_1517mhz: opp-1516800000 {
   opp-hz = /bits/ 64 <1516800000>;
   opp-peak-kBps = <4068000 24576000>;
  };

  cpu7_opp_1766mhz: opp-1766400000 {
   opp-hz = /bits/ 64 <1766400000>;
   opp-peak-kBps = <6220000 38092800>;
  };

  cpu7_opp_1862mhz: opp-1862400000 {
   opp-hz = /bits/ 64 <1862400000>;
   opp-peak-kBps = <6220000 38092800>;
  };

  cpu7_opp_2035mhz: opp-2035200000 {
   opp-hz = /bits/ 64 <2035200000>;
   opp-peak-kBps = <6220000 38092800>;
  };

  cpu7_opp_2112mhz: opp-2112000000 {
   opp-hz = /bits/ 64 <2112000000>;
   opp-peak-kBps = <6220000 44851200>;
  };

  cpu7_opp_2208mhz: opp-2208000000 {
   opp-hz = /bits/ 64 <2208000000>;
   opp-peak-kBps = <6220000 44851200>;
  };

  cpu7_opp_2381mhz: opp-2380800000 {
   opp-hz = /bits/ 64 <2380800000>;
   opp-peak-kBps = <6832000 44851200>;
  };

  cpu7_opp_2400mhz: opp-2400000000 {
   opp-hz = /bits/ 64 <2400000000>;
   opp-peak-kBps = <8532000 48537600>;
  };

  cpu7_opp_2515mhz: opp-2515200000 {
   opp-hz = /bits/ 64 <2515200000>;
   opp-peak-kBps = <8532000 48537600>;
  };

  cpu7_opp_2707mhz: opp-2707200000 {
   opp-hz = /bits/ 64 <2707200000>;
   opp-peak-kBps = <8532000 48537600>;
  };

  cpu7_opp_3014mhz: opp-3014400000 {
   opp-hz = /bits/ 64 <3014400000>;
   opp-peak-kBps = <8532000 48537600>;
  };
 };

 memory@80000000 {
  device_type = "memory";
  /* We expect the bootloader to fill in the size */
  reg = <0 0x80000000 0 0>;
 };

 firmware {
  scm: scm {
   compatible = "qcom,scm-sc7280", "qcom,scm";
   qcom,dload-mode = <&tcsr_2 0x13000>;
  };
 };

 clk_virt: interconnect {
  compatible = "qcom,sc7280-clk-virt";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 smem {
  compatible = "qcom,smem";
  memory-region = <&smem_mem>;
  hwlocks = <&tcsr_mutex 3>;
 };

 smp2p-adsp {
  compatible = "qcom,smp2p";
  qcom,smem = <443>, <429>;
  interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
          IPCC_MPROC_SIGNAL_SMP2P
          IRQ_TYPE_EDGE_RISING>;
  mboxes = <&ipcc IPCC_CLIENT_LPASS
    IPCC_MPROC_SIGNAL_SMP2P>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <2>;

  adsp_smp2p_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  adsp_smp2p_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-cdsp {
  compatible = "qcom,smp2p";
  qcom,smem = <94>, <432>;
  interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
          IPCC_MPROC_SIGNAL_SMP2P
          IRQ_TYPE_EDGE_RISING>;
  mboxes = <&ipcc IPCC_CLIENT_CDSP
    IPCC_MPROC_SIGNAL_SMP2P>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <5>;

  cdsp_smp2p_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  cdsp_smp2p_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-mpss {
  compatible = "qcom,smp2p";
  qcom,smem = <435>, <428>;
  interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
          IPCC_MPROC_SIGNAL_SMP2P
          IRQ_TYPE_EDGE_RISING>;
  mboxes = <&ipcc IPCC_CLIENT_MPSS
    IPCC_MPROC_SIGNAL_SMP2P>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <1>;

  modem_smp2p_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  modem_smp2p_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  ipa_smp2p_out: ipa-ap-to-modem {
   qcom,entry-name = "ipa";
   #qcom,smem-state-cells = <1>;
  };

  ipa_smp2p_in: ipa-modem-to-ap {
   qcom,entry-name = "ipa";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-wpss {
  compatible = "qcom,smp2p";
  qcom,smem = <617>, <616>;
  interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
          IPCC_MPROC_SIGNAL_SMP2P
          IRQ_TYPE_EDGE_RISING>;
  mboxes = <&ipcc IPCC_CLIENT_WPSS
    IPCC_MPROC_SIGNAL_SMP2P>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <13>;

  wpss_smp2p_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  wpss_smp2p_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  wlan_smp2p_out: wlan-ap-to-wpss {
   qcom,entry-name = "wlan";
   #qcom,smem-state-cells = <1>;
  };

  wlan_smp2p_in: wlan-wpss-to-ap {
   qcom,entry-name = "wlan";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 pmu-a55 {
  compatible = "arm,cortex-a55-pmu";
  interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 };

 pmu-a78 {
  compatible = "arm,cortex-a78-pmu";
  interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 };

 psci {
  compatible = "arm,psci-1.0";
  method = "smc";

  cpu_pd0: power-domain-cpu0 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
  };

  cpu_pd1: power-domain-cpu1 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
  };

  cpu_pd2: power-domain-cpu2 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
  };

  cpu_pd3: power-domain-cpu3 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>;
  };

  cpu_pd4: power-domain-cpu4 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
  };

  cpu_pd5: power-domain-cpu5 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
  };

  cpu_pd6: power-domain-cpu6 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
  };

  cpu_pd7: power-domain-cpu7 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
  };

  cluster_pd: power-domain-cluster {
   #power-domain-cells = <0>;
   domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_cx_ret &cluster_sleep_llcc_off>;
  };
 };

 qspi_opp_table: opp-table-qspi {
  compatible = "operating-points-v2";

  opp-75000000 {
   opp-hz = /bits/ 64 <75000000>;
   required-opps = <&rpmhpd_opp_low_svs>;
  };

  opp-150000000 {
   opp-hz = /bits/ 64 <150000000>;
   required-opps = <&rpmhpd_opp_svs>;
  };

  opp-200000000 {
   opp-hz = /bits/ 64 <200000000>;
   required-opps = <&rpmhpd_opp_svs_l1>;
  };

  opp-300000000 {
   opp-hz = /bits/ 64 <300000000>;
   required-opps = <&rpmhpd_opp_nom>;
  };
 };

 qup_opp_table: opp-table-qup {
  compatible = "operating-points-v2";

  opp-75000000 {
   opp-hz = /bits/ 64 <75000000>;
   required-opps = <&rpmhpd_opp_low_svs>;
  };

  opp-100000000 {
   opp-hz = /bits/ 64 <100000000>;
   required-opps = <&rpmhpd_opp_svs>;
  };

  opp-128000000 {
   opp-hz = /bits/ 64 <128000000>;
   required-opps = <&rpmhpd_opp_nom>;
  };
 };

 soc: soc@0 {
  #address-cells = <2>;
  #size-cells = <2>;
  ranges = <0 0 0 0 0x10 0>;
  dma-ranges = <0 0 0 0 0x10 0>;
  compatible = "simple-bus";

  gcc: clock-controller@100000 {
   compatible = "qcom,gcc-sc7280";
   reg = <0 0x00100000 0 0x1f0000>;
   clocks = <&rpmhcc RPMH_CXO_CLK>,
     <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
     <0>, <&pcie1_phy>,
     <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>,
     <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
   clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
          "pcie_0_pipe_clk", "pcie_1_pipe_clk",
          "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
          "ufs_phy_tx_symbol_0_clk",
          "usb3_phy_wrapper_gcc_usb30_pipe_clk";
   #clock-cells = <1>;
   #reset-cells = <1>;
   #power-domain-cells = <1>;
   power-domains = <&rpmhpd SC7280_CX>;
  };

  ipcc: mailbox@408000 {
   compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
   reg = <0 0x00408000 0 0x1000>;
   interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-controller;
   #interrupt-cells = <3>;
   #mbox-cells = <2>;
  };

  qfprom: efuse@784000 {
   compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
   reg = <0 0x00784000 0 0xa20>,
         <0 0x00780000 0 0xa20>,
         <0 0x00782000 0 0x120>,
         <0 0x00786000 0 0x1fff>;
   clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
   clock-names = "core";
   power-domains = <&rpmhpd SC7280_MX>;
   #address-cells = <1>;
   #size-cells = <1>;

   gpu_speed_bin: gpu-speed-bin@1e9 {
    reg = <0x1e9 0x2>;
    bits = <5 8>;
   };
  };

  sdhc_1: mmc@7c4000 {
   compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
   pinctrl-names = "default", "sleep";
   pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
   pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
   status = "disabled";

   reg = <0 0x007c4000 0 0x1000>,
         <0 0x007c5000 0 0x1000>;
   reg-names = "hc", "cqhci";

   iommus = <&apps_smmu 0xc0 0x0>;
   interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "hc_irq", "pwr_irq";

   clocks = <&gcc GCC_SDCC1_AHB_CLK>,
     <&gcc GCC_SDCC1_APPS_CLK>,
     <&rpmhcc RPMH_CXO_CLK>;
   clock-names = "iface", "core", "xo";
   interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
     <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
   interconnect-names = "sdhc-ddr","cpu-sdhc";
   power-domains = <&rpmhpd SC7280_CX>;
   operating-points-v2 = <&sdhc1_opp_table>;

   bus-width = <8>;
   supports-cqe;
   dma-coherent;

   qcom,dll-config = <0x0007642c>;
   qcom,ddr-config = <0x80040868>;

   mmc-ddr-1_8v;
   mmc-hs200-1_8v;
   mmc-hs400-1_8v;
   mmc-hs400-enhanced-strobe;

   resets = <&gcc GCC_SDCC1_BCR>;

   sdhc1_opp_table: opp-table {
    compatible = "operating-points-v2";

    opp-100000000 {
     opp-hz = /bits/ 64 <100000000>;
     required-opps = <&rpmhpd_opp_low_svs>;
     opp-peak-kBps = <1800000 400000>;
     opp-avg-kBps = <100000 0>;
    };

    opp-384000000 {
     opp-hz = /bits/ 64 <384000000>;
     required-opps = <&rpmhpd_opp_nom>;
     opp-peak-kBps = <5400000 1600000>;
     opp-avg-kBps = <390000 0>;
    };
   };
  };

  gpi_dma0: dma-controller@900000 {
   #dma-cells = <3>;
   compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
   reg = <0 0x00900000 0 0x60000>;
   interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
   dma-channels = <12>;
   dma-channel-mask = <0x7f>;
   iommus = <&apps_smmu 0x0136 0x0>;
   status = "disabled";
  };

  qupv3_id_0: geniqup@9c0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0 0x009c0000 0 0x2000>;
   clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
     <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
   clock-names = "m-ahb", "s-ahb";
   #address-cells = <2>;
   #size-cells = <2>;
   ranges;
   iommus = <&apps_smmu 0x123 0x0>;
   status = "disabled";

   i2c0: i2c@980000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00980000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c0_data_clk>;
    interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7280_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
           <&gpi_dma0 1 0 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi0: spi@980000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00980000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
    interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
           <&gpi_dma0 1 0 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   uart0: serial@980000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00980000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
    interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c1: i2c@984000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00984000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c1_data_clk>;
    interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7280_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
           <&gpi_dma0 1 1 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi1: spi@984000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00984000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
    interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
           <&gpi_dma0 1 1 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   uart1: serial@984000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00984000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
    interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c2: i2c@988000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00988000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c2_data_clk>;
    interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7280_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
           <&gpi_dma0 1 2 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi2: spi@988000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00988000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
    interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
           <&gpi_dma0 1 2 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   uart2: serial@988000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00988000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
    interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c3: i2c@98c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x0098c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c3_data_clk>;
    interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7280_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
           <&gpi_dma0 1 3 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi3: spi@98c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x0098c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
    interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
           <&gpi_dma0 1 3 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   uart3: serial@98c000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x0098c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
    interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c4: i2c@990000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00990000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c4_data_clk>;
    interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7280_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
           <&gpi_dma0 1 4 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi4: spi@990000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00990000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
    interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
           <&gpi_dma0 1 4 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   uart4: serial@990000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00990000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
    interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c5: i2c@994000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00994000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c5_data_clk>;
    interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7280_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
           <&gpi_dma0 1 5 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi5: spi@994000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00994000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
    interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
           <&gpi_dma0 1 5 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   uart5: serial@994000 {
    compatible = "qcom,geni-debug-uart";
    reg = <0 0x00994000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>;
    interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c6: i2c@998000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00998000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c6_data_clk>;
    interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7280_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
           <&gpi_dma0 1 6 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi6: spi@998000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00998000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
    interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
           <&gpi_dma0 1 6 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   uart6: serial@998000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00998000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
    interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c7: i2c@99c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x0099c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c7_data_clk>;
    interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
      <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7280_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
           <&gpi_dma0 1 7 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi7: spi@99c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x0099c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
    interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
           <&gpi_dma0 1 7 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   uart7: serial@99c000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x0099c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
    interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };
  };

  gpi_dma1: dma-controller@a00000 {
   #dma-cells = <3>;
   compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
   reg = <0 0x00a00000 0 0x60000>;
   interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
   dma-channels = <12>;
   dma-channel-mask = <0x1e>;
   iommus = <&apps_smmu 0x56 0x0>;
   status = "disabled";
  };

  qupv3_id_1: geniqup@ac0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0 0x00ac0000 0 0x2000>;
   clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
     <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
   clock-names = "m-ahb", "s-ahb";
   #address-cells = <2>;
   #size-cells = <2>;
   ranges;
   iommus = <&apps_smmu 0x43 0x0>;
   status = "disabled";

   i2c8: i2c@a80000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a80000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c8_data_clk>;
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
      <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7280_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
           <&gpi_dma1 1 0 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi8: spi@a80000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a80000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
           <&gpi_dma1 1 0 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   uart8: serial@a80000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00a80000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c9: i2c@a84000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a84000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c9_data_clk>;
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
      <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7280_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
           <&gpi_dma1 1 1 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi9: spi@a84000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a84000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
           <&gpi_dma1 1 1 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   uart9: serial@a84000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00a84000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c10: i2c@a88000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a88000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c10_data_clk>;
    interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
      <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7280_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
           <&gpi_dma1 1 2 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi10: spi@a88000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a88000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
    interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
           <&gpi_dma1 1 2 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   uart10: serial@a88000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00a88000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
    interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c11: i2c@a8c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a8c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c11_data_clk>;
    interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
      <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7280_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
           <&gpi_dma1 1 3 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi11: spi@a8c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a8c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
    interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
           <&gpi_dma1 1 3 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   uart11: serial@a8c000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00a8c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
    interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c12: i2c@a90000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a90000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c12_data_clk>;
    interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
      <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7280_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
           <&gpi_dma1 1 4 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi12: spi@a90000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a90000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
    interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
           <&gpi_dma1 1 4 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   uart12: serial@a90000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00a90000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
    interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c13: i2c@a94000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a94000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c13_data_clk>;
    interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
      <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7280_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
           <&gpi_dma1 1 5 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi13: spi@a94000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a94000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
    interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
           <&gpi_dma1 1 5 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   uart13: serial@a94000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00a94000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
    interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c14: i2c@a98000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a98000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c14_data_clk>;
    interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
      <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7280_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
           <&gpi_dma1 1 6 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi14: spi@a98000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a98000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
    interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
           <&gpi_dma1 1 6 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   uart14: serial@a98000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00a98000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
    interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };

   i2c15: i2c@a9c000 {
    compatible = "qcom,geni-i2c";
    reg = <0 0x00a9c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c15_data_clk>;
    interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
      <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
    interconnect-names = "qup-core", "qup-config",
       "qup-memory";
    power-domains = <&rpmhpd SC7280_CX>;
    required-opps = <&rpmhpd_opp_low_svs>;
    dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
           <&gpi_dma1 1 7 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   spi15: spi@a9c000 {
    compatible = "qcom,geni-spi";
    reg = <0 0x00a9c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
    interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
           <&gpi_dma1 1 7 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    status = "disabled";
   };

   uart15: serial@a9c000 {
    compatible = "qcom,geni-uart";
    reg = <0 0x00a9c000 0 0x4000>;
    clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
    clock-names = "se";
    pinctrl-names = "default";
    pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
    interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
    power-domains = <&rpmhpd SC7280_CX>;
    operating-points-v2 = <&qup_opp_table>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
      <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
    interconnect-names = "qup-core", "qup-config";
    status = "disabled";
   };
  };

  rng: rng@10d3000 {
   compatible = "qcom,sc7280-trng", "qcom,trng";
   reg = <0 0x010d3000 0 0x1000>;
  };

  cnoc2: interconnect@1500000 {
   reg = <0 0x01500000 0 0x1000>;
   compatible = "qcom,sc7280-cnoc2";
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  cnoc3: interconnect@1502000 {
   reg = <0 0x01502000 0 0x1000>;
   compatible = "qcom,sc7280-cnoc3";
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  mc_virt: interconnect@1580000 {
   reg = <0 0x01580000 0 0x4>;
   compatible = "qcom,sc7280-mc-virt";
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  system_noc: interconnect@1680000 {
   reg = <0 0x01680000 0 0x15480>;
   compatible = "qcom,sc7280-system-noc";
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  aggre1_noc: interconnect@16e0000 {
   compatible = "qcom,sc7280-aggre1-noc";
   reg = <0 0x016e0000 0 0x1c080>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
   clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
     <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
  };

  aggre2_noc: interconnect@1700000 {
   reg = <0 0x01700000 0 0x2b080>;
   compatible = "qcom,sc7280-aggre2-noc";
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
   clocks = <&rpmhcc RPMH_IPA_CLK>;
  };

  mmss_noc: interconnect@1740000 {
   reg = <0 0x01740000 0 0x1e080>;
   compatible = "qcom,sc7280-mmss-noc";
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  wifi: wifi@17a10040 {
   compatible = "qcom,wcn6750-wifi";
   reg = <0 0x17a10040 0 0x0>;
   iommus = <&apps_smmu 0x1c00 0x1>;
   interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
         <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
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