Quelle  sar2130p.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2024, Linaro Limited
 */

#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sar2130p-gcc.h>
#include <dt-bindings/clock/qcom,sar2130p-gpucc.h>
#include <dt-bindings/clock/qcom,sm8550-dispcc.h>
#include <dt-bindings/clock/qcom,sm8550-tcsr.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sar2130p-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/thermal/thermal.h>

/ {
 interrupt-parent = <&intc>;

 #address-cells = <2>;
 #size-cells = <2>;

 chosen { };

 clocks {
  xo_board: xo-board {
   compatible = "fixed-clock";
   #clock-cells = <0>;
   clock-frequency = <19200000>;
  };

  sleep_clk: sleep-clk {
   compatible = "fixed-clock";
   #clock-cells = <0>;
   clock-frequency = <32764>;
  };
 };

 cpus {
  #address-cells = <2>;
  #size-cells = <0>;

  cpu0: cpu@0 {
   device_type = "cpu";
   compatible = "arm,cortex-a55";
   reg = <0x0 0x0>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   next-level-cache = <&l2_0>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   power-domains = <&cpu_pd0>;
   power-domain-names = "psci";
   #cooling-cells = <2>;

   l2_0: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;

    l3_0: l3-cache {
     compatible = "cache";
     cache-level = <3>;
     cache-unified;
    };
   };
  };

  cpu1: cpu@100 {
   device_type = "cpu";
   compatible = "arm,cortex-a55";
   reg = <0x0 0x100>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   next-level-cache = <&l2_100>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   power-domains = <&cpu_pd1>;
   power-domain-names = "psci";
   #cooling-cells = <2>;

   l2_100: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu2: cpu@200 {
   device_type = "cpu";
   compatible = "arm,cortex-a55";
   reg = <0x0 0x200>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   next-level-cache = <&l2_200>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   power-domains = <&cpu_pd2>;
   power-domain-names = "psci";
   #cooling-cells = <2>;

   l2_200: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu3: cpu@300 {
   device_type = "cpu";
   compatible = "arm,cortex-a55";
   reg = <0x0 0x300>;
   clocks = <&cpufreq_hw 0>;
   enable-method = "psci";
   next-level-cache = <&l2_300>;
   qcom,freq-domain = <&cpufreq_hw 0>;
   power-domains = <&cpu_pd3>;
   power-domain-names = "psci";
   #cooling-cells = <2>;

   l2_300: l2-cache {
    compatible = "cache";
    cache-level = <2>;
    cache-unified;
    next-level-cache = <&l3_0>;
   };
  };

  cpu-map {
   cluster0 {
    core0 {
     cpu = <&cpu0>;
    };

    core1 {
     cpu = <&cpu1>;
    };

    core2 {
     cpu = <&cpu2>;
    };

    core3 {
     cpu = <&cpu3>;
    };
   };
  };

  idle-states {
   entry-method = "psci";

   cpu_sleep_0: cpu-sleep-0-0 {
    compatible = "arm,idle-state";
    idle-state-name = "silver-power-collapse";
    arm,psci-suspend-param = <0x40000003>;
    entry-latency-us = <549>;
    exit-latency-us = <901>;
    min-residency-us = <1774>;
    local-timer-stop;
   };

   cpu_sleep_1: cpu-sleep-0-1 {
    compatible = "arm,idle-state";
    idle-state-name = "silver-rail-power-collapse";
    arm,psci-suspend-param = <0x40000004>;
    entry-latency-us = <702>;
    exit-latency-us = <915>;
    min-residency-us = <4001>;
    local-timer-stop;
   };
  };

  domain-idle-states {
   cluster_sleep_0: cluster-sleep-0 {
    compatible = "domain-idle-state";
    arm,psci-suspend-param = <0x41000044>;
    entry-latency-us = <2752>;
    exit-latency-us = <3048>;
    min-residency-us = <6118>;
   };

   cluster_sleep_1: cluster-sleep-1 {
    compatible = "domain-idle-state";
    arm,psci-suspend-param = <0x41002344>;
    entry-latency-us = <3263>;
    exit-latency-us = <4562>;
    min-residency-us = <8467>;
   };

   cluster_sleep_2: cluster-sleep-2 {
    compatible = "domain-idle-state";
    arm,psci-suspend-param = <0x4100c344>;
    entry-latency-us = <3638>;
    exit-latency-us = <6562>;
    min-residency-us = <9862>;
   };
  };
 };

 firmware {
  scm: scm {
   compatible = "qcom,scm-sar2130p", "qcom,scm";
   qcom,dload-mode = <&tcsr_mutex 0x13000>;
   interconnects = <&system_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
      &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
  };
 };

 clk_virt: interconnect-0 {
  compatible = "qcom,sar2130p-clk-virt";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 mc_virt: interconnect-1 {
  compatible = "qcom,sar2130p-mc-virt";
  #interconnect-cells = <2>;
  qcom,bcm-voters = <&apps_bcm_voter>;
 };

 memory@80000000 {
  device_type = "memory";
  /* We expect the bootloader to fill in the size */
  reg = <0x0 0x80000000 0x0 0x0>;
 };

 pmu {
  compatible = "arm,armv8-pmuv3";
  interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 };

 psci {
  compatible = "arm,psci-1.0";
  method = "smc";

  cpu_pd0: power-domain-cpu0 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>;
  };

  cpu_pd1: power-domain-cpu1 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>;
  };

  cpu_pd2: power-domain-cpu2 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>;
  };

  cpu_pd3: power-domain-cpu3 {
   #power-domain-cells = <0>;
   power-domains = <&cluster_pd>;
   domain-idle-states = <&cpu_sleep_0>, <&cpu_sleep_1>;
  };

  cluster_pd: power-domain-cpu-cluster0 {
   #power-domain-cells = <0>;
   domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>, <&cluster_sleep_2>;
  };
 };

 reserved_memory: reserved-memory {
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  hyp_mem: hyp@80000000 {
   reg = <0x0 0x80000000 0x0 0x600000>;
   no-map;
  };

  xbl_dt_log_mem: xbl-dt-log@80600000 {
   reg = <0x0 0x80600000 0x0 0x40000>;
   no-map;
  };

  xbl_ramdump_mem: xbl-ramdump@80640000 {
   reg = <0x0 0x80640000 0x0 0x1c0000>;
   no-map;
  };

  aop_image_mem: aop-image@80800000 {
   reg = <0x0 0x80800000 0x0 0x60000>;
   no-map;
  };

  aop_cmd_db_mem: aop-cmd-db@80860000 {
   compatible = "qcom,cmd-db";
   reg = <0x0 0x80860000 0x0 0x20000>;
   no-map;
  };

  aop_config_mem: aop-config@80880000 {
   reg = <0x0 0x80880000 0x0 0x20000>;
   no-map;
  };

  tme_crash_dump_mem: tme-crash-dump@808a0000 {
   reg = <0x0 0x808a0000 0x0 0x40000>;
   no-map;
  };

  tme_log_mem: tme-log@808e0000 {
   reg = <0x0 0x808e0000 0x0 0x4000>;
   no-map;
  };

  uefi_log_mem: uefi-log@808e4000 {
   reg = <0x0 0x808e4000 0x0 0x10000>;
   no-map;
  };

  secdata_apss_mem: secdata-apss@808ff000 {
   reg = <0x0 0x808ff000 0x0 0x1000>;
   no-map;
  };

  smem: smem@80900000 {
   compatible = "qcom,smem";
   reg = <0x0 0x80900000 0x0 0x200000>;
   hwlocks = <&tcsr_mutex 3>;
   no-map;
  };

  cpucp_fw_mem: cpucp-fw@80b00000 {
   reg = <0x0 0x80b00000 0x0 0x100000>;
   no-map;
  };

  helios_ram_dump_mem: helios-ram-dump@80c00000 {
   reg = <0x0 0x80c00000 0x0 0xe00000>;
   no-map;
  };

  camera_mem: camera@84e00000 {
   reg = <0x0 0x84e00000 0x0 0x800000>;
   no-map;
  };

  video_mem: video@86f00000 {
   reg = <0x0 0x86f00000 0x0 0x500000>;
   no-map;
  };

  adsp_mem: adsp@87600000 {
   reg = <0x0 0x87600000 0x0 0x1e00000>;
   no-map;
  };

  cdsp_mem: cdsp@89400000 {
   reg = <0x0 0x89400000 0x0 0xf00000>;
   no-map;
  };

  ipa_fw_mem: ipa-fw@8a300000 {
   reg = <0x0 0x8a300000 0x0 0x10000>;
   no-map;
  };

  ipa_gsi_mem: ipa-gsi@8a3a0000 {
   reg = <0x0 0x8a310000 0x0 0xa000>;
   no-map;
  };

  gpu_micro_code_mem: gpu-micro-code@8a31a000 {
   reg = <0x0 0x8a31a000 0x0 0x2000>;
   no-map;
  };

  cvp_mem: cvp@8a400000 {
   reg = <0x0 0x8a400000 0x0 0x700000>;
   no-map;
  };

  xbl_sc_mem: xbl-sc@a6e00000 {
   no-map;
   reg = <0x0 0xa6e00000 0x0 0x40000>;
  };

  global_sync_mem: global-sync@a6f00000 {
   no-map;
   reg = <0x0 0xa6f00000 0x0 0x100000>;
  };

  tz_stat_mem: tz-stat@e8800000 {
   no-map;
   reg = <0x0 0xe8800000 0x0 0x100000>;
  };

  tags_mem: tags@e8900000 {
   no-map;
   reg = <0x0 0xe8900000 0x0 0x500000>;
  };

  qtee_mem: qtee@e8e00000 {
   no-map;
   reg = <0x0 0xe8e00000 0x0 0x500000>;
  };

  trusted_apps_mem: trusted-apps@e9300000 {
   no-map;
   reg = <0x0 0xe9300000 0x0 0xc00000>;
  };
 };

 smp2p-adsp {
  compatible = "qcom,smp2p";
  qcom,smem = <443>, <429>;
  interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
          IPCC_MPROC_SIGNAL_SMP2P
          IRQ_TYPE_EDGE_RISING>;
  mboxes = <&ipcc IPCC_CLIENT_LPASS
    IPCC_MPROC_SIGNAL_SMP2P>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <2>;

  smp2p_adsp_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  smp2p_adsp_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 smp2p-cdsp {
  compatible = "qcom,smp2p";
  qcom,smem = <94>, <432>;
  interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
          IPCC_MPROC_SIGNAL_SMP2P
          IRQ_TYPE_EDGE_RISING>;
  mboxes = <&ipcc IPCC_CLIENT_CDSP
    IPCC_MPROC_SIGNAL_SMP2P>;

  qcom,local-pid = <0>;
  qcom,remote-pid = <5>;

  smp2p_cdsp_out: master-kernel {
   qcom,entry-name = "master-kernel";
   #qcom,smem-state-cells = <1>;
  };

  smp2p_cdsp_in: slave-kernel {
   qcom,entry-name = "slave-kernel";
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };

 soc: soc@0 {
  compatible = "simple-bus";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges = <0 0 0 0 0x10 0>;
  dma-ranges = <0 0 0 0 0x10 0>;

  gcc: clock-controller@100000 {
   compatible = "qcom,sar2130p-gcc";
   reg = <0x0 0x00100000 0x0 0x1f4200>;
   #clock-cells = <1>;
   #reset-cells = <1>;
   #power-domain-cells = <1>;
   clocks = <&rpmhcc RPMH_CXO_CLK>,
     <&sleep_clk>,
     <&pcie0_phy>,
     <&pcie1_phy>,
     <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
  };

  sdhc_1: mmc@7c4000 {
   compatible = "qcom,sar2130p-sdhci", "qcom,sdhci-msm-v5";
   reg = <0x0 0x007c4000 0x0 0x1000>,
         <0x0 0x007c5000 0x0 0x1000>;
   reg-names = "hc", "cqhci";

   iommus = <&apps_smmu 0x160 0x0>;
   interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "hc_irq", "pwr_irq";

   clocks = <&gcc GCC_SDCC1_AHB_CLK>,
     <&gcc GCC_SDCC1_APPS_CLK>,
     <&rpmhcc RPMH_CXO_CLK>;
   clock-names = "iface", "core", "xo";
   interconnects = <&system_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
      &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
     <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
      &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ALWAYS>;
   interconnect-names = "sdhc-ddr","cpu-sdhc";
   power-domains = <&rpmhpd RPMHPD_CX>;
   operating-points-v2 = <&sdhc1_opp_table>;

   pinctrl-0 = <&sdc1_default>;
   pinctrl-1 = <&sdc1_sleep>;
   pinctrl-names = "default", "sleep";

   bus-width = <8>;
   non-removable;
   supports-cqe;

   mmc-ddr-1_8v;
   mmc-hs200-1_8v;
   mmc-hs400-1_8v;
   mmc-hs400-enhanced-strobe;

   status = "disabled";

   sdhc1_opp_table: opp-table {
    compatible = "operating-points-v2";

    opp-100000000 {
     opp-hz = /bits/ 64 <100000000>;
     required-opps = <&rpmhpd_opp_low_svs>;
     opp-peak-kBps = <500000 200000>;
     opp-avg-kBps = <104000 0>;
    };

    opp-384000000 {
     opp-hz = /bits/ 64 <384000000>;
     required-opps = <&rpmhpd_opp_nom>;
     opp-peak-kBps = <2500000 1000000>;
     opp-avg-kBps = <400000 0>;
    };
   };
  };

  gpi_dma0: dma-controller@900000 {
   compatible = "qcom,sar2130p-gpi-dma", "qcom,sm6350-gpi-dma";
   reg = <0x0 0x00900000 0x0 0x60000>;
   interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
   #dma-cells = <3>;
   dma-channels = <12>;
   dma-channel-mask = <0x7e>;
   iommus = <&apps_smmu 0x76 0x0>;

   status = "disabled";
  };

  qupv3_id_0: geniqup@9c0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0x0 0x009c0000 0x0 0x2000>;
   clock-names = "m-ahb", "s-ahb";
   clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
     <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
   iommus = <&apps_smmu 0x63 0x0>;
   interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
      &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
   interconnect-names = "qup-core";
   #address-cells = <2>;
   #size-cells = <2>;
   ranges;

   status = "disabled";

   i2c0: i2c@980000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x00980000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    pinctrl-0 = <&qup_i2c0_data_clk>;
    pinctrl-names = "default";
    interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
           <&gpi_dma0 1 0 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";

    status = "disabled";
   };

   spi0: spi@980000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x00980000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
    interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs0>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
           <&gpi_dma0 1 0 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    #address-cells = <1>;
    #size-cells = <0>;

    status = "disabled";
   };

   i2c1: i2c@984000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x00984000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
    pinctrl-0 = <&qup_i2c1_data_clk>;
    pinctrl-names = "default";
    interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
           <&gpi_dma0 1 1 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";

    status = "disabled";
   };

   spi1: spi@984000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x00984000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
    interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
           <&gpi_dma0 1 1 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    #address-cells = <1>;
    #size-cells = <0>;

    status = "disabled";
   };

   i2c2: i2c@988000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x00988000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
    pinctrl-0 = <&qup_i2c2_data_clk>;
    pinctrl-names = "default";
    interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
           <&gpi_dma0 1 2 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";

    status = "disabled";
   };

   spi2: spi@988000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x00988000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
    interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
           <&gpi_dma0 1 2 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    #address-cells = <1>;
    #size-cells = <0>;

    status = "disabled";
   };


   i2c3: i2c@98c000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x0098c000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
    pinctrl-0 = <&qup_i2c3_data_clk>;
    pinctrl-names = "default";
    interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
           <&gpi_dma0 1 3 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";

    status = "disabled";
   };

   spi3: spi@98c000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x0098c000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
    interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs0>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
           <&gpi_dma0 1 3 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    #address-cells = <1>;
    #size-cells = <0>;

    status = "disabled";
   };

   i2c4: i2c@990000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x00990000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
    pinctrl-0 = <&qup_i2c4_data_clk>;
    pinctrl-names = "default";
    interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
           <&gpi_dma0 1 4 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";

    status = "disabled";
   };

   spi4: spi@990000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x00990000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
    interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs0>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
           <&gpi_dma0 1 4 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    #address-cells = <1>;
    #size-cells = <0>;

    status = "disabled";
   };

   i2c5: i2c@994000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x00994000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
    pinctrl-0 = <&qup_i2c5_data_clk>;
    pinctrl-names = "default";
    interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
           <&gpi_dma0 1 5 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";

    status = "disabled";
   };

   spi5: spi@994000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x00994000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
    interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
           <&gpi_dma0 1 5 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    #address-cells = <1>;
    #size-cells = <0>;

    status = "disabled";
   };
  };

  gpi_dma1: dma-controller@a00000 {
   compatible = "qcom,sar2130p-gpi-dma", "qcom,sm6350-gpi-dma";
   #dma-cells = <3>;
   reg = <0x0 0x00a00000 0x0 0x60000>;
   interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
   dma-channels = <12>;
   dma-channel-mask = <0x7e>;
   iommus = <&apps_smmu 0x16 0x0>;

   status = "disabled";
  };

  qupv3_id_1: geniqup@ac0000 {
   compatible = "qcom,geni-se-qup";
   reg = <0x0 0x00ac0000 0x0 0x6000>;
   clock-names = "m-ahb", "s-ahb";
   clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
     <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
   iommus = <&apps_smmu 0x3 0x0>;
   interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
      &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>;
   interconnect-names = "qup-core";
   #address-cells = <2>;
   #size-cells = <2>;
   ranges;

   status = "disabled";

   i2c6: i2c@a80000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x00a80000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
    pinctrl-0 = <&qup_i2c6_data_clk>;
    pinctrl-names = "default";
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
           <&gpi_dma1 1 0 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";

    status = "disabled";
   };

   spi6: spi@a80000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x00a80000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
           <&gpi_dma1 1 0 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    #address-cells = <1>;
    #size-cells = <0>;

    status = "disabled";
   };

   i2c7: i2c@a84000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x00a84000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
    pinctrl-0 = <&qup_i2c7_data_clk>;
    pinctrl-names = "default";
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
           <&gpi_dma1 1 1 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";

    status = "disabled";
   };

   spi7: spi@a84000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x00a84000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
           <&gpi_dma1 1 1 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    #address-cells = <1>;
    #size-cells = <0>;

    status = "disabled";
   };

   uart7: serial@a84000 {
    compatible = "qcom,geni-uart";
    reg = <0x0 0x00a84000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
    pinctrl-0 = <&qup_uart7_default>;
    pinctrl-names = "default";
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config";

    status = "disabled";
   };

   i2c8: i2c@a88000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x00a88000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
    pinctrl-0 = <&qup_i2c8_data_clk>;
    pinctrl-names = "default";
    interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
           <&gpi_dma1 1 2 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";

    status = "disabled";
   };

   spi8: spi@a88000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x00a88000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
    interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
           <&gpi_dma1 1 2 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    #address-cells = <1>;
    #size-cells = <0>;

    status = "disabled";
   };

   i2c9: i2c@a8c000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x00a8c000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
    pinctrl-0 = <&qup_i2c9_data_clk>;
    pinctrl-names = "default";
    interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
           <&gpi_dma1 1 3 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";

    status = "disabled";
   };

   spi9: spi@a8c000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x00a8c000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
    interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
           <&gpi_dma1 1 3 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    #address-cells = <1>;
    #size-cells = <0>;

    status = "disabled";
   };

   i2c10: i2c@a90000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x00a90000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
    pinctrl-0 = <&qup_i2c10_data_clk>;
    pinctrl-names = "default";
    interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
           <&gpi_dma1 1 4 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";

    status = "disabled";
   };

   spi10: spi@a90000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x00a90000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
    interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
           <&gpi_dma1 1 4 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    #address-cells = <1>;
    #size-cells = <0>;

    status = "disabled";
   };

   i2c11: i2c@a94000 {
    compatible = "qcom,geni-i2c";
    reg = <0x0 0x00a94000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
    pinctrl-0 = <&qup_i2c11_data_clk>;
    pinctrl-names = "default";
    interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
    #address-cells = <1>;
    #size-cells = <0>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
           <&gpi_dma1 1 5 QCOM_GPI_I2C>;
    dma-names = "tx", "rx";

    status = "disabled";
   };

   spi11: spi@a94000 {
    compatible = "qcom,geni-spi";
    reg = <0x0 0x00a94000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
    interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
    pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
    pinctrl-names = "default";
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_A2NOC_SNOC QCOM_ICC_TAG_ALWAYS
       &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
      <&system_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
       &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core", "qup-config", "qup-memory";
    dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
           <&gpi_dma1 1 5 QCOM_GPI_SPI>;
    dma-names = "tx", "rx";
    #address-cells = <1>;
    #size-cells = <0>;

    status = "disabled";
   };

   uart11: serial@a94000 {
    compatible = "qcom,geni-debug-uart";
    reg = <0x0 0x00a94000 0x0 0x4000>;
    clock-names = "se";
    clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
    pinctrl-0 = <&qup_uart11_default>;
    pinctrl-names = "default";
    interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
    interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
       &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
      <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
       &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
    interconnect-names = "qup-core",
           "qup-config";

    status = "disabled";
   };
  };

  config_noc: interconnect@1500000 {
   compatible = "qcom,sar2130p-config-noc";
   reg = <0x0 0x01500000 0x0 0x10>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  system_noc: interconnect@1680000 {
   compatible = "qcom,sar2130p-system-noc";
   reg = <0x0 0x01680000 0x0 0x29080>;
   clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  pcie_noc: interconnect@16c0000 {
   compatible = "qcom,sar2130p-pcie-anoc";
   reg = <0x0 0x016c0000 0x0 0xa080>;
   clocks = <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
     <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  mmss_noc: interconnect@1740000 {
   compatible = "qcom,sar2130p-mmss-noc";
   reg = <0x0 0x01740000 0x0 0x1f100>;
   #interconnect-cells = <2>;
   qcom,bcm-voters = <&apps_bcm_voter>;
  };

  pcie0: pcie@1c00000 {
   device_type = "pci";
   compatible = "qcom,sar2130p-pcie", "qcom,pcie-sm8550";
   reg = <0x0 0x01c00000 0x0 0x3000>,
         <0x0 0x60000000 0x0 0xf1d>,
         <0x0 0x60000f20 0x0 0xa8>,
         <0x0 0x60001000 0x0 0x1000>,
         <0x0 0x60100000 0x0 0x100000>,
         <0x0 0x01c0c000 0x0 0x1000>;
   reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
   #address-cells = <3>;
   #size-cells = <2>;
   ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
     <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
   bus-range = <0x00 0xff>;

   dma-coherent;

   linux,pci-domain = <0>;
   num-lanes = <2>;

   interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "msi0",
       "msi1",
       "msi2",
       "msi3",
       "msi4",
       "msi5",
       "msi6",
       "msi7",
       "global";
   #interrupt-cells = <1>;
   interrupt-map-mask = <0 0 0 0x7>;
   interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
     <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
     <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
     <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

   clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
     <&gcc GCC_DDRSS_PCIE_SF_CLK>,
     <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>;
   clock-names = "aux",
          "cfg",
          "bus_master",
          "bus_slave",
          "slave_q2a",
          "ddrss_sf_tbu",
          "noc_aggr";

   interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
      &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
     <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
      &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>;
   interconnect-names = "pcie-mem", "cpu-pcie";

   iommu-map = <0x0   &apps_smmu 0x1c00 0x1>,
        <0x100 &apps_smmu 0x1c01 0x1>;

   resets = <&gcc GCC_PCIE_0_BCR>;
   reset-names = "pci";

   power-domains = <&gcc PCIE_0_GDSC>;

   phys = <&pcie0_phy>;
   phy-names = "pciephy";

   status = "disabled";

   pcieport0: pcie@0 {
    device_type = "pci";
    reg = <0x0 0x0 0x0 0x0 0x0>;
    bus-range = <0x01 0xff>;

    #address-cells = <3>;
    #size-cells = <2>;
    ranges;
   };
  };

  pcie0_phy: phy@1c06000 {
   compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy";
   reg = <0x0 0x01c06000 0x0 0x2000>;

   clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
     <&tcsr TCSR_PCIE_0_CLKREF_EN>,
     <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
     <&gcc GCC_PCIE_0_PIPE_CLK>;
   clock-names = "aux", "cfg_ahb", "ref", "rchng",
          "pipe";

   resets = <&gcc GCC_PCIE_0_PHY_BCR>;
   reset-names = "phy";

   assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
   assigned-clock-rates = <100000000>;

   power-domains = <&gcc PCIE_0_PHY_GDSC>;

   #clock-cells = <0>;
   clock-output-names = "pcie0_pipe_clk";

   #phy-cells = <0>;

   status = "disabled";
  };

  pcie1: pcie@1c08000 {
   device_type = "pci";
   compatible = "qcom,sar2130p-pcie", "qcom,pcie-sm8550";
   reg = <0x0 0x01c08000 0x0 0x3000>,
         <0x0 0x40000000 0x0 0xf1d>,
         <0x0 0x40000f20 0x0 0xa8>,
         <0x0 0x40001000 0x0 0x1000>,
         <0x0 0x40100000 0x0 0x100000>,
         <0x0 0x01c0b000 0x0 0x1000>;
   reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
   #address-cells = <3>;
   #size-cells = <2>;
   ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
     <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
   bus-range = <0x00 0xff>;

   dma-coherent;

   linux,pci-domain = <1>;
   num-lanes = <2>;

   interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "msi0",
       "msi1",
       "msi2",
       "msi3",
       "msi4",
       "msi5",
       "msi6",
       "msi7",
       "global";
   #interrupt-cells = <1>;
   interrupt-map-mask = <0 0 0 0x7>;
   interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
     <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
     <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
     <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

   clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
     <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
     <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
     <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
     <&gcc GCC_DDRSS_PCIE_SF_CLK>,
     <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
     <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
     <&gcc GCC_QMIP_PCIE_AHB_CLK>;
   clock-names = "aux",
          "cfg",
          "bus_master",
          "bus_slave",
          "slave_q2a",
          "ddrss_sf_tbu",
          "noc_aggr",
          "cnoc_sf_axi",
          "qmip_pcie_ahb";

   assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
   assigned-clock-rates = <19200000>;

   interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS
      &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
     <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
      &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>;
   interconnect-names = "pcie-mem", "cpu-pcie";

   iommu-map = <0x0   &apps_smmu 0x1e00 0x1>,
        <0x100 &apps_smmu 0x1e01 0x1>;

   resets = <&gcc GCC_PCIE_1_BCR>,
    <&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
   reset-names = "pci", "link_down";

   power-domains = <&gcc PCIE_1_GDSC>;

   phys = <&pcie1_phy>;
   phy-names = "pciephy";

   status = "disabled";

   pcie@0 {
    device_type = "pci";
    reg = <0x0 0x0 0x0 0x0 0x0>;
    bus-range = <0x01 0xff>;

    #address-cells = <3>;
    #size-cells = <2>;
    ranges;
   };
  };

  pcie1_ep: pcie-ep@1c08000 {
   compatible = "qcom,sar2130p-pcie-ep";
   reg = <0x0 0x01c08000 0x0 0x3000>,
         <0x0 0x40000000 0x0 0xf1d>,
         <0x0 0x40000f20 0x0 0xa8>,
         <0x0 0x40001000 0x0 0x1000>,
         <0x0 0x40200000 0x0 0x1000000>,
         <0x0 0x01c0b000 0x0 0x1000>,
         <0x0 0x40002000 0x0 0x2000>;
   reg-names = "parf",
        "dbi",
        "elbi",
        "atu",
        "addr_space",
        "mmio",
        "dma";

   clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
     <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
     <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
     <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
     <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
     <&gcc GCC_DDRSS_PCIE_SF_CLK>,
     <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
     <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
     <&gcc GCC_QMIP_PCIE_AHB_CLK>;
   clock-names = "aux",
          "cfg",
          "bus_master",
          "bus_slave",
          "slave_q2a",
          "ddrss_sf_tbu",
          "aggre_noc_axi",
          "cnoc_sf_axi",
          "qmip_pcie_ahb";

   interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "global",
       "doorbell",
       "dma";

   interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS
      &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
     <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
      &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
   interconnect-names = "pcie-mem",
          "cpu-pcie";
   iommus = <&apps_smmu 0x1e00 0x1>;
   resets = <&gcc GCC_PCIE_1_BCR>;
   reset-names = "core";
   power-domains = <&gcc PCIE_1_GDSC>;
   phys = <&pcie1_phy>;
   phy-names = "pciephy";

   num-lanes = <2>;

   status = "disabled";
  };

  pcie1_phy: phy@1c0e000 {
   compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy";
   reg = <0x0 0x01c0e000 0x0 0x2000>;

   clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
     <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
     <&tcsr TCSR_PCIE_1_CLKREF_EN>,
     <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
     <&gcc GCC_PCIE_1_PIPE_CLK>;
   clock-names = "aux", "cfg_ahb", "ref", "rchng",
          "pipe";

   resets = <&gcc GCC_PCIE_1_PHY_BCR>;
   reset-names = "phy";

   assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
   assigned-clock-rates = <100000000>;

   power-domains = <&gcc PCIE_1_PHY_GDSC>;

   #clock-cells = <0>;
   clock-output-names = "pcie1_pipe_clk";

   #phy-cells = <0>;

   status = "disabled";
  };

  tcsr_mutex: hwlock@1f40000 {
   compatible = "qcom,tcsr-mutex";
   reg = <0x0 0x01f40000 0x0 0x20000>;

   #hwlock-cells = <1>;
  };

  tcsr: clock-controller@1fc0000 {
   compatible = "qcom,sar2130p-tcsr", "syscon";
   reg = <0x0 0x01fc0000 0x0 0x30000>;
   clocks = <&rpmhcc RPMH_CXO_CLK>;
   #clock-cells = <1>;
   #reset-cells = <1>;
  };

  remoteproc_adsp: remoteproc@3000000 {
   compatible = "qcom,sar2130p-adsp-pas";
   reg = <0x0 0x03000000 0x0 0x10000>;

   interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
           <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
           <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
           <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
           <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
   interrupt-names = "wdog", "fatal", "ready",
       "handover", "stop-ack";

   clocks = <&rpmhcc RPMH_CXO_CLK>;
   clock-names = "xo";

   power-domains = <&rpmhpd RPMHPD_LCX>,
     <&rpmhpd RPMHPD_LMX>;
   power-domain-names = "lcx", "lmx";

   memory-region = <&adsp_mem>;

   qcom,qmp = <&aoss_qmp>;

   qcom,smem-states = <&smp2p_adsp_out 0>;
   qcom,smem-state-names = "stop";

   status = "disabled";

   remoteproc_adsp_glink: glink-edge {
    interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
            IPCC_MPROC_SIGNAL_GLINK_QMP
            IRQ_TYPE_EDGE_RISING>;
    mboxes = <&ipcc IPCC_CLIENT_LPASS
      IPCC_MPROC_SIGNAL_GLINK_QMP>;

    label = "lpass";
    qcom,remote-pid = <2>;

    gpr {
     compatible = "qcom,gpr";
     qcom,glink-channels = "adsp_apps";
     qcom,domain = <GPR_DOMAIN_ID_ADSP>;
     qcom,intents = <512 20>;
     #address-cells = <1>;
     #size-cells = <0>;

     q6apm: service@1 {
      compatible = "qcom,q6apm";
      reg = <GPR_APM_MODULE_IID>;
      #sound-dai-cells = <0>;
      qcom,protection-domain = "avs/audio",
          "msm/adsp/audio_pd";

      q6apmdai: dais {
       compatible = "qcom,q6apm-dais";
       iommus = <&apps_smmu 0x1801 0x0>;
      };

      q6apmbedai: bedais {
       compatible = "qcom,q6apm-lpass-dais";
       #sound-dai-cells = <1>;
      };
     };

     q6prm: service@2 {
      compatible = "qcom,q6prm";
      reg = <GPR_PRM_MODULE_IID>;
      qcom,protection-domain = "avs/audio",
          "msm/adsp/audio_pd";

      q6prmcc: clock-controller {
       compatible = "qcom,q6prm-lpass-clocks";
       #clock-cells = <2>;
      };
     };
    };

    fastrpc {
     compatible = "qcom,fastrpc";
     qcom,glink-channels = "fastrpcglink-apps-dsp";
     label = "adsp";
     qcom,non-secure-domain;
     #address-cells = <1>;
     #size-cells = <0>;

     compute-cb@3 {
      compatible = "qcom,fastrpc-compute-cb";
      reg = <3>;
      iommus = <&apps_smmu 0x1803 0x0>;
     };

     compute-cb@4 {
      compatible = "qcom,fastrpc-compute-cb";
      reg = <4>;
      iommus = <&apps_smmu 0x1804 0x0>;
     };

     compute-cb@5 {
      compatible = "qcom,fastrpc-compute-cb";
      reg = <5>;
      iommus = <&apps_smmu 0x1805 0x0>;
     };

     compute-cb@6 {
      compatible = "qcom,fastrpc-compute-cb";
      reg = <6>;
      iommus = <&apps_smmu 0x1806 0x0>;
     };
    };
   };
  };

  gpu: gpu@3d00000 {
   compatible = "qcom,adreno-621.0", "qcom,adreno";
   reg = <0x0 0x03d00000 0x0 0x40000>,
         <0x0 0x03d9e000 0x0 0x2000>,
         <0x0 0x03d61000 0x0 0x800>;
   reg-names = "kgsl_3d0_reg_memory",
        "cx_mem",
        "cx_dbgc";

   interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;

   iommus = <&adreno_smmu 0 0x401>;

   operating-points-v2 = <&gpu_opp_table>;

   qcom,gmu = <&gmu>;

   nvmem-cells = <&gpu_speed_bin>;
   nvmem-cell-names = "speed_bin";
   #cooling-cells = <2>;

   status = "disabled";

   gpu_zap_shader: zap-shader {
    memory-region = <&gpu_micro_code_mem>;
   };

   gpu_opp_table: opp-table {
    compatible = "operating-points-v2";

    opp-843000000 {
     opp-hz = /bits/ 64 <843000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
     opp-supported-hw = <0x1>;
    };

    opp-780000000 {
     opp-hz = /bits/ 64 <780000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
     opp-supported-hw = <0x1>;
    };

    opp-644000000 {
     opp-hz = /bits/ 64 <644000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
     opp-supported-hw = <0x3>;
    };

    opp-570000000 {
     opp-hz = /bits/ 64 <570000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
     opp-supported-hw = <0x3>;
    };

    opp-450000000 {
     opp-hz = /bits/ 64 <450000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
     opp-supported-hw = <0x3>;
    };

    opp-320000000 {
     opp-hz = /bits/ 64 <320000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
     opp-supported-hw = <0x3>;
    };

    opp-235000000 {
     opp-hz = /bits/ 64 <235000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
     opp-supported-hw = <0x3>;
    };
   };
  };

  gmu: gmu@3d6a000 {
   compatible = "qcom,adreno-gmu-621.0", "qcom,adreno-gmu";
   reg = <0x0 0x03d6a000 0x0 0x35000>,
         <0x0 0x03de0000 0x0 0x10000>,
         <0x0 0x0b290000 0x0 0x10000>;
   reg-names = "gmu", "rscc", "gmu_pdc";

   interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "hfi", "gmu";

   clocks = <&gpucc GPU_CC_AHB_CLK>,
     <&gpucc GPU_CC_CX_GMU_CLK>,
     <&gpucc GPU_CC_CXO_CLK>,
     <&gcc GCC_DDRSS_GPU_AXI_CLK>,
     <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
     <&gpucc GPU_CC_HUB_CX_INT_CLK>;
   clock-names = "ahb",
          "gmu",
          "cxo",
          "axi",
          "memnoc",
          "hub";

   power-domains = <&gpucc GPU_CX_GDSC>,
     <&gpucc GPU_GX_GDSC>;
   power-domain-names = "cx",
          "gx";

   iommus = <&adreno_smmu 5 0x400>;

   qcom,qmp = <&aoss_qmp>;

   operating-points-v2 = <&gmu_opp_table>;

   gmu_opp_table: opp-table {
    compatible = "operating-points-v2";

    opp-220000000 {
     opp-hz = /bits/ 64 <220000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
    };

    opp-550000000 {
     opp-hz = /bits/ 64 <550000000>;
     opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
    };
   };
  };

  gpucc: clock-controller@3d90000 {
   compatible = "qcom,sar2130p-gpucc";
   reg = <0x0 0x03d90000 0x0 0xa000>;

   clocks = <&rpmhcc RPMH_CXO_CLK>,
     <&gcc GCC_GPU_GPLL0_CLK_SRC>,
     <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;

   #clock-cells = <1>;
   #reset-cells = <1>;
   #power-domain-cells = <1>;
  };

  adreno_smmu: iommu@3da0000 {
   compatible = "qcom,sar2130p-smmu-500", "qcom,adreno-smmu",
         "qcom,smmu-500", "arm,mmu-500";
   reg = <0x0 0x03da0000 0x0 0x10000>;
   #iommu-cells = <2>;
   #global-interrupts = <1>;
   interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;

   clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
     <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
     <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
     <&gpucc GPU_CC_AHB_CLK>;
   clock-names = "hlos",
          "bus",
          "iface",
          "ahb";
   power-domains = <&gpucc GPU_CX_GDSC>;
   dma-coherent;
  };

  usb_1_hsphy: phy@88e3000 {
   compatible = "qcom,sar2130p-snps-eusb2-phy",
         "qcom,sm8550-snps-eusb2-phy";
   reg = <0x0 0x088e3000 0x0 0x154>;
   #phy-cells = <0>;

   clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
   clock-names = "ref";

   resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

   status = "disabled";
  };

  usb_dp_qmpphy: phy@88e8000 {
   compatible = "qcom,sar2130p-qmp-usb3-dp-phy";
   reg = <0x0 0x088e8000 0x0 0x3000>;

   clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
     <&rpmhcc RPMH_CXO_CLK>,
     <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
     <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
   clock-names = "aux", "ref", "com_aux", "usb3_pipe";

   power-domains = <&gcc USB3_PHY_GDSC>;

   resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
     <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
   reset-names = "phy", "common";

   #clock-cells = <1>;
   #phy-cells = <1>;

   orientation-switch;

   status = "disabled";

   ports {
    #address-cells = <1>;
    #size-cells = <0>;

    port@0 {
     reg = <0>;

     usb_dp_qmpphy_out: endpoint {
     };
    };

    port@1 {
     reg = <1>;

     usb_dp_qmpphy_usb_ss_in: endpoint {
      remote-endpoint = <&usb_1_dwc3_ss>;
     };
    };

    port@2 {
     reg = <2>;

     usb_dp_qmpphy_dp_in: endpoint {
      remote-endpoint = <&mdss_dp0_out>;
     };
    };
   };
  };

  usb_1: usb@a6f8800 {
   compatible = "qcom,sar2130p-dwc3", "qcom,dwc3";
   reg = <0x0 0x0a6f8800 0x0 0x400>;
   #address-cells = <2>;
   #size-cells = <2>;
   ranges;

   clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
     <&gcc GCC_USB30_PRIM_MASTER_CLK>,
     <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
     <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
     <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
     <&tcsr TCSR_USB3_CLKREF_EN>;
   clock-names = "cfg_noc",
          "core",
          "iface",
          "sleep",
          "mock_utmi",
          "xo";

   assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
       <&gcc GCC_USB30_PRIM_MASTER_CLK>;
   assigned-clock-rates = <19200000>, <200000000>;

   interrupts-extended = <&intc GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
           <&intc GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
           <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
           <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
           <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "pwr_event",
       "hs_phy_irq",
       "dp_hs_phy_irq",
       "dm_hs_phy_irq",
       "ss_phy_irq";

   power-domains = <&gcc USB30_PRIM_GDSC>;
   required-opps = <&rpmhpd_opp_nom>;

   resets = <&gcc GCC_USB30_PRIM_BCR>;

   interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
      &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
     <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
      &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>;
   interconnect-names = "usb-ddr", "apps-usb";

   status = "disabled";

   usb_1_dwc3: usb@a600000 {
    compatible = "snps,dwc3";
    reg = <0x0 0x0a600000 0x0 0xcd00>;
    interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
    iommus = <&apps_smmu 0x20 0x0>;
    phys = <&usb_1_hsphy>,
           <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
    phy-names = "usb2-phy", "usb3-phy";

    snps,has-lpm-erratum;
    snps,hird-threshold = /bits/ 8 <0x0>;
    snps,is-utmi-l1-suspend;
    snps,dis-u1-entry-quirk;
    snps,dis-u2-entry-quirk;
    snps,dis_u2_susphy_quirk;
    snps,dis_u3_susphy_quirk;
    snps,parkmode-disable-ss-quirk;

    tx-fifo-resize;
    dma-coherent;
    usb-role-switch;

    ports {
     #address-cells = <1>;
     #size-cells = <0>;

     port@0 {
      reg = <0>;

      usb_1_dwc3_hs: endpoint {
      };
     };

     port@1 {
      reg = <1>;

      usb_1_dwc3_ss: endpoint {
       remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
      };
     };
    };
   };
  };

  mdss: display-subsystem@ae00000 {
   compatible = "qcom,sar2130p-mdss";
   reg = <0x0 0x0ae00000 0x0 0x1000>;
   reg-names = "mdss";

   interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-controller;
   #interrupt-cells = <1>;

   clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
     <&gcc GCC_DISP_AHB_CLK>,
     <&gcc GCC_DISP_HF_AXI_CLK>,
     <&dispcc DISP_CC_MDSS_MDP_CLK>;

   resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;

   power-domains = <&dispcc MDSS_GDSC>;

   interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ACTIVE_ONLY
      &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
     <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
      &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
   interconnect-names = "mdp0-mem", "cpu-cfg";

   iommus = <&apps_smmu 0x2000 0x402>;

   #address-cells = <2>;
   #size-cells = <2>;
   ranges;

   status = "disabled";

   mdss_mdp: display-controller@ae01000 {
    compatible = "qcom,sar2130p-dpu";
    reg = <0x0 0x0ae01000 0x0 0x8f000>,
          <0x0 0x0aeb0000 0x0 0x2008>;
    reg-names = "mdp",
         "vbif";

    interrupt-parent = <&mdss>;
    interrupts = <0>;

    clocks = <&gcc GCC_DISP_AHB_CLK>,
      <&gcc GCC_DISP_HF_AXI_CLK>,
      <&dispcc DISP_CC_MDSS_AHB_CLK>,
      <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
      <&dispcc DISP_CC_MDSS_MDP_CLK>,
      <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
    clock-names = "bus",
           "nrt_bus",
           "iface",
           "lut",
           "core",
           "vsync";

    power-domains = <&rpmhpd RPMHPD_MMCX>;

    assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
    assigned-clock-rates = <19200000>;

    operating-points-v2 = <&mdp_opp_table>;

    ports {
     #address-cells = <1>;
     #size-cells = <0>;

     port@0 {
      reg = <0>;

      dpu_intf1_out: endpoint {
       remote-endpoint = <&mdss_dsi0_in>;
      };
     };

     port@1 {
      reg = <1>;

      dpu_intf2_out: endpoint {
       remote-endpoint = <&mdss_dsi1_in>;
      };
     };

     port@2 {
      reg = <2>;

      dpu_intf0_out: endpoint {
       remote-endpoint = <&mdss_dp0_in>;
      };
     };
    };

    mdp_opp_table: opp-table {
     compatible = "operating-points-v2";

     opp-200000000 {
      opp-hz = /bits/ 64 <200000000>;
      required-opps = <&rpmhpd_opp_low_svs>;
     };

     opp-325000000 {
      opp-hz = /bits/ 64 <325000000>;
      required-opps = <&rpmhpd_opp_svs>;
     };

     opp-514000000 {
      opp-hz = /bits/ 64 <514000000>;
      required-opps = <&rpmhpd_opp_turbo>;
     };
    };
   };

   mdss_dp0: displayport-controller@ae90000 {
    compatible = "qcom,sar2130p-dp",
          "qcom,sm8350-dp";
    reg = <0x0 0xae90000 0x0 0x200>,
          <0x0 0xae90200 0x0 0x200>,
          <0x0 0xae90400 0x0 0xc00>,
          <0x0 0xae91000 0x0 0x400>,
          <0x0 0xae91400 0x0 0x400>;
    interrupt-parent = <&mdss>;
    interrupts = <12>;
    clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
      <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
      <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
      <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
      <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
    clock-names = "core_iface",
           "core_aux",
           "ctrl_link",
           "ctrl_link_iface",
           "stream_pixel";

    assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
        <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
    assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
        <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;

    phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
    phy-names = "dp";

    #sound-dai-cells = <0>;

    operating-points-v2 = <&dp_opp_table>;
    power-domains = <&rpmhpd RPMHPD_MMCX>;

    status = "disabled";

    ports {
     #address-cells = <1>;
     #size-cells = <0>;

     port@0 {
      reg = <0>;

      mdss_dp0_in: endpoint {
       remote-endpoint = <&dpu_intf0_out>;
      };
     };

     port@1 {
      reg = <1>;

      mdss_dp0_out: endpoint {
       remote-endpoint = <&usb_dp_qmpphy_dp_in>;
      };
     };
    };

    dp_opp_table: opp-table {
     compatible = "operating-points-v2";

     opp-162000000 {
      opp-hz = /bits/ 64 <162000000>;
      required-opps = <&rpmhpd_opp_low_svs_d1>;
     };

     opp-270000000 {
      opp-hz = /bits/ 64 <270000000>;
      required-opps = <&rpmhpd_opp_low_svs>;
     };

     opp-540000000 {
      opp-hz = /bits/ 64 <540000000>;
      required-opps = <&rpmhpd_opp_svs_l1>;
     };

     opp-810000000 {
      opp-hz = /bits/ 64 <810000000>;
      required-opps = <&rpmhpd_opp_nom>;
     };
    };
   };

   mdss_dsi0: dsi@ae94000 {
    compatible = "qcom,sar2130p-dsi-ctrl",
          "qcom,mdss-dsi-ctrl";
    reg = <0x0 0x0ae94000 0x0 0x400>;
    reg-names = "dsi_ctrl";

    interrupt-parent = <&mdss>;
    interrupts = <4>;

    clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
      <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
      <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
      <&dispcc DISP_CC_MDSS_ESC0_CLK>,
      <&dispcc DISP_CC_MDSS_AHB_CLK>,
      <&gcc GCC_DISP_HF_AXI_CLK>;
    clock-names = "byte",
           "byte_intf",
           "pixel",
           "core",
           "iface",
           "bus";

    power-domains = <&rpmhpd RPMHPD_MMCX>;

    assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
        <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
    assigned-clock-parents = <&mdss_dsi0_phy 0>,
        <&mdss_dsi0_phy 1>;

    operating-points-v2 = <&mdss_dsi_opp_table>;

    phys = <&mdss_dsi0_phy>;
    phy-names = "dsi";

    #address-cells = <1>;
    #size-cells = <0>;

    status = "disabled";

    ports {
     #address-cells = <1>;
     #size-cells = <0>;

     port@0 {
      reg = <0>;
      mdss_dsi0_in: endpoint {
       remote-endpoint = <&dpu_intf1_out>;
      };
     };

     port@1 {
      reg = <1>;
      mdss_dsi0_out: endpoint {
      };
     };
    };

    mdss_dsi_opp_table: opp-table {
     compatible = "operating-points-v2";

     opp-187500000 {
      opp-hz = /bits/ 64 <187500000>;
      required-opps = <&rpmhpd_opp_low_svs>;
     };

     opp-300000000 {
      opp-hz = /bits/ 64 <300000000>;
      required-opps = <&rpmhpd_opp_svs>;
     };

     opp-358000000 {
      opp-hz = /bits/ 64 <358000000>;
      required-opps = <&rpmhpd_opp_nom>;
     };
    };
   };

   mdss_dsi0_phy: phy@ae95000 {
    compatible = "qcom,sar2130p-dsi-phy-5nm";
    reg = <0x0 0x0ae95000 0x0 0x200>,
          <0x0 0x0ae95200 0x0 0x280>,
          <0x0 0x0ae95500 0x0 0x400>;
    reg-names = "dsi_phy",
         "dsi_phy_lane",
         "dsi_pll";

    clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
      <&rpmhcc RPMH_CXO_CLK>;
    clock-names = "iface", "ref";

    #clock-cells = <1>;
    #phy-cells = <0>;

    status = "disabled";
   };

   mdss_dsi1: dsi@ae96000 {
    compatible = "qcom,sar2130p-dsi-ctrl",
          "qcom,mdss-dsi-ctrl";
    reg = <0x0 0x0ae96000 0x0 0x400>;
    reg-names = "dsi_ctrl";

    interrupt-parent = <&mdss>;
    interrupts = <5>;

    clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
      <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
      <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
      <&dispcc DISP_CC_MDSS_ESC1_CLK>,
      <&dispcc DISP_CC_MDSS_AHB_CLK>,
      <&gcc GCC_DISP_HF_AXI_CLK>;
    clock-names = "byte",
           "byte_intf",
           "pixel",
           "core",
           "iface",
           "bus";

    power-domains = <&rpmhpd RPMHPD_MMCX>;

    assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
        <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
    assigned-clock-parents = <&mdss_dsi1_phy 0>,
        <&mdss_dsi1_phy 1>;

    operating-points-v2 = <&mdss_dsi_opp_table>;

    phys = <&mdss_dsi1_phy>;
    phy-names = "dsi";

    #address-cells = <1>;
    #size-cells = <0>;

    status = "disabled";

    ports {
     #address-cells = <1>;
     #size-cells = <0>;

     port@0 {
      reg = <0>;
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