Quelle  imx8mn-beacon-som.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright 2020 Compass Electronics Group, LLC
 */

#include "imx8mn-overdrive.dtsi"

/ {
 aliases {
  rtc0 = &rtc;
  rtc1 = &snvs_rtc;
  spi0 = &flexspi;
 };

 usdhc1_pwrseq: usdhc1_pwrseq {
  compatible = "mmc-pwrseq-simple";
  pinctrl-names = "default";
  pinctrl-0 = <&pinctrl_usdhc1_gpio>;
  reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
  clocks = <&osc_32k>;
  clock-names = "ext_clock";
  post-power-on-delay-ms = <80>;
 };

 memory@40000000 {
  device_type = "memory";
  reg = <0x0 0x40000000 0 0x80000000>;
 };
};

&A53_0 {
 cpu-supply = <&buck2_reg>;
};

&A53_1 {
 cpu-supply = <&buck2_reg>;
};

&A53_2 {
 cpu-supply = <&buck2_reg>;
};

&A53_3 {
 cpu-supply = <&buck2_reg>;
};

/* DDR controller is running LPDDR at 800MHz which requires 0.95V */
&a53_opp_table {
 opp-1200000000 {
  opp-microvolt = <950000>;
 };
};

&ddrc {
 operating-points-v2 = <&ddrc_opp_table>;

 ddrc_opp_table: opp-table {
  compatible = "operating-points-v2";

  opp-25000000 {
   opp-hz = /bits/ 64 <25000000>;
  };

  opp-100000000 {
   opp-hz = /bits/ 64 <100000000>;
  };

  opp-800000000 {
   opp-hz = /bits/ 64 <800000000>;
  };
 };
};

&fec1 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_fec1>;
 phy-mode = "rgmii-id";
 phy-handle = <ðphy0>;
 phy-supply = <&buck6_reg>;
 phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 fsl,magic-packet;
 status = "okay";

 mdio {
  #address-cells = <1>;
  #size-cells = <0>;

  ethphy0: ethernet-phy@0 {
   compatible = "ethernet-phy-ieee802.3-c22";
   reg = <0>;
   reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
   interrupt-parent = <&gpio1>;
   interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
  };
 };
};

&flexspi {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_flexspi>;
 status = "okay";

 flash@0 {
  reg = <0>;
  #address-cells = <1>;
  #size-cells = <1>;
  compatible = "jedec,spi-nor";
  spi-max-frequency = <80000000>;
  spi-tx-bus-width = <1>;
  spi-rx-bus-width = <4>;
 };
};

&i2c1 {
 clock-frequency = <400000>;
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_i2c1>;
 status = "okay";

 pmic@4b {
  compatible = "rohm,bd71847";
  reg = <0x4b>;
  pinctrl-names = "default";
  pinctrl-0 = <&pinctrl_pmic>;
  interrupt-parent = <&gpio1>;
  interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
  rohm,reset-snvs-powered;
  #clock-cells = <0>;
  clocks = <&osc_32k>;
  clock-output-names = "clk-32k-out";

  regulators {
   buck1_reg: BUCK1 {
    regulator-name = "buck1";
    regulator-min-microvolt = <700000>;
    regulator-max-microvolt = <1300000>;
    regulator-boot-on;
    regulator-always-on;
    regulator-ramp-delay = <1250>;
   };

   buck2_reg: BUCK2 {
    regulator-name = "buck2";
    regulator-min-microvolt = <700000>;
    regulator-max-microvolt = <1300000>;
    regulator-boot-on;
    regulator-always-on;
    regulator-ramp-delay = <1250>;
    rohm,dvs-run-voltage = <1000000>;
    rohm,dvs-idle-voltage = <900000>;
   };

   buck3_reg: BUCK3 {
    // BUCK5 in datasheet
    regulator-name = "buck3";
    regulator-min-microvolt = <700000>;
    regulator-max-microvolt = <1350000>;
    regulator-boot-on;
    regulator-always-on;
   };

   buck4_reg: BUCK4 {
    // BUCK6 in datasheet
    regulator-name = "buck4";
    regulator-min-microvolt = <3000000>;
    regulator-max-microvolt = <3300000>;
    regulator-boot-on;
    regulator-always-on;
   };

   buck5_reg: BUCK5 {
    // BUCK7 in datasheet
    regulator-name = "buck5";
    regulator-min-microvolt = <1605000>;
    regulator-max-microvolt = <1995000>;
    regulator-boot-on;
    regulator-always-on;
   };

   buck6_reg: BUCK6 {
    // BUCK8 in datasheet
    regulator-name = "buck6";
    regulator-min-microvolt = <800000>;
    regulator-max-microvolt = <1400000>;
    regulator-boot-on;
    regulator-always-on;
   };

   ldo1_reg: LDO1 {
    regulator-name = "ldo1";
    regulator-min-microvolt = <1600000>;
    regulator-max-microvolt = <3300000>;
    regulator-boot-on;
    regulator-always-on;
   };

   ldo2_reg: LDO2 {
    regulator-name = "ldo2";
    regulator-min-microvolt = <800000>;
    regulator-max-microvolt = <900000>;
    regulator-boot-on;
    regulator-always-on;
   };

   ldo3_reg: LDO3 {
    regulator-name = "ldo3";
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <3300000>;
    regulator-boot-on;
    regulator-always-on;
   };

   ldo4_reg: LDO4 {
    regulator-name = "ldo4";
    regulator-min-microvolt = <900000>;
    regulator-max-microvolt = <1800000>;
    regulator-boot-on;
    regulator-always-on;
   };

   ldo6_reg: LDO6 {
    regulator-name = "ldo6";
    regulator-min-microvolt = <900000>;
    regulator-max-microvolt = <1800000>;
    regulator-boot-on;
    regulator-always-on;
   };
  };
 };
};

&i2c3 {
 clock-frequency = <400000>;
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_i2c3>;
 status = "okay";

 eeprom@50 {
  compatible = "microchip,24c64", "atmel,24c64";
  pagesize = <32>;
  read-only; /* Manufacturing EEPROM programmed at factory */
  reg = <0x50>;
 };

 rtc: rtc@51 {
  compatible = "nxp,pcf85263";
  reg = <0x51>;
  pinctrl-names = "default";
  pinctrl-0 = <&pinctrl_rtc>;
  interrupt-parent = <&gpio1>;
  interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
  quartz-load-femtofarads = <12500>;
  wakeup-source;
 };
};

&uart1 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_uart1>;
 assigned-clocks = <&clk IMX8MN_CLK_UART1>;
 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
 uart-has-rtscts;
 status = "okay";

 bluetooth {
  compatible = "brcm,bcm43438-bt";
  shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
  host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
  device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
  clocks = <&osc_32k>;
  max-speed = <4000000>;
  clock-names = "extclk";
 };
};

&usdhc1 {
 #address-cells = <1>;
 #size-cells = <0>;
 pinctrl-names = "default", "state_100mhz", "state_200mhz";
 pinctrl-0 = <&pinctrl_usdhc1>;
 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 vmmc-supply = <&buck4_reg>;
 vqmmc-supply = <&buck5_reg>;
 bus-width = <4>;
 non-removable;
 cap-power-off-card;
 keep-power-in-suspend;
 mmc-pwrseq = <&usdhc1_pwrseq>;
 status = "okay";

 brcmf: wifi@1 {
  reg = <1>;
  compatible = "brcm,bcm4329-fmac";
  pinctrl-names = "default";
  pinctrl-0 = <&pinctrl_wlan>;
  interrupt-parent = <&gpio2>;
  interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
  interrupt-names = "host-wake";
 };
};

&usdhc3 {
 pinctrl-names = "default", "state_100mhz", "state_200mhz";
 pinctrl-0 = <&pinctrl_usdhc3>;
 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 assigned-clocks = <&clk IMX8MN_CLK_USDHC3>;
 assigned-clock-rates = <400000000>;
 bus-width = <8>;
 non-removable;
 status = "okay";
};

&wdog1 {
 pinctrl-names = "default";
 pinctrl-0 = <&pinctrl_wdog>;
 fsl,ext-reset-output;
 status = "okay";
};

&iomuxc {
 pinctrl_fec1: fec1grp {
  fsl,pins = <
   MX8MN_IOMUXC_ENET_MDC_ENET1_MDC  0x3
   MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
   MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
   MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
   MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
   MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
   MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
   MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
   MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
   MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
   MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
   MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
   MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
   MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
   MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10             0x146
   MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
  >;
 };

 pinctrl_i2c1: i2c1grp {
  fsl,pins = <
   MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL  0x400001c3
   MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA  0x400001c3
  >;
 };

 pinctrl_i2c3: i2c3grp {
  fsl,pins = <
   MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL  0x400001c3
   MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA  0x400001c3
  >;
 };

 pinctrl_flexspi: flexspigrp {
  fsl,pins = <
   MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
   MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
   MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
   MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
   MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
   MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
  >;
 };

 pinctrl_pmic: pmicirqgrp {
  fsl,pins = <
   MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3  0x141
  >;
 };

 pinctrl_rtc: rtcgrp {
  fsl,pins = <
   MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146
  >;
 };

 pinctrl_uart1: uart1grp {
  fsl,pins = <
   MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
   MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
   MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
   MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
   MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19
   MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19
   MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19
   MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141
  >;
 };

 pinctrl_usdhc1_gpio: usdhc1gpiogrp {
  fsl,pins = <
   MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
  >;
 };

 pinctrl_usdhc1: usdhc1grp {
  fsl,pins = <
   MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK  0x190
   MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD  0x1d0
   MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
   MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
   MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
   MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
  >;
 };

 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
  fsl,pins = <
   MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK  0x194
   MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD  0x1d4
   MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
   MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
   MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
   MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
  >;
 };

 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
  fsl,pins = <
   MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK  0x196
   MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD  0x1d6
   MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
   MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
   MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
   MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
  >;
 };

 pinctrl_usdhc3: usdhc3grp {
  fsl,pins = <
   MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK  0x190
   MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD  0x1d0
   MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0  0x1d0
   MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1  0x1d0
   MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2  0x1d0
   MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3  0x1d0
   MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4  0x1d0
   MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5  0x1d0
   MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6  0x1d0
   MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7  0x1d0
   MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE  0x190
  >;
 };

 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
  fsl,pins = <
   MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK  0x194
   MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD  0x1d4
   MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0  0x1d4
   MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1  0x1d4
   MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2  0x1d4
   MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3  0x1d4
   MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4  0x1d4
   MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5  0x1d4
   MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6  0x1d4
   MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7  0x1d4
   MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE  0x194
  >;
 };

 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
  fsl,pins = <
   MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK  0x196
   MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD  0x1d6
   MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0  0x1d6
   MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1  0x1d6
   MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2  0x1d6
   MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3  0x1d6
   MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4  0x1d6
   MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5  0x1d6
   MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6  0x1d6
   MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7  0x1d6
   MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE  0x196
  >;
 };

 pinctrl_wdog: wdoggrp {
  fsl,pins = <
   MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B  0xc6
  >;
 };

 pinctrl_wlan: wlangrp {
  fsl,pins = <
   MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9  0x111
  >;
 };
};