Quelle  imx8-ss-conn.dtsi   Sprache: unbekannt

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018-2019 NXP
 * Dong Aisheng <aisheng.dong@nxp.com>
 */

#include <dt-bindings/clock/imx8-lpcg.h>
#include <dt-bindings/firmware/imx/rsrc.h>

conn_axi_clk: clock-conn-axi {
 compatible = "fixed-clock";
 #clock-cells = <0>;
 clock-frequency = <333333333>;
 clock-output-names = "conn_axi_clk";
};

conn_ahb_clk: clock-conn-ahb {
 compatible = "fixed-clock";
 #clock-cells = <0>;
 clock-frequency = <166666666>;
 clock-output-names = "conn_ahb_clk";
};

conn_ipg_clk: clock-conn-ipg {
 compatible = "fixed-clock";
 #clock-cells = <0>;
 clock-frequency = <83333333>;
 clock-output-names = "conn_ipg_clk";
};

conn_bch_clk: clock-conn-bch {
 compatible = "fixed-clock";
 #clock-cells = <0>;
 clock-frequency = <400000000>;
 clock-output-names = "conn_bch_clk";
};

conn_subsys: bus@5b000000 {
 compatible = "simple-bus";
 #address-cells = <1>;
 #size-cells = <1>;
 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;

 usbotg1: usb@5b0d0000 {
  compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb";
  reg = <0x5b0d0000 0x200>;
  interrupt-parent = <&gic>;
  interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
  fsl,usbphy = <&usbphy1>;
  fsl,usbmisc = <&usbmisc1 0>;
  clocks = <&usb2_lpcg IMX_LPCG_CLK_6>;
  ahb-burst-config = <0x0>;
  tx-burst-size-dword = <0x10>;
  rx-burst-size-dword = <0x10>;
  power-domains = <&pd IMX_SC_R_USB_0>;
  status = "disabled";
 };

 usbmisc1: usbmisc@5b0d0200 {
  #index-cells = <1>;
  compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
  reg = <0x5b0d0200 0x200>;
 };

 usbphy1: usbphy@5b100000 {
  compatible = "fsl,imx7ulp-usbphy";
  reg = <0x5b100000 0x1000>;
  clocks = <&usb2_lpcg IMX_LPCG_CLK_7>;
  power-domains = <&pd IMX_SC_R_USB_0_PHY>;
  status = "disabled";
 };

 usdhc1: mmc@5b010000 {
  interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
  reg = <0x5b010000 0x10000>;
  clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
    <&sdhc0_lpcg IMX_LPCG_CLK_5>,
    <&sdhc0_lpcg IMX_LPCG_CLK_0>;
  clock-names = "ipg", "ahb", "per";
  power-domains = <&pd IMX_SC_R_SDHC_0>;
  status = "disabled";
 };

 usdhc2: mmc@5b020000 {
  interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
  reg = <0x5b020000 0x10000>;
  clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>,
    <&sdhc1_lpcg IMX_LPCG_CLK_5>,
    <&sdhc1_lpcg IMX_LPCG_CLK_0>;
  clock-names = "ipg", "ahb", "per";
  power-domains = <&pd IMX_SC_R_SDHC_1>;
  fsl,tuning-start-tap = <20>;
  fsl,tuning-step = <2>;
  status = "disabled";
 };

 usdhc3: mmc@5b030000 {
  interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
  reg = <0x5b030000 0x10000>;
  clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>,
    <&sdhc2_lpcg IMX_LPCG_CLK_5>,
    <&sdhc2_lpcg IMX_LPCG_CLK_0>;
  clock-names = "ipg", "ahb", "per";
  power-domains = <&pd IMX_SC_R_SDHC_2>;
  status = "disabled";
 };

 fec1: ethernet@5b040000 {
  reg = <0x5b040000 0x10000>;
  interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
        <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
        <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
        <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
  clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
    <&enet0_lpcg IMX_LPCG_CLK_2>,
    <&enet0_lpcg IMX_LPCG_CLK_3>,
    <&enet0_lpcg IMX_LPCG_CLK_0>;
  clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
  assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
      <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
  assigned-clock-rates = <250000000>, <125000000>;
  fsl,num-tx-queues = <3>;
  fsl,num-rx-queues = <3>;
  power-domains = <&pd IMX_SC_R_ENET_0>;
  status = "disabled";
 };

 fec2: ethernet@5b050000 {
  reg = <0x5b050000 0x10000>;
  interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
    <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
    <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
    <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
  clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
    <&enet1_lpcg IMX_LPCG_CLK_2>,
    <&enet1_lpcg IMX_LPCG_CLK_3>,
    <&enet1_lpcg IMX_LPCG_CLK_0>;
  clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
  assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
      <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
  assigned-clock-rates = <250000000>, <125000000>;
  fsl,num-tx-queues = <3>;
  fsl,num-rx-queues = <3>;
  power-domains = <&pd IMX_SC_R_ENET_1>;
  status = "disabled";
 };

 usbotg3: usb@5b110000 {
  compatible = "fsl,imx8qm-usb3";
  reg = <0x5b110000 0x10000>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges;
  clocks = <&usb3_lpcg IMX_LPCG_CLK_1>,
    <&usb3_lpcg IMX_LPCG_CLK_0>,
    <&usb3_lpcg IMX_LPCG_CLK_7>,
    <&usb3_lpcg IMX_LPCG_CLK_4>,
    <&usb3_lpcg IMX_LPCG_CLK_5>;
  clock-names = "lpm", "bus", "aclk", "ipg", "core";
  assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
  assigned-clock-rates = <250000000>;
  power-domains = <&pd IMX_SC_R_USB_2>;
  status = "disabled";

  usbotg3_cdns3: usb@5b120000 {
   compatible = "cdns,usb3";
   reg = <0x5b120000 0x10000>,   /* memory area for OTG/DRD registers */
         <0x5b130000 0x10000>,   /* memory area for HOST registers */
         <0x5b140000 0x10000>;   /* memory area for DEVICE registers */
   reg-names = "otg", "xhci", "dev";
   interrupt-parent = <&gic>;
   interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
         <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
   interrupt-names = "host", "peripheral", "otg", "wakeup";
   phys = <&usb3_phy>;
   phy-names = "cdns3,usb3-phy";
   cdns,on-chip-buff-size = /bits/ 16 <18>;
   status = "disabled";
  };
 };

 usb3_phy: usb-phy@5b160000 {
  compatible = "nxp,salvo-phy";
  reg = <0x5b160000 0x40000>;
  clocks = <&usb3_lpcg IMX_LPCG_CLK_6>;
  clock-names = "salvo_phy_clk";
  power-domains = <&pd IMX_SC_R_USB_2_PHY>;
  #phy-cells = <0>;
  status = "disabled";
 };

 /* LPCG clocks */
 sdhc0_lpcg: clock-controller@5b200000 {
  compatible = "fsl,imx8qxp-lpcg";
  reg = <0x5b200000 0x10000>;
  #clock-cells = <1>;
  clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
    <&conn_ipg_clk>, <&conn_axi_clk>;
  clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
    <IMX_LPCG_CLK_5>;
  clock-output-names = "sdhc0_lpcg_per_clk",
         "sdhc0_lpcg_ipg_clk",
         "sdhc0_lpcg_ahb_clk";
  power-domains = <&pd IMX_SC_R_SDHC_0>;
 };

 sdhc1_lpcg: clock-controller@5b210000 {
  compatible = "fsl,imx8qxp-lpcg";
  reg = <0x5b210000 0x10000>;
  #clock-cells = <1>;
  clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
    <&conn_ipg_clk>, <&conn_axi_clk>;
  clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
    <IMX_LPCG_CLK_5>;
  clock-output-names = "sdhc1_lpcg_per_clk",
         "sdhc1_lpcg_ipg_clk",
         "sdhc1_lpcg_ahb_clk";
  power-domains = <&pd IMX_SC_R_SDHC_1>;
 };

 sdhc2_lpcg: clock-controller@5b220000 {
  compatible = "fsl,imx8qxp-lpcg";
  reg = <0x5b220000 0x10000>;
  #clock-cells = <1>;
  clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
    <&conn_ipg_clk>, <&conn_axi_clk>;
  clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
    <IMX_LPCG_CLK_5>;
  clock-output-names = "sdhc2_lpcg_per_clk",
         "sdhc2_lpcg_ipg_clk",
         "sdhc2_lpcg_ahb_clk";
  power-domains = <&pd IMX_SC_R_SDHC_2>;
 };

 enet0_lpcg: clock-controller@5b230000 {
  compatible = "fsl,imx8qxp-lpcg";
  reg = <0x5b230000 0x10000>;
  #clock-cells = <1>;
  clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
    <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
    <&conn_axi_clk>,
    <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
    <&conn_ipg_clk>,
    <&conn_ipg_clk>;
  clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
    <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
    <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
  clock-output-names = "enet0_lpcg_timer_clk",
         "enet0_lpcg_txc_sampling_clk",
         "enet0_lpcg_ahb_clk",
         "enet0_lpcg_rgmii_txc_clk",
         "enet0_lpcg_ipg_clk",
         "enet0_lpcg_ipg_s_clk";
  power-domains = <&pd IMX_SC_R_ENET_0>;
 };

 enet1_lpcg: clock-controller@5b240000 {
  compatible = "fsl,imx8qxp-lpcg";
  reg = <0x5b240000 0x10000>;
  #clock-cells = <1>;
  clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
    <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
    <&conn_axi_clk>,
    <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>,
    <&conn_ipg_clk>,
    <&conn_ipg_clk>;
  clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
    <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
    <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
  clock-output-names = "enet1_lpcg_timer_clk",
         "enet1_lpcg_txc_sampling_clk",
         "enet1_lpcg_ahb_clk",
         "enet1_lpcg_rgmii_txc_clk",
         "enet1_lpcg_ipg_clk",
         "enet1_lpcg_ipg_s_clk";
  power-domains = <&pd IMX_SC_R_ENET_1>;
 };

 usb2_lpcg: clock-controller@5b270000 {
  compatible = "fsl,imx8qxp-lpcg";
  reg = <0x5b270000 0x10000>;
  #clock-cells = <1>;
  clocks = <&conn_ahb_clk>, <&conn_ipg_clk>;
  clock-indices = <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
  clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";
  power-domains = <&pd IMX_SC_R_USB_0_PHY>;
 };

 usb3_lpcg: clock-controller@5b280000 {
  compatible = "fsl,imx8qxp-lpcg";
  reg = <0x5b280000 0x10000>;
  #clock-cells = <1>;
  clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
    <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
    <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
  clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>,
    <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>,
    <&conn_ipg_clk>,
    <&conn_ipg_clk>,
    <&conn_ipg_clk>,
    <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
  clock-output-names = "usb3_app_clk",
         "usb3_lpm_clk",
         "usb3_ipg_clk",
         "usb3_core_pclk",
         "usb3_phy_clk",
         "usb3_aclk";
  power-domains = <&pd IMX_SC_R_USB_2_PHY>;
 };

 rawnand_0_lpcg: clock-controller@5b290000 {
  compatible = "fsl,imx8qxp-lpcg";
  reg = <0x5b290000 0x4>;
  #clock-cells = <1>;
  clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_PER>,
    <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>,
    <&conn_axi_clk>,
    <&conn_axi_clk>;
  clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
    <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
  clock-output-names = "gpmi_bch",
         "gpmi_io",
         "gpmi_apb",
         "gpmi_bch_apb";
  power-domains = <&pd IMX_SC_R_NAND>;
 };

 rawnand_4_lpcg: clock-controller@5b290004 {
  compatible = "fsl,imx8qxp-lpcg";
  reg = <0x5b290004 0x10000>;
  #clock-cells = <1>;
  clocks = <&conn_axi_clk>;
  clock-indices = <IMX_LPCG_CLK_4>;
  clock-output-names = "apbhdma_hclk";
  power-domains = <&pd IMX_SC_R_NAND>;
 };

 dma_apbh: dma-controller@5b810000 {
  compatible = "fsl,imx8qxp-dma-apbh", "fsl,imx28-dma-apbh";
  reg = <0x5b810000 0x2000>;
  interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
        <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
        <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
        <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
  #dma-cells = <1>;
  dma-channels = <4>;
  clocks = <&rawnand_4_lpcg IMX_LPCG_CLK_0>;
  power-domains = <&pd IMX_SC_R_NAND>;
 };

 gpmi: nand-controller@5b812000 {
  compatible = "fsl,imx8qxp-gpmi-nand";
  reg = <0x5b812000 0x2000>, <0x5b814000 0x2000>;
  reg-names = "gpmi-nand", "bch";
  #address-cells = <1>;
  #size-cells = <0>;
  interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
  interrupt-names = "bch";
  clocks = <&rawnand_0_lpcg IMX_LPCG_CLK_1>,
    <&rawnand_0_lpcg IMX_LPCG_CLK_4>,
    <&rawnand_0_lpcg IMX_LPCG_CLK_0>,
    <&rawnand_0_lpcg IMX_LPCG_CLK_5>;
  clock-names = "gpmi_io", "gpmi_apb",
         "gpmi_bch", "gpmi_bch_apb";
  dmas = <&dma_apbh 0>;
  dma-names = "rx-tx";
  power-domains = <&pd IMX_SC_R_NAND>;
  assigned-clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>;
  assigned-clock-rates = <50000000>;
  status = "disabled";
 };
};