Quelle  qcom,nandc.yaml   Sprache: unbekannt

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/qcom,nandc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm NAND controller

maintainers:
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - qcom,sdx75-nand
          - const: qcom,sdx55-nand
      - items:
          - enum:
              - qcom,ipq806x-nand
              - qcom,ipq4019-nand
              - qcom,ipq6018-nand
              - qcom,ipq8074-nand
              - qcom,sdx55-nand

  reg:
    maxItems: 1

  clocks:
    items:
      - description: Core Clock
      - description: Always ON Clock

  clock-names:
    items:
      - const: core
      - const: aon

  qcom,cmd-crci:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Must contain the ADM command type CRCI block instance number specified for
      the NAND controller on the given platform

  qcom,data-crci:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      Must contain the ADM data type CRCI block instance number specified for
      the NAND controller on the given platform

patternProperties:
  "^nand@[a-f0-9]$":
    type: object
    $ref: raw-nand-chip.yaml
    properties:

      nand-bus-width:
        const: 8

      nand-ecc-strength:
        enum: [1, 4, 8]

      nand-ecc-step-size:
        enum:
          - 512

      qcom,boot-partitions:
        $ref: /schemas/types.yaml#/definitions/uint32-matrix
        items:
          items:
            - description: offset
            - description: size
        description:
          Boot partition use a different layout where the 4 bytes of spare
          data are not protected by ECC. Use this to declare these special
          partitions by defining first the offset and then the size.

          It's in the form of <offset1 size1 offset2 size2 offset3 ...>
          and should be declared in ascending order.

          Refer to the ipq8064 example on how to use this special binding.

    unevaluatedProperties: false

allOf:
  - $ref: nand-controller.yaml#

  - if:
      properties:
        compatible:
          contains:
            const: qcom,ipq806x-nand
    then:
      properties:
        dmas:
          items:
            - description: rxtx DMA channel

        dma-names:
          items:
            - const: rxtx

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,sdx75-nand

    then:
      properties:
        iommus:
          maxItems: 1

  - if:
      properties:
        compatible:
          contains:
            enum:
              - qcom,ipq4019-nand
              - qcom,ipq6018-nand
              - qcom,ipq8074-nand
              - qcom,sdx55-nand

    then:
      properties:
        dmas:
          items:
            - description: tx DMA channel
            - description: rx DMA channel
            - description: cmd DMA channel

        dma-names:
          items:
            - const: tx
            - const: rx
            - const: cmd

        qcom,cmd-crci: false
        qcom,data-crci: false

      patternProperties:
        "^nand@[a-f0-9]$":
          properties:
            qcom,boot-partitions: false

required:
  - compatible
  - reg
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
    nand-controller@1ac00000 {
        compatible = "qcom,ipq806x-nand";
        reg = <0x1ac00000 0x800>;

        clocks = <&gcc EBI2_CLK>,
                 <&gcc EBI2_AON_CLK>;
        clock-names = "core", "aon";

        dmas = <&adm_dma 3>;
        dma-names = "rxtx";
        qcom,cmd-crci = <15>;
        qcom,data-crci = <3>;

        #address-cells = <1>;
        #size-cells = <0>;

        nand@0 {
            reg = <0>;

            nand-ecc-strength = <4>;
            nand-bus-width = <8>;

            qcom,boot-partitions = <0x0 0x58a0000>;

            partitions {
                compatible = "fixed-partitions";
                #address-cells = <1>;
                #size-cells = <1>;

                partition@0 {
                    label = "boot-nand";
                    reg = <0 0x58a0000>;
                };

                partition@58a0000 {
                    label = "fs-nand";
                    reg = <0x58a0000 0x4000000>;
                };
            };
        };
    };

    #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
    nand-controller@79b0000 {
        compatible = "qcom,ipq4019-nand";
        reg = <0x79b0000 0x1000>;

        clocks = <&gcc GCC_QPIC_CLK>,
                 <&gcc GCC_QPIC_AHB_CLK>;
        clock-names = "core", "aon";

        dmas = <&qpicbam 0>,
               <&qpicbam 1>,
               <&qpicbam 2>;
        dma-names = "tx", "rx", "cmd";

        #address-cells = <1>;
        #size-cells = <0>;

        nand@0 {
            reg = <0>;
            nand-ecc-strength = <4>;
            nand-bus-width = <8>;

            partitions {
                compatible = "fixed-partitions";
                #address-cells = <1>;
                #size-cells = <1>;

                partition@0 {
                    label = "boot-nand";
                    reg = <0 0x58a0000>;
                };

                partition@58a0000 {
                    label = "fs-nand";
                    reg = <0x58a0000 0x4000000>;
                };
            };
        };
    };

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