Quelle assembler_s390.hpp
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/* * Copyright (c) 2016, 2022, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2016, 2022 SAP SE. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. * #ifndef CPU_S390_ASSEMBLER_S390_HPP#define CPU_S390_ASSEMBLER_S390_HPP#undef LUCY_DBG// Immediate is an abstraction to represent the various immediate // operands which exist on z/Architecture. Neither this class nor // instances hereof have an own state. It consists of methods only. class Immediate {public :static bool is_simm(int64_t x, unsigned int nbits) {// nbits < 2 --> false // nbits >= 64 --> true "Don't call, use statically known result." );const int64_t min = -(1L << (nbits-1));const int64_t maxplus1 = (1L << (nbits-1));return min <= x && x < maxplus1;static bool is_simm32(int64_t x) {return is_simm(x, 32);static bool is_simm20(int64_t x) {return is_simm(x, 20);static bool is_simm16(int64_t x) {return is_simm(x, 16);static bool is_simm8(int64_t x) {return is_simm(x, 8);// Test if x is within signed immediate range for nbits. static bool is_uimm(int64_t x, unsigned int nbits) {// nbits == 0 --> false // nbits >= 64 --> true "don't call, use statically known result" );const uint64_t xu = (unsigned long )x;const uint64_t maxplus1 = 1UL << nbits;return xu < maxplus1; // Unsigned comparison. Negative inputs appear to be very large. static bool is_uimm32(int64_t x) {return is_uimm(x, 32);static bool is_uimm16(int64_t x) {return is_uimm(x, 16);static bool is_uimm12(int64_t x) {return is_uimm(x, 12);static bool is_uimm8(int64_t x) {return is_uimm(x, 8);// Displacement is an abstraction to represent the various // displacements which exist with addresses on z/ArchiTecture. // Neither this class nor instances hereof have an own state. It // consists of methods only. class Displacement {public : // These tests are used outside the (Macro)Assembler world, e.g. in ad-file. static bool is_longDisp(int64_t x) { // Fits in a 20-bit displacement field. return Immediate::is_simm20(x);static bool is_shortDisp(int64_t x) { // Fits in a 12-bit displacement field. return Immediate::is_uimm12(x);static bool is_validDisp(int64_t x) { // Is a valid displacement, regardless of length constraints. return is_longDisp(x);// RelAddr is an abstraction to represent relative addresses in the // form they are used on z/Architecture for instructions which access // their operand with pc-relative addresses. Neither this class nor // instances hereof have an own state. It consists of methods only. class RelAddr {private : // No public use at all. Solely for (Macro)Assembler. static bool is_in_range_of_RelAddr(address target, address pc, bool shortForm) {// Guard against illegal branch targets, e.g. -1. Occurrences in // CompiledStaticCall and ad-file. Do not assert (it's a test // function!). Just return false in case of illegal operands. if ((((uint64_t)target) & 0x0001L) != 0) return false ;if ((((uint64_t)pc) & 0x0001L) != 0) return false ;if (shortForm) {return Immediate::is_simm((int64_t)(target-pc), 17); // Relative short addresses can reach +/- 2**16 bytes. else {return Immediate::is_simm((int64_t)(target-pc), 33); // Relative long addresses can reach +/- 2**32 bytes. static bool is_in_range_of_RelAddr16(address target, address pc) {return is_in_range_of_RelAddr(target, pc, true );static bool is_in_range_of_RelAddr16(ptrdiff_t distance) {return is_in_range_of_RelAddr((address)distance, 0, true );static bool is_in_range_of_RelAddr32(address target, address pc) {return is_in_range_of_RelAddr(target, pc, false );static bool is_in_range_of_RelAddr32(ptrdiff_t distance) {return is_in_range_of_RelAddr((address)distance, 0, false );static int pcrel_off(address target, address pc, bool shortForm) {"target of a relative address must be aligned" );"origin of a relative address must be aligned" );if ((target == NULL) || (target == pc)) {return 0; // Yet unknown branch destination. else {"target not within reach" );return (int )((target - pc)>>1);static int pcrel_off16(address target, address pc) {return pcrel_off(target, pc, true );static int pcrel_off16(ptrdiff_t distance) {return pcrel_off((address)distance, 0, true );static int pcrel_off32(address target, address pc) {return pcrel_off(target, pc, false );static int pcrel_off32(ptrdiff_t distance) {return pcrel_off((address)distance, 0, false );static ptrdiff_t inv_pcrel_off16(int offset) {return ((ptrdiff_t)offset)<<1;static ptrdiff_t inv_pcrel_off32(int offset) {return ((ptrdiff_t)offset)<<1;friend class Assembler;friend class MacroAssembler;friend class NativeGeneralJump;// Address is an abstraction used to represent a memory location // as passed to Z assembler instructions. // // Note: A register location is represented via a Register, not // via an address for efficiency & simplicity reasons. class Address {private :Register _base; // Base register. Register _index; // Index register // Constant displacement. public :Register base, Register index, intptr_t disp = 0) :Register base, intptr_t disp = 0) :Register base, RegisterOrConstant roc, intptr_t disp = 0) :if (roc.is_constant()) _disp += roc.as_constant(); else _index = roc.as_register();Register base, ByteSize disp) :Register base, Register index, ByteSize disp) :// Aborts if disp is a register and base and index are set already. const {this );if (disp.is_register()) {if (a._index == noreg) {else {"can not encode" ); a._base = disp.as_register();return a;// A call to this is generated by adlc for replacement variable $xxx$$Address. static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);bool is_same_address(Address a) const {return _base == a._base && _index == a._index && _disp == a._disp;// testers bool has_base() const { return _base != noreg; }bool has_index() const { return _index != noreg; }bool has_disp() const { return true ; } // There is no "invalid" value. bool is_disp12() const { return Immediate::is_uimm12(disp()); }bool is_disp20() const { return Immediate::is_simm20(disp()); }bool is_RSform() { return has_base() && !has_index() && is_disp12(); }bool is_RSYform() { return has_base() && !has_index() && is_disp20(); }bool is_RXform() { return has_base() && has_index() && is_disp12(); }bool is_RXYform() { return has_base() && has_index() && is_disp20(); }bool uses(Register r) { return _base == r || _index == r; };// accessors Register base() const { return _base; }Register baseOrR0() const { assert(_base != Z_R0, "" ); return _base == noreg ? Z_R0 : _base; }Register index() const { return _index; }Register indexOrR0() const { assert(_index != Z_R0, "" ); return _index == noreg ? Z_R0 : _index; }const { return _disp; }// Specific version for short displacement instructions. int disp12() const {"displacement out of range for uimm12" );return _disp;// Specific version for long displacement instructions. int disp20() const {"displacement out of range for simm20" );return _disp;const { return _disp; }friend class Assembler;class AddressLiteral {private :switch (rtype) {case relocInfo::external_word_type:return external_word_Relocation::spec(addr);case relocInfo::internal_word_type:return internal_word_Relocation::spec(addr);case relocInfo::opt_virtual_call_type:return opt_virtual_call_Relocation::spec();case relocInfo::static_call_type:return static_call_Relocation::spec();case relocInfo::runtime_call_w_cp_type:return runtime_call_w_cp_Relocation::spec();case relocInfo::none:return RelocationHolder();default :return RelocationHolder();protected :// creation public :const & rspec)// Some constructors to avoid casting at the call site. const & rspec)const & rspec)// Some constructors to avoid casting at the call site. bool * addr, relocInfo::relocType rtype = relocInfo::none)const bool * addr, relocInfo::relocType rtype = relocInfo::none)signed char * addr, relocInfo::relocType rtype = relocInfo::none)int * addr, relocInfo::relocType rtype = relocInfo::none)float * addr, relocInfo::relocType rtype = relocInfo::none)double * addr, relocInfo::relocType rtype = relocInfo::none)const { return (intptr_t) _address; }const relocInfo::relocType rtype() const { return _rspec.type(); }const RelocationHolder& rspec() const { return _rspec; }int offset) const {return offset == 0 ? _rspec : _rspec.plus(offset);// Convenience classes class ExternalAddress: public AddressLiteral {private :static relocInfo::relocType reloc_for_target(address target) {// Sometimes ExternalAddress is used for values which aren't // exactly addresses, like the card table base. // External_word_type can't be used for values in the first page // so just skip the reloc in that case. return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;public :// Argument is an abstraction used to represent an outgoing actual // argument or an incoming formal parameter, whether it resides in // memory or in a register, in a manner consistent with the // z/Architecture Application Binary Interface, or ABI. This is often // referred to as the native or C calling convention. class Argument {private :int _number;bool _is_in;public :enum {// Only 5 registers may contain integer parameters. // Can have up to 4 floating registers. // creation int number, bool is_in) : _number(number), _is_in(is_in) {}int number) : _number(number) {}int number() const { return _number; }const { return Argument(number() + 1); }// Locating register-based arguments: bool is_register() const { return _number < n_register_parameters; }// Locating Floating Point register-based arguments: bool is_float_register() const { return _number < n_float_register_parameters; }const {"must be a register argument" );return as_FloatRegister((number() *2) + 1);const {"must be a register argument" );return as_FloatRegister((number() *2));Register as_register() const {"must be a register argument" );return as_Register(number() + Z_ARG1->encoding());// debugging const char * name() const ;friend class Assembler;// The z/Architecture Assembler: Pure assembler doing NO optimizations // on the instruction level; i.e., what you write is what you get. The // Assembler is generating code into a CodeBuffer. class Assembler : public AbstractAssembler {protected :friend class AbstractAssembler;friend class AddressLiteral;// Code patchers need various routines like inv_wdisp(). friend class NativeInstruction;#ifndef COMPILER2friend class NativeGeneralJump;#endif friend class Relocation;public :// Addressing // address calculation #define LA_ZOPC (unsigned int )(0x41 << 24)#define LAY_ZOPC (unsigned long )(0xe3L << 40 | 0x71L)#define LARL_ZOPC (unsigned long )(0xc0L << 40 | 0x00L << 32)// Data Transfer // register to register transfer #define LR_ZOPC (unsigned int )(24 << 8)#define LBR_ZOPC (unsigned int )(0xb926 << 16)#define LHR_ZOPC (unsigned int )(0xb927 << 16)#define LGBR_ZOPC (unsigned int )(0xb906 << 16)#define LGHR_ZOPC (unsigned int )(0xb907 << 16)#define LGFR_ZOPC (unsigned int )(0xb914 << 16)#define LGR_ZOPC (unsigned int )(0xb904 << 16)#define LLHR_ZOPC (unsigned int )(0xb995 << 16)#define LLGCR_ZOPC (unsigned int )(0xb984 << 16)#define LLGHR_ZOPC (unsigned int )(0xb985 << 16)#define LLGTR_ZOPC (unsigned int )(185 << 24 | 23 << 16)#define LLGFR_ZOPC (unsigned int )(185 << 24 | 22 << 16)#define LTR_ZOPC (unsigned int )(18 << 8)#define LTGFR_ZOPC (unsigned int )(185 << 24 | 18 << 16)#define LTGR_ZOPC (unsigned int )(185 << 24 | 2 << 16)#define LER_ZOPC (unsigned int )(56 << 8)#define LEDBR_ZOPC (unsigned int )(179 << 24 | 68 << 16)#define LEXBR_ZOPC (unsigned int )(179 << 24 | 70 << 16)#define LDEBR_ZOPC (unsigned int )(179 << 24 | 4 << 16)#define LDR_ZOPC (unsigned int )(40 << 8)#define LDXBR_ZOPC (unsigned int )(179 << 24 | 69 << 16)#define LXEBR_ZOPC (unsigned int )(179 << 24 | 6 << 16)#define LXDBR_ZOPC (unsigned int )(179 << 24 | 5 << 16)#define LXR_ZOPC (unsigned int )(179 << 24 | 101 << 16)#define LTEBR_ZOPC (unsigned int )(179 << 24 | 2 << 16)#define LTDBR_ZOPC (unsigned int )(179 << 24 | 18 << 16)#define LTXBR_ZOPC (unsigned int )(179 << 24 | 66 << 16)#define LRVR_ZOPC (unsigned int )(0xb91f << 16)#define LRVGR_ZOPC (unsigned int )(0xb90f << 16)#define LDGR_ZOPC (unsigned int )(0xb3c1 << 16) // z10 #define LGDR_ZOPC (unsigned int )(0xb3cd << 16) // z10 #define LOCR_ZOPC (unsigned int )(0xb9f2 << 16) // z196 #define LOCGR_ZOPC (unsigned int )(0xb9e2 << 16) // z196 // immediate to register transfer #define IIHH_ZOPC (unsigned int )(165 << 24)#define IIHL_ZOPC (unsigned int )(165 << 24 | 1 << 16)#define IILH_ZOPC (unsigned int )(165 << 24 | 2 << 16)#define IILL_ZOPC (unsigned int )(165 << 24 | 3 << 16)#define IIHF_ZOPC (unsigned long )(0xc0L << 40 | 8L << 32)#define IILF_ZOPC (unsigned long )(0xc0L << 40 | 9L << 32)#define LLIHH_ZOPC (unsigned int )(165 << 24 | 12 << 16)#define LLIHL_ZOPC (unsigned int )(165 << 24 | 13 << 16)#define LLILH_ZOPC (unsigned int )(165 << 24 | 14 << 16)#define LLILL_ZOPC (unsigned int )(165 << 24 | 15 << 16)#define LLIHF_ZOPC (unsigned long )(0xc0L << 40 | 14L << 32)#define LLILF_ZOPC (unsigned long )(0xc0L << 40 | 15L << 32)#define LHI_ZOPC (unsigned int )(167 << 24 | 8 << 16)#define LGHI_ZOPC (unsigned int )(167 << 24 | 9 << 16)#define LGFI_ZOPC (unsigned long )(0xc0L << 40 | 1L << 32)#define LZER_ZOPC (unsigned int )(0xb374 << 16)#define LZDR_ZOPC (unsigned int )(0xb375 << 16)// LOAD: memory to register transfer #define LB_ZOPC (unsigned long )(227L << 40 | 118L)#define LH_ZOPC (unsigned int )(72 << 24)#define LHY_ZOPC (unsigned long )(227L << 40 | 120L)#define L_ZOPC (unsigned int )(88 << 24)#define LY_ZOPC (unsigned long )(227L << 40 | 88L)#define LT_ZOPC (unsigned long )(0xe3L << 40 | 0x12L)#define LGB_ZOPC (unsigned long )(227L << 40 | 119L)#define LGH_ZOPC (unsigned long )(227L << 40 | 21L)#define LGF_ZOPC (unsigned long )(227L << 40 | 20L)#define LG_ZOPC (unsigned long )(227L << 40 | 4L)#define LTG_ZOPC (unsigned long )(0xe3L << 40 | 0x02L)#define LTGF_ZOPC (unsigned long )(0xe3L << 40 | 0x32L)#define LLC_ZOPC (unsigned long )(0xe3L << 40 | 0x94L)#define LLH_ZOPC (unsigned long )(0xe3L << 40 | 0x95L)#define LLGT_ZOPC (unsigned long )(227L << 40 | 23L)#define LLGC_ZOPC (unsigned long )(227L << 40 | 144L)#define LLGH_ZOPC (unsigned long )(227L << 40 | 145L)#define LLGF_ZOPC (unsigned long )(227L << 40 | 22L)#define IC_ZOPC (unsigned int )(0x43 << 24)#define ICY_ZOPC (unsigned long )(0xe3L << 40 | 0x73L)#define ICM_ZOPC (unsigned int )(0xbf << 24)#define ICMY_ZOPC (unsigned long )(0xebL << 40 | 0x81L)#define ICMH_ZOPC (unsigned long )(0xebL << 40 | 0x80L)#define LRVH_ZOPC (unsigned long )(0xe3L << 40 | 0x1fL)#define LRV_ZOPC (unsigned long )(0xe3L << 40 | 0x1eL)#define LRVG_ZOPC (unsigned long )(0xe3L << 40 | 0x0fL)// LOAD relative: memory to register transfer #define LHRL_ZOPC (unsigned long )(0xc4L << 40 | 0x05L << 32) // z10 #define LRL_ZOPC (unsigned long )(0xc4L << 40 | 0x0dL << 32) // z10 #define LGHRL_ZOPC (unsigned long )(0xc4L << 40 | 0x04L << 32) // z10 #define LGFRL_ZOPC (unsigned long )(0xc4L << 40 | 0x0cL << 32) // z10 #define LGRL_ZOPC (unsigned long )(0xc4L << 40 | 0x08L << 32) // z10 #define LLHRL_ZOPC (unsigned long )(0xc4L << 40 | 0x02L << 32) // z10 #define LLGHRL_ZOPC (unsigned long )(0xc4L << 40 | 0x06L << 32) // z10 #define LLGFRL_ZOPC (unsigned long )(0xc4L << 40 | 0x0eL << 32) // z10 #define LOC_ZOPC (unsigned long )(0xebL << 40 | 0xf2L) // z196 #define LOCG_ZOPC (unsigned long )(0xebL << 40 | 0xe2L) // z196 // LOAD multiple registers at once #define LM_ZOPC (unsigned int )(0x98 << 24)#define LMY_ZOPC (unsigned long )(0xebL << 40 | 0x98L)#define LMG_ZOPC (unsigned long )(0xebL << 40 | 0x04L)#define LE_ZOPC (unsigned int )(0x78 << 24)#define LEY_ZOPC (unsigned long )(237L << 40 | 100L)#define LDEB_ZOPC (unsigned long )(237L << 40 | 4)#define LD_ZOPC (unsigned int )(0x68 << 24)#define LDY_ZOPC (unsigned long )(237L << 40 | 101L)#define LXEB_ZOPC (unsigned long )(237L << 40 | 6)#define LXDB_ZOPC (unsigned long )(237L << 40 | 5)// STORE: register to memory transfer #define STC_ZOPC (unsigned int )(0x42 << 24)#define STCY_ZOPC (unsigned long )(227L << 40 | 114L)#define STH_ZOPC (unsigned int )(64 << 24)#define STHY_ZOPC (unsigned long )(227L << 40 | 112L)#define ST_ZOPC (unsigned int )(80 << 24)#define STY_ZOPC (unsigned long )(227L << 40 | 80L)#define STG_ZOPC (unsigned long )(227L << 40 | 36L)#define STCM_ZOPC (unsigned long )(0xbeL << 24)#define STCMY_ZOPC (unsigned long )(0xebL << 40 | 0x2dL)#define STCMH_ZOPC (unsigned long )(0xebL << 40 | 0x2cL)// STORE relative: memory to register transfer #define STHRL_ZOPC (unsigned long )(0xc4L << 40 | 0x07L << 32) // z10 #define STRL_ZOPC (unsigned long )(0xc4L << 40 | 0x0fL << 32) // z10 #define STGRL_ZOPC (unsigned long )(0xc4L << 40 | 0x0bL << 32) // z10 #define STOC_ZOPC (unsigned long )(0xebL << 40 | 0xf3L) // z196 #define STOCG_ZOPC (unsigned long )(0xebL << 40 | 0xe3L) // z196 // STORE multiple registers at once #define STM_ZOPC (unsigned int )(0x90 << 24)#define STMY_ZOPC (unsigned long )(0xebL << 40 | 0x90L)#define STMG_ZOPC (unsigned long )(0xebL << 40 | 0x24L)#define STE_ZOPC (unsigned int )(0x70 << 24)#define STEY_ZOPC (unsigned long )(237L << 40 | 102L)#define STD_ZOPC (unsigned int )(0x60 << 24)#define STDY_ZOPC (unsigned long )(237L << 40 | 103L)// MOVE: immediate to memory transfer #define MVHHI_ZOPC (unsigned long )(0xe5L << 40 | 0x44L << 32) // z10 #define MVHI_ZOPC (unsigned long )(0xe5L << 40 | 0x4cL << 32) // z10 #define MVGHI_ZOPC (unsigned long )(0xe5L << 40 | 0x48L << 32) // z10 // ALU operations // Load Positive #define LPR_ZOPC (unsigned int )(16 << 8)#define LPGFR_ZOPC (unsigned int )(185 << 24 | 16 << 16)#define LPGR_ZOPC (unsigned int )(185 << 24)#define LPEBR_ZOPC (unsigned int )(179 << 24)#define LPDBR_ZOPC (unsigned int )(179 << 24 | 16 << 16)#define LPXBR_ZOPC (unsigned int )(179 << 24 | 64 << 16)// Load Negative #define LNR_ZOPC (unsigned int )(17 << 8)#define LNGFR_ZOPC (unsigned int )(185 << 24 | 17 << 16)#define LNGR_ZOPC (unsigned int )(185 << 24 | 1 << 16)#define LNEBR_ZOPC (unsigned int )(179 << 24 | 1 << 16)#define LNDBR_ZOPC (unsigned int )(179 << 24 | 17 << 16)#define LNXBR_ZOPC (unsigned int )(179 << 24 | 65 << 16)// Load Complement #define LCR_ZOPC (unsigned int )(19 << 8)#define LCGFR_ZOPC (unsigned int )(185 << 24 | 19 << 16)#define LCGR_ZOPC (unsigned int )(185 << 24 | 3 << 16)#define LCEBR_ZOPC (unsigned int )(179 << 24 | 3 << 16)#define LCDBR_ZOPC (unsigned int )(179 << 24 | 19 << 16)#define LCXBR_ZOPC (unsigned int )(179 << 24 | 67 << 16)// Add // RR, signed #define AR_ZOPC (unsigned int )(26 << 8)#define AGFR_ZOPC (unsigned int )(0xb9 << 24 | 0x18 << 16)#define AGR_ZOPC (unsigned int )(0xb9 << 24 | 0x08 << 16)// RRF, signed #define ARK_ZOPC (unsigned int )(0xb9 << 24 | 0x00f8 << 16)#define AGRK_ZOPC (unsigned int )(0xb9 << 24 | 0x00e8 << 16)// RI, signed #define AHI_ZOPC (unsigned int )(167 << 24 | 10 << 16)#define AFI_ZOPC (unsigned long )(0xc2L << 40 | 9L << 32)#define AGHI_ZOPC (unsigned int )(167 << 24 | 11 << 16)#define AGFI_ZOPC (unsigned long )(0xc2L << 40 | 8L << 32)// RIE, signed #define AHIK_ZOPC (unsigned long )(0xecL << 40 | 0x00d8L)#define AGHIK_ZOPC (unsigned long )(0xecL << 40 | 0x00d9L)#define AIH_ZOPC (unsigned long )(0xccL << 40 | 0x08L << 32)// RM, signed #define AHY_ZOPC (unsigned long )(227L << 40 | 122L)#define A_ZOPC (unsigned int )(90 << 24)#define AY_ZOPC (unsigned long )(227L << 40 | 90L)#define AGF_ZOPC (unsigned long )(227L << 40 | 24L)#define AG_ZOPC (unsigned long )(227L << 40 | 8L)// In-memory arithmetic (add signed, add logical with signed immediate). // MI, signed #define ASI_ZOPC (unsigned long )(0xebL << 40 | 0x6aL)#define AGSI_ZOPC (unsigned long )(0xebL << 40 | 0x7aL)// RR, Logical #define ALR_ZOPC (unsigned int )(30 << 8)#define ALGFR_ZOPC (unsigned int )(185 << 24 | 26 << 16)#define ALGR_ZOPC (unsigned int )(185 << 24 | 10 << 16)#define ALCGR_ZOPC (unsigned int )(185 << 24 | 136 << 16)// RRF, Logical #define ALRK_ZOPC (unsigned int )(0xb9 << 24 | 0x00fa << 16)#define ALGRK_ZOPC (unsigned int )(0xb9 << 24 | 0x00ea << 16)// RI, Logical #define ALFI_ZOPC (unsigned long )(0xc2L << 40 | 0x0bL << 32)#define ALGFI_ZOPC (unsigned long )(0xc2L << 40 | 0x0aL << 32)// RIE, Logical #define ALHSIK_ZOPC (unsigned long )(0xecL << 40 | 0x00daL)#define ALGHSIK_ZOPC (unsigned long )(0xecL << 40 | 0x00dbL)// RM, Logical #define AL_ZOPC (unsigned int )(0x5e << 24)#define ALY_ZOPC (unsigned long )(227L << 40 | 94L)#define ALGF_ZOPC (unsigned long )(227L << 40 | 26L)#define ALG_ZOPC (unsigned long )(227L << 40 | 10L)#define ALC_ZOPC (unsigned long )(227L << 40 | 152L)#define ALCG_ZOPC (unsigned long )(227L << 40 | 136L)// In-memory arithmetic (add signed, add logical with signed immediate). // MI, Logical #define ALSI_ZOPC (unsigned long )(0xebL << 40 | 0x6eL)#define ALGSI_ZOPC (unsigned long )(0xebL << 40 | 0x7eL)// RR, BFP #define AEBR_ZOPC (unsigned int )(179 << 24 | 10 << 16)#define ADBR_ZOPC (unsigned int )(179 << 24 | 26 << 16)#define AXBR_ZOPC (unsigned int )(179 << 24 | 74 << 16)// RM, BFP #define AEB_ZOPC (unsigned long )(237L << 40 | 10)#define ADB_ZOPC (unsigned long )(237L << 40 | 26)// Subtract // RR, signed #define SR_ZOPC (unsigned int )(27 << 8)#define SGFR_ZOPC (unsigned int )(185 << 24 | 25 << 16)#define SGR_ZOPC (unsigned int )(185 << 24 | 9 << 16)// RRF, signed #define SRK_ZOPC (unsigned int )(0xb9 << 24 | 0x00f9 << 16)#define SGRK_ZOPC (unsigned int )(0xb9 << 24 | 0x00e9 << 16)// RM, signed #define SH_ZOPC (unsigned int )(0x4b << 24)#define SHY_ZOPC (unsigned long )(227L << 40 | 123L)#define S_ZOPC (unsigned int )(0x5B << 24)#define SY_ZOPC (unsigned long )(227L << 40 | 91L)#define SGF_ZOPC (unsigned long )(227L << 40 | 25)#define SG_ZOPC (unsigned long )(227L << 40 | 9)// RR, Logical #define SLR_ZOPC (unsigned int )(31 << 8)#define SLGFR_ZOPC (unsigned int )(185 << 24 | 27 << 16)#define SLGR_ZOPC (unsigned int )(185 << 24 | 11 << 16)// RIL, Logical #define SLFI_ZOPC (unsigned long )(0xc2L << 40 | 0x05L << 32)#define SLGFI_ZOPC (unsigned long )(0xc2L << 40 | 0x04L << 32)// RRF, Logical #define SLRK_ZOPC (unsigned int )(0xb9 << 24 | 0x00fb << 16)#define SLGRK_ZOPC (unsigned int )(0xb9 << 24 | 0x00eb << 16)// RM, Logical #define SL_ZOPC (unsigned int )(0x5f << 24)#define SLY_ZOPC (unsigned long )(227L << 40 | 95L)#define SLGF_ZOPC (unsigned long )(227L << 40 | 27L)#define SLG_ZOPC (unsigned long )(227L << 40 | 11L)// RR, BFP #define SEBR_ZOPC (unsigned int )(179 << 24 | 11 << 16)#define SDBR_ZOPC (unsigned int )(179 << 24 | 27 << 16)#define SXBR_ZOPC (unsigned int )(179 << 24 | 75 << 16)// RM, BFP #define SEB_ZOPC (unsigned long )(237L << 40 | 11)#define SDB_ZOPC (unsigned long )(237L << 40 | 27)// Multiply // RR, signed #define MR_ZOPC (unsigned int )(28 << 8)#define MSR_ZOPC (unsigned int )(178 << 24 | 82 << 16)#define MSGFR_ZOPC (unsigned int )(185 << 24 | 28 << 16)#define MSGR_ZOPC (unsigned int )(185 << 24 | 12 << 16)// RI, signed #define MHI_ZOPC (unsigned int )(167 << 24 | 12 << 16)#define MGHI_ZOPC (unsigned int )(167 << 24 | 13 << 16)#define MSFI_ZOPC (unsigned long )(0xc2L << 40 | 0x01L << 32) // z10 #define MSGFI_ZOPC (unsigned long )(0xc2L << 40 | 0x00L << 32) // z10 // RM, signed #define M_ZOPC (unsigned int )(92 << 24)#define MS_ZOPC (unsigned int )(0x71 << 24)#define MHY_ZOPC (unsigned long )(0xe3L<< 40 | 0x7cL)#define MSY_ZOPC (unsigned long )(227L << 40 | 81L)#define MSGF_ZOPC (unsigned long )(227L << 40 | 28L)#define MSG_ZOPC (unsigned long )(227L << 40 | 12L)// RR, unsigned #define MLR_ZOPC (unsigned int )(185 << 24 | 150 << 16)#define MLGR_ZOPC (unsigned int )(185 << 24 | 134 << 16)// RM, unsigned #define ML_ZOPC (unsigned long )(227L << 40 | 150L)#define MLG_ZOPC (unsigned long )(227L << 40 | 134L)// RR, BFP #define MEEBR_ZOPC (unsigned int )(179 << 24 | 23 << 16)#define MDEBR_ZOPC (unsigned int )(179 << 24 | 12 << 16)#define MDBR_ZOPC (unsigned int )(179 << 24 | 28 << 16)#define MXDBR_ZOPC (unsigned int )(179 << 24 | 7 << 16)#define MXBR_ZOPC (unsigned int )(179 << 24 | 76 << 16)// RM, BFP #define MEEB_ZOPC (unsigned long )(237L << 40 | 23)#define MDEB_ZOPC (unsigned long )(237L << 40 | 12)#define MDB_ZOPC (unsigned long )(237L << 40 | 28)#define MXDB_ZOPC (unsigned long )(237L << 40 | 7)// Multiply-Add #define MAEBR_ZOPC (unsigned int )(179 << 24 | 14 << 16)#define MADBR_ZOPC (unsigned int )(179 << 24 | 30 << 16)#define MSEBR_ZOPC (unsigned int )(179 << 24 | 15 << 16)#define MSDBR_ZOPC (unsigned int )(179 << 24 | 31 << 16)#define MAEB_ZOPC (unsigned long )(237L << 40 | 14)#define MADB_ZOPC (unsigned long )(237L << 40 | 30)#define MSEB_ZOPC (unsigned long )(237L << 40 | 15)#define MSDB_ZOPC (unsigned long )(237L << 40 | 31)// Divide // RR, signed #define DSGFR_ZOPC (unsigned int )(0xb91d << 16)#define DSGR_ZOPC (unsigned int )(0xb90d << 16)// RM, signed #define D_ZOPC (unsigned int )(93 << 24)#define DSGF_ZOPC (unsigned long )(227L << 40 | 29L)#define DSG_ZOPC (unsigned long )(227L << 40 | 13L)// RR, unsigned #define DLR_ZOPC (unsigned int )(185 << 24 | 151 << 16)#define DLGR_ZOPC (unsigned int )(185 << 24 | 135 << 16)// RM, unsigned #define DL_ZOPC (unsigned long )(227L << 40 | 151L)#define DLG_ZOPC (unsigned long )(227L << 40 | 135L)// RR, BFP #define DEBR_ZOPC (unsigned int )(179 << 24 | 13 << 16)#define DDBR_ZOPC (unsigned int )(179 << 24 | 29 << 16)#define DXBR_ZOPC (unsigned int )(179 << 24 | 77 << 16)// RM, BFP #define DEB_ZOPC (unsigned long )(237L << 40 | 13)#define DDB_ZOPC (unsigned long )(237L << 40 | 29)// Square Root // RR, BFP #define SQEBR_ZOPC (unsigned int )(0xb314 << 16)#define SQDBR_ZOPC (unsigned int )(0xb315 << 16)#define SQXBR_ZOPC (unsigned int )(0xb316 << 16)// RM, BFP #define SQEB_ZOPC (unsigned long )(237L << 40 | 20)#define SQDB_ZOPC (unsigned long )(237L << 40 | 21)// Compare and Test // RR, signed #define CR_ZOPC (unsigned int )(25 << 8)#define CGFR_ZOPC (unsigned int )(185 << 24 | 48 << 16)#define CGR_ZOPC (unsigned int )(185 << 24 | 32 << 16)// RI, signed #define CHI_ZOPC (unsigned int )(167 << 24 | 14 << 16)#define CFI_ZOPC (unsigned long )(0xc2L << 40 | 0xdL << 32)#define CGHI_ZOPC (unsigned int )(167 << 24 | 15 << 16)#define CGFI_ZOPC (unsigned long )(0xc2L << 40 | 0xcL << 32)// RM, signed #define CH_ZOPC (unsigned int )(0x49 << 24)#define CHY_ZOPC (unsigned long )(227L << 40 | 121L)#define C_ZOPC (unsigned int )(0x59 << 24)#define CY_ZOPC (unsigned long )(227L << 40 | 89L)#define CGF_ZOPC (unsigned long )(227L << 40 | 48L)#define CG_ZOPC (unsigned long )(227L << 40 | 32L)// RR, unsigned #define CLR_ZOPC (unsigned int )(21 << 8)#define CLGFR_ZOPC (unsigned int )(185 << 24 | 49 << 16)#define CLGR_ZOPC (unsigned int )(185 << 24 | 33 << 16)// RIL, unsigned #define CLFI_ZOPC (unsigned long )(0xc2L << 40 | 0xfL << 32)#define CLGFI_ZOPC (unsigned long )(0xc2L << 40 | 0xeL << 32)// RM, unsigned #define CL_ZOPC (unsigned int )(0x55 << 24)#define CLY_ZOPC (unsigned long )(227L << 40 | 85L)#define CLGF_ZOPC (unsigned long )(227L << 40 | 49L)#define CLG_ZOPC (unsigned long )(227L << 40 | 33L)// RI, unsigned #define TMHH_ZOPC (unsigned int )(167 << 24 | 2 << 16)#define TMHL_ZOPC (unsigned int )(167 << 24 | 3 << 16)#define TMLH_ZOPC (unsigned int )(167 << 24)#define TMLL_ZOPC (unsigned int )(167 << 24 | 1 << 16)// RR, BFP #define CEBR_ZOPC (unsigned int )(179 << 24 | 9 << 16)#define CDBR_ZOPC (unsigned int )(179 << 24 | 25 << 16)#define CXBR_ZOPC (unsigned int )(179 << 24 | 73 << 16)// RM, BFP #define CEB_ZOPC (unsigned long )(237L << 40 | 9)#define CDB_ZOPC (unsigned long )(237L << 40 | 25)// Shift // arithmetic #define SLA_ZOPC (unsigned int )(0x8b << 24)#define SLAK_ZOPC (unsigned long )(0xebL << 40 | 0xddL)#define SLAG_ZOPC (unsigned long )(0xebL << 40 | 0x0bL)#define SRA_ZOPC (unsigned int )(0x8a << 24)#define SRAK_ZOPC (unsigned long )(0xebL << 40 | 0xdcL)#define SRAG_ZOPC (unsigned long )(0xebL << 40 | 0x0aL)// logical #define SLL_ZOPC (unsigned int )(0x89 << 24)#define SLLK_ZOPC (unsigned long )(0xebL << 40 | 0xdfL)#define SLLG_ZOPC (unsigned long )(0xebL << 40 | 0x0dL)#define SRL_ZOPC (unsigned int )(0x88 << 24)#define SRLK_ZOPC (unsigned long )(0xebL << 40 | 0xdeL)#define SRLG_ZOPC (unsigned long )(0xebL << 40 | 0x0cL)// Rotate, then AND/XOR/OR/insert // rotate #define RLL_ZOPC (unsigned long )(0xebL << 40 | 0x1dL) // z10 #define RLLG_ZOPC (unsigned long )(0xebL << 40 | 0x1cL) // z10 // rotate and {AND|XOR|OR|INS} #define RNSBG_ZOPC (unsigned long )(0xecL << 40 | 0x54L) // z196 #define RXSBG_ZOPC (unsigned long )(0xecL << 40 | 0x57L) // z196 #define ROSBG_ZOPC (unsigned long )(0xecL << 40 | 0x56L) // z196 #define RISBG_ZOPC (unsigned long )(0xecL << 40 | 0x55L) // z196 // AND // RR, signed #define NR_ZOPC (unsigned int )(20 << 8)#define NGR_ZOPC (unsigned int )(185 << 24 | 128 << 16)// RRF, signed #define NRK_ZOPC (unsigned int )(0xb9 << 24 | 0x00f4 << 16)#define NGRK_ZOPC (unsigned int )(0xb9 << 24 | 0x00e4 << 16)// RI, signed #define NIHH_ZOPC (unsigned int )(165 << 24 | 4 << 16)#define NIHL_ZOPC (unsigned int )(165 << 24 | 5 << 16)#define NILH_ZOPC (unsigned int )(165 << 24 | 6 << 16)#define NILL_ZOPC (unsigned int )(165 << 24 | 7 << 16)#define NIHF_ZOPC (unsigned long )(0xc0L << 40 | 10L << 32)#define NILF_ZOPC (unsigned long )(0xc0L << 40 | 11L << 32)// RM, signed #define N_ZOPC (unsigned int )(0x54 << 24)#define NY_ZOPC (unsigned long )(227L << 40 | 84L)#define NG_ZOPC (unsigned long )(227L << 40 | 128L)// OR // RR, signed #define OR_ZOPC (unsigned int )(22 << 8)#define OGR_ZOPC (unsigned int )(185 << 24 | 129 << 16)// RRF, signed #define ORK_ZOPC (unsigned int )(0xb9 << 24 | 0x00f6 << 16)#define OGRK_ZOPC (unsigned int )(0xb9 << 24 | 0x00e6 << 16)// RI, signed #define OIHH_ZOPC (unsigned int )(165 << 24 | 8 << 16)#define OIHL_ZOPC (unsigned int )(165 << 24 | 9 << 16)#define OILH_ZOPC (unsigned int )(165 << 24 | 10 << 16)#define OILL_ZOPC (unsigned int )(165 << 24 | 11 << 16)#define OIHF_ZOPC (unsigned long )(0xc0L << 40 | 12L << 32)#define OILF_ZOPC (unsigned long )(0xc0L << 40 | 13L << 32)// RM, signed #define O_ZOPC (unsigned int )(0x56 << 24)#define OY_ZOPC (unsigned long )(227L << 40 | 86L)#define OG_ZOPC (unsigned long )(227L << 40 | 129L)// XOR // RR, signed #define XR_ZOPC (unsigned int )(23 << 8)#define XGR_ZOPC (unsigned int )(185 << 24 | 130 << 16)// RRF, signed #define XRK_ZOPC (unsigned int )(0xb9 << 24 | 0x00f7 << 16)#define XGRK_ZOPC (unsigned int )(0xb9 << 24 | 0x00e7 << 16)// RI, signed #define XIHF_ZOPC (unsigned long )(0xc0L << 40 | 6L << 32)#define XILF_ZOPC (unsigned long )(0xc0L << 40 | 7L << 32)// RM, signed #define X_ZOPC (unsigned int )(0x57 << 24)#define XY_ZOPC (unsigned long )(227L << 40 | 87L)#define XG_ZOPC (unsigned long )(227L << 40 | 130L)// Data Conversion // INT to BFP #define CEFBR_ZOPC (unsigned int )(179 << 24 | 148 << 16)#define CDFBR_ZOPC (unsigned int )(179 << 24 | 149 << 16)#define CXFBR_ZOPC (unsigned int )(179 << 24 | 150 << 16)#define CEGBR_ZOPC (unsigned int )(179 << 24 | 164 << 16)#define CDGBR_ZOPC (unsigned int )(179 << 24 | 165 << 16)#define CXGBR_ZOPC (unsigned int )(179 << 24 | 166 << 16)// BFP to INT #define CFEBR_ZOPC (unsigned int )(179 << 24 | 152 << 16)#define CFDBR_ZOPC (unsigned int )(179 << 24 | 153 << 16)#define CFXBR_ZOPC (unsigned int )(179 << 24 | 154 << 16)#define CGEBR_ZOPC (unsigned int )(179 << 24 | 168 << 16)#define CGDBR_ZOPC (unsigned int )(179 << 24 | 169 << 16)#define CGXBR_ZOPC (unsigned int )(179 << 24 | 170 << 16)// INT to DEC #define CVD_ZOPC (unsigned int )(0x4e << 24)#define CVDY_ZOPC (unsigned long )(0xe3L << 40 | 0x26L)#define CVDG_ZOPC (unsigned long )(0xe3L << 40 | 0x2eL)// BFP Control #define SRNM_ZOPC (unsigned int )(178 << 24 | 153 << 16)#define EFPC_ZOPC (unsigned int )(179 << 24 | 140 << 16)#define SFPC_ZOPC (unsigned int )(179 << 24 | 132 << 16)#define STFPC_ZOPC (unsigned int )(178 << 24 | 156 << 16)#define LFPC_ZOPC (unsigned int )(178 << 24 | 157 << 16)// Branch Instructions // Register #define BCR_ZOPC (unsigned int )(7 << 8)#define BALR_ZOPC (unsigned int )(5 << 8)#define BASR_ZOPC (unsigned int )(13 << 8)#define BCTGR_ZOPC (unsigned long )(0xb946 << 16)// Absolute #define BC_ZOPC (unsigned int )(71 << 24)#define BAL_ZOPC (unsigned int )(69 << 24)#define BAS_ZOPC (unsigned int )(77 << 24)#define BXH_ZOPC (unsigned int )(134 << 24)#define BXHG_ZOPC (unsigned long )(235L << 40 | 68)// Relative #define BRC_ZOPC (unsigned int )(167 << 24 | 4 << 16)#define BRCL_ZOPC (unsigned long )(192L << 40 | 4L << 32)#define BRAS_ZOPC (unsigned int )(167 << 24 | 5 << 16)#define BRASL_ZOPC (unsigned long )(192L << 40 | 5L << 32)#define BRCT_ZOPC (unsigned int )(167 << 24 | 6 << 16)#define BRCTG_ZOPC (unsigned int )(167 << 24 | 7 << 16)#define BRXH_ZOPC (unsigned int )(132 << 24)#define BRXHG_ZOPC (unsigned long )(236L << 40 | 68)#define BRXLE_ZOPC (unsigned int )(133 << 24)#define BRXLG_ZOPC (unsigned long )(236L << 40 | 69)// Compare and Branch Instructions // signed comp reg/reg, branch Absolute #define CRB_ZOPC (unsigned long )(0xecL << 40 | 0xf6L) // z10 #define CGRB_ZOPC (unsigned long )(0xecL << 40 | 0xe4L) // z10 // signed comp reg/reg, branch Relative #define CRJ_ZOPC (unsigned long )(0xecL << 40 | 0x76L) // z10 #define CGRJ_ZOPC (unsigned long )(0xecL << 40 | 0x64L) // z10 // signed comp reg/imm, branch absolute #define CIB_ZOPC (unsigned long )(0xecL << 40 | 0xfeL) // z10 #define CGIB_ZOPC (unsigned long )(0xecL << 40 | 0xfcL) // z10 // signed comp reg/imm, branch relative #define CIJ_ZOPC (unsigned long )(0xecL << 40 | 0x7eL) // z10 #define CGIJ_ZOPC (unsigned long )(0xecL << 40 | 0x7cL) // z10 // unsigned comp reg/reg, branch Absolute #define CLRB_ZOPC (unsigned long )(0xecL << 40 | 0xf7L) // z10 #define CLGRB_ZOPC (unsigned long )(0xecL << 40 | 0xe5L) // z10 // unsigned comp reg/reg, branch Relative #define CLRJ_ZOPC (unsigned long )(0xecL << 40 | 0x77L) // z10 #define CLGRJ_ZOPC (unsigned long )(0xecL << 40 | 0x65L) // z10 // unsigned comp reg/imm, branch absolute #define CLIB_ZOPC (unsigned long )(0xecL << 40 | 0xffL) // z10 #define CLGIB_ZOPC (unsigned long )(0xecL << 40 | 0xfdL) // z10 // unsigned comp reg/imm, branch relative #define CLIJ_ZOPC (unsigned long )(0xecL << 40 | 0x7fL) // z10 #define CLGIJ_ZOPC (unsigned long )(0xecL << 40 | 0x7dL) // z10 // comp reg/reg, trap #define CRT_ZOPC (unsigned int )(0xb972 << 16) // z10 #define CGRT_ZOPC (unsigned int )(0xb960 << 16) // z10 #define CLRT_ZOPC (unsigned int )(0xb973 << 16) // z10 #define CLGRT_ZOPC (unsigned int )(0xb961 << 16) // z10 // comp reg/imm, trap #define CIT_ZOPC (unsigned long )(0xecL << 40 | 0x72L) // z10 #define CGIT_ZOPC (unsigned long )(0xecL << 40 | 0x70L) // z10 #define CLFIT_ZOPC (unsigned long )(0xecL << 40 | 0x73L) // z10 #define CLGIT_ZOPC (unsigned long )(0xecL << 40 | 0x71L) // z10 // Direct Memory Operations // Compare #define CLI_ZOPC (unsigned int )(0x95 << 24)#define CLIY_ZOPC (unsigned long )(0xebL << 40 | 0x55L)#define CLC_ZOPC (unsigned long )(0xd5L << 40)#define CLCL_ZOPC (unsigned int )(0x0f << 8)#define CLCLE_ZOPC (unsigned int )(0xa9 << 24)#define CLCLU_ZOPC (unsigned long )(0xebL << 40 | 0x8fL)// Move #define MVI_ZOPC (unsigned int )(0x92 << 24)#define MVIY_ZOPC (unsigned long )(0xebL << 40 | 0x52L)#define MVC_ZOPC (unsigned long )(0xd2L << 40)#define MVCL_ZOPC (unsigned int )(0x0e << 8)#define MVCLE_ZOPC (unsigned int )(0xa8 << 24)// Test #define TM_ZOPC (unsigned int )(0x91 << 24)#define TMY_ZOPC (unsigned long )(0xebL << 40 | 0x51L)// AND #define NI_ZOPC (unsigned int )(0x94 << 24)#define NIY_ZOPC (unsigned long )(0xebL << 40 | 0x54L)#define NC_ZOPC (unsigned long )(0xd4L << 40)// OR #define OI_ZOPC (unsigned int )(0x96 << 24)#define OIY_ZOPC (unsigned long )(0xebL << 40 | 0x56L)#define OC_ZOPC (unsigned long )(0xd6L << 40)// XOR #define XI_ZOPC (unsigned int )(0x97 << 24)#define XIY_ZOPC (unsigned long )(0xebL << 40 | 0x57L)#define XC_ZOPC (unsigned long )(0xd7L << 40)// Search String #define SRST_ZOPC (unsigned int )(178 << 24 | 94 << 16)#define SRSTU_ZOPC (unsigned int )(185 << 24 | 190 << 16)// Translate characters #define TROO_ZOPC (unsigned int )(0xb9 << 24 | 0x93 << 16)#define TROT_ZOPC (unsigned int )(0xb9 << 24 | 0x92 << 16)#define TRTO_ZOPC (unsigned int )(0xb9 << 24 | 0x91 << 16)#define TRTT_ZOPC (unsigned int )(0xb9 << 24 | 0x90 << 16)//--------------------------- //-- Vector Instructions -- //--------------------------- //---< Vector Support Instructions >--- //--- Load (memory) --- #define VLM_ZOPC (unsigned long )(0xe7L << 40 | 0x36L << 0) // load full vreg range (n * 128 bit) #define VL_ZOPC (unsigned long )(0xe7L << 40 | 0x06L << 0) // load full vreg (128 bit) #define VLEB_ZOPC (unsigned long )(0xe7L << 40 | 0x00L << 0) // load vreg element (8 bit) #define VLEH_ZOPC (unsigned long )(0xe7L << 40 | 0x01L << 0) // load vreg element (16 bit) #define VLEF_ZOPC (unsigned long )(0xe7L << 40 | 0x03L << 0) // load vreg element (32 bit) #define VLEG_ZOPC (unsigned long )(0xe7L << 40 | 0x02L << 0) // load vreg element (64 bit) #define VLREP_ZOPC (unsigned long )(0xe7L << 40 | 0x05L << 0) // load and replicate into all vector elements #define VLLEZ_ZOPC (unsigned long )(0xe7L << 40 | 0x04L << 0) // load logical element and zero. // vector register gather #define VGEF_ZOPC (unsigned long )(0xe7L << 40 | 0x13L << 0) // gather element (32 bit), V1(M3) = [D2(V2(M3),B2)] #define VGEG_ZOPC (unsigned long )(0xe7L << 40 | 0x12L << 0) // gather element (64 bit), V1(M3) = [D2(V2(M3),B2)] // vector register scatter #define VSCEF_ZOPC (unsigned long )(0xe7L << 40 | 0x1bL << 0) // vector scatter element FW #define VSCEG_ZOPC (unsigned long )(0xe7L << 40 | 0x1aL << 0) // vector scatter element DW #define VLBB_ZOPC (unsigned long )(0xe7L << 40 | 0x07L << 0) // load vreg to block boundary (load to alignment). #define VLL_ZOPC (unsigned long )(0xe7L << 40 | 0x37L << 0) // load vreg with length. //--- Load (register) --- #define VLR_ZOPC (unsigned long )(0xe7L << 40 | 0x56L << 0) // copy full vreg (128 bit) #define VLGV_ZOPC (unsigned long )(0xe7L << 40 | 0x21L << 0) // copy vreg element -> GR #define VLVG_ZOPC (unsigned long )(0xe7L << 40 | 0x22L << 0) // copy GR -> vreg element #define VLVGP_ZOPC (unsigned long )(0xe7L << 40 | 0x62L << 0) // copy GR2, GR3 (disjoint pair) -> vreg // vector register pack: cut in half the size the source vector elements #define VPK_ZOPC (unsigned long )(0xe7L << 40 | 0x94L << 0) // just cut #define VPKS_ZOPC (unsigned long )(0xe7L << 40 | 0x97L << 0) // saturate as signed values #define VPKLS_ZOPC (unsigned long )(0xe7L << 40 | 0x95L << 0) // saturate as unsigned values // vector register unpack: double in size the source vector elements #define VUPH_ZOPC (unsigned long )(0xe7L << 40 | 0xd7L << 0) // signed, left half of the source vector elements #define VUPLH_ZOPC (unsigned long )(0xe7L << 40 | 0xd5L << 0) // unsigned, left half of the source vector elements #define VUPL_ZOPC (unsigned long )(0xe7L << 40 | 0xd6L << 0) // signed, right half of the source vector elements #define VUPLL_ZOPC (unsigned long )(0xe7L << 40 | 0xd4L << 0) // unsigned, right half of the source vector element // vector register merge #define VMRH_ZOPC (unsigned long )(0xe7L << 40 | 0x61L << 0) // register merge high (left half of source registers) #define VMRL_ZOPC (unsigned long )(0xe7L << 40 | 0x60L << 0) // register merge low (right half of source registers) // vector register permute #define VPERM_ZOPC (unsigned long )(0xe7L << 40 | 0x8cL << 0) // vector permute #define VPDI_ZOPC (unsigned long )(0xe7L << 40 | 0x84L << 0) // vector permute DW immediate // vector register replicate #define VREP_ZOPC (unsigned long )(0xe7L << 40 | 0x4dL << 0) // vector replicate #define VREPI_ZOPC (unsigned long )(0xe7L << 40 | 0x45L << 0) // vector replicate immediate #define VSEL_ZOPC (unsigned long )(0xe7L << 40 | 0x8dL << 0) // vector select #define VSEG_ZOPC (unsigned long )(0xe7L << 40 | 0x5fL << 0) // vector sign-extend to DW (rightmost element in each DW). //--- Load (immediate) --- #define VLEIB_ZOPC (unsigned long )(0xe7L << 40 | 0x40L << 0) // load vreg element (16 bit imm to 8 bit) #define VLEIH_ZOPC (unsigned long )(0xe7L << 40 | 0x41L << 0) // load vreg element (16 bit imm to 16 bit) #define VLEIF_ZOPC (unsigned long )(0xe7L << 40 | 0x43L << 0) // load vreg element (16 bit imm to 32 bit) #define VLEIG_ZOPC (unsigned long )(0xe7L << 40 | 0x42L << 0) // load vreg element (16 bit imm to 64 bit) //--- Store --- #define VSTM_ZOPC (unsigned long )(0xe7L << 40 | 0x3eL << 0) // store full vreg range (n * 128 bit) #define VST_ZOPC (unsigned long )(0xe7L << 40 | 0x0eL << 0) // store full vreg (128 bit) #define VSTEB_ZOPC (unsigned long )(0xe7L << 40 | 0x08L << 0) // store vreg element (8 bit) #define VSTEH_ZOPC (unsigned long )(0xe7L << 40 | 0x09L << 0) // store vreg element (16 bit) #define VSTEF_ZOPC (unsigned long )(0xe7L << 40 | 0x0bL << 0) // store vreg element (32 bit) #define VSTEG_ZOPC (unsigned long )(0xe7L << 40 | 0x0aL << 0) // store vreg element (64 bit) #define VSTL_ZOPC (unsigned long )(0xe7L << 40 | 0x3fL << 0) // store vreg with length. //--- Misc --- #define VGM_ZOPC (unsigned long )(0xe7L << 40 | 0x46L << 0) // generate bit mask, [start..end] = '1', else '0' #define VGBM_ZOPC (unsigned long )(0xe7L << 40 | 0x44L << 0) // generate byte mask, bits(imm16) -> bytes //---< Vector Arithmetic Instructions >--- // Load #define VLC_ZOPC (unsigned long )(0xe7L << 40 | 0xdeL << 0) // V1 := -V2, element size = 2**m #define VLP_ZOPC (unsigned long )(0xe7L << 40 | 0xdfL << 0) // V1 := |V2|, element size = 2**m // ADD #define VA_ZOPC (unsigned long )(0xe7L << 40 | 0xf3L << 0) // V1 := V2 + V3, element size = 2**m #define VACC_ZOPC (unsigned long )(0xe7L << 40 | 0xf1L << 0) // V1 := carry(V2 + V3), element size = 2**m // SUB #define VS_ZOPC (unsigned long )(0xe7L << 40 | 0xf7L << 0) // V1 := V2 - V3, element size = 2**m #define VSCBI_ZOPC (unsigned long )(0xe7L << 40 | 0xf5L << 0) // V1 := borrow(V2 - V3), element size = 2**m // MUL #define VML_ZOPC (unsigned long )(0xe7L << 40 | 0xa2L << 0) // V1 := V2 * V3, element size = 2**m #define VMH_ZOPC (unsigned long )(0xe7L << 40 | 0xa3L << 0) // V1 := V2 * V3, element size = 2**m #define VMLH_ZOPC (unsigned long )(0xe7L << 40 | 0xa1L << 0) // V1 := V2 * V3, element size = 2**m, unsigned #define VME_ZOPC (unsigned long )(0xe7L << 40 | 0xa6L << 0) // V1 := V2 * V3, element size = 2**m #define VMLE_ZOPC (unsigned long )(0xe7L << 40 | 0xa4L << 0) // V1 := V2 * V3, element size = 2**m, unsigned #define VMO_ZOPC (unsigned long )(0xe7L << 40 | 0xa7L << 0) // V1 := V2 * V3, element size = 2**m #define VMLO_ZOPC (unsigned long )(0xe7L << 40 | 0xa5L << 0) // V1 := V2 * V3, element size = 2**m, unsigned // MUL & ADD #define VMAL_ZOPC (unsigned long )(0xe7L << 40 | 0xaaL << 0) // V1 := V2 * V3 + V4, element size = 2**m #define VMAH_ZOPC (unsigned long )(0xe7L << 40 | 0xabL << 0) // V1 := V2 * V3 + V4, element size = 2**m #define VMALH_ZOPC (unsigned long )(0xe7L << 40 | 0xa9L << 0) // V1 := V2 * V3 + V4, element size = 2**m, unsigned #define VMAE_ZOPC (unsigned long )(0xe7L << 40 | 0xaeL << 0) // V1 := V2 * V3 + V4, element size = 2**m #define VMALE_ZOPC (unsigned long )(0xe7L << 40 | 0xacL << 0) // V1 := V2 * V3 + V4, element size = 2**m, unsigned #define VMAO_ZOPC (unsigned long )(0xe7L << 40 | 0xafL << 0) // V1 := V2 * V3 + V4, element size = 2**m #define VMALO_ZOPC (unsigned long )(0xe7L << 40 | 0xadL << 0) // V1 := V2 * V3 + V4, element size = 2**m, unsigned // Vector SUM #define VSUM_ZOPC (unsigned long )(0xe7L << 40 | 0x64L << 0) // V1[j] := toFW(sum(V2[i]) + V3[j]), subelements: byte or HW #define VSUMG_ZOPC (unsigned long )(0xe7L << 40 | 0x65L << 0) // V1[j] := toDW(sum(V2[i]) + V3[j]), subelements: HW or FW #define VSUMQ_ZOPC (unsigned long )(0xe7L << 40 | 0x67L << 0) // V1[j] := toQW(sum(V2[i]) + V3[j]), subelements: FW or DW // Average #define VAVG_ZOPC (unsigned long )(0xe7L << 40 | 0xf2L << 0) // V1 := (V2+V3+1)/2, signed, element size = 2**m #define VAVGL_ZOPC (unsigned long )(0xe7L << 40 | 0xf0L << 0) // V1 := (V2+V3+1)/2, unsigned, element size = 2**m // VECTOR Galois Field Multiply Sum #define VGFM_ZOPC (unsigned long )(0xe7L << 40 | 0xb4L << 0)#define VGFMA_ZOPC (unsigned long )(0xe7L << 40 | 0xbcL << 0)//---< Vector Logical Instructions >--- // AND #define VN_ZOPC (unsigned long )(0xe7L << 40 | 0x68L << 0) // V1 := V2 & V3, element size = 2**m #define VNC_ZOPC (unsigned long )(0xe7L << 40 | 0x69L << 0) // V1 := V2 & ~V3, element size = 2**m // XOR #define VX_ZOPC (unsigned long )(0xe7L << 40 | 0x6dL << 0) // V1 := V2 ^ V3, element size = 2**m // NOR #define VNO_ZOPC (unsigned long )(0xe7L << 40 | 0x6bL << 0) // V1 := !(V2 | V3), element size = 2**m // OR #define VO_ZOPC (unsigned long )(0xe7L << 40 | 0x6aL << 0) // V1 := V2 | V3, element size = 2**m // Comparison (element-wise) #define VCEQ_ZOPC (unsigned long )(0xe7L << 40 | 0xf8L << 0) // V1 := (V2 == V3) ? 0xffff : 0x0000, element size = 2**m #define VCH_ZOPC (unsigned long )(0xe7L << 40 | 0xfbL << 0) // V1 := (V2 > V3) ? 0xffff : 0x0000, element size = 2**m, signed #define VCHL_ZOPC (unsigned long )(0xe7L << 40 | 0xf9L << 0) // V1 := (V2 > V3) ? 0xffff : 0x0000, element size = 2**m, unsigned // Max/Min (element-wise) #define VMX_ZOPC (unsigned long )(0xe7L << 40 | 0xffL << 0) // V1 := (V2 > V3) ? V2 : V3, element size = 2**m, signed #define VMXL_ZOPC (unsigned long )(0xe7L << 40 | 0xfdL << 0) // V1 := (V2 > V3) ? V2 : V3, element size = 2**m, unsigned #define VMN_ZOPC (unsigned long )(0xe7L << 40 | 0xfeL << 0) // V1 := (V2 < V3) ? V2 : V3, element size = 2**m, signed #define VMNL_ZOPC (unsigned long )(0xe7L << 40 | 0xfcL << 0) // V1 := (V2 < V3) ? V2 : V3, element size = 2**m, unsigned // Leading/Trailing Zeros, population count #define VCLZ_ZOPC (unsigned long )(0xe7L << 40 | 0x53L << 0) // V1 := leadingzeros(V2), element size = 2**m #define VCTZ_ZOPC (unsigned long )(0xe7L << 40 | 0x52L << 0) // V1 := trailingzeros(V2), element size = 2**m #define VPOPCT_ZOPC (unsigned long )(0xe7L << 40 | 0x50L << 0) // V1 := popcount(V2), bytewise!! // Rotate/Shift #define VERLLV_ZOPC (unsigned long )(0xe7L << 40 | 0x73L << 0) // V1 := rotateleft(V2), rotate count in V3 element #define VERLL_ZOPC (unsigned long )(0xe7L << 40 | 0x33L << 0) // V1 := rotateleft(V3), rotate count from d2(b2). #define VERIM_ZOPC (unsigned long )(0xe7L << 40 | 0x72L << 0) // Rotate then insert under mask. Read Principles of Operation!! #define VESLV_ZOPC (unsigned long )(0xe7L << 40 | 0x70L << 0) // V1 := SLL(V2, V3), unsigned, element-wise #define VESL_ZOPC (unsigned long )(0xe7L << 40 | 0x30L << 0) // V1 := SLL(V3), unsigned, shift count from d2(b2). #define VESRAV_ZOPC (unsigned long )(0xe7L << 40 | 0x7AL << 0) // V1 := SRA(V2, V3), signed, element-wise #define VESRA_ZOPC (unsigned long )(0xe7L << 40 | 0x3AL << 0) // V1 := SRA(V3), signed, shift count from d2(b2). #define VESRLV_ZOPC (unsigned long )(0xe7L << 40 | 0x78L << 0) // V1 := SRL(V2, V3), unsigned, element-wise #define VESRL_ZOPC (unsigned long )(0xe7L << 40 | 0x38L << 0) // V1 := SRL(V3), unsigned, shift count from d2(b2). #define VSL_ZOPC (unsigned long )(0xe7L << 40 | 0x74L << 0) // V1 := SLL(V2), unsigned, bit-count #define VSLB_ZOPC (unsigned long )(0xe7L << 40 | 0x75L << 0) // V1 := SLL(V2), unsigned, byte-count #define VSLDB_ZOPC (unsigned long )(0xe7L << 40 | 0x77L << 0) // V1 := SLL((V2,V3)), unsigned, byte-count #define VSRA_ZOPC (unsigned long )(0xe7L << 40 | 0x7eL << 0) // V1 := SRA(V2), signed, bit-count #define VSRAB_ZOPC (unsigned long )(0xe7L << 40 | 0x7fL << 0) // V1 := SRA(V2), signed, byte-count #define VSRL_ZOPC (unsigned long )(0xe7L << 40 | 0x7cL << 0) // V1 := SRL(V2), unsigned, bit-count #define VSRLB_ZOPC (unsigned long )(0xe7L << 40 | 0x7dL << 0) // V1 := SRL(V2), unsigned, byte-count // Test under Mask #define VTM_ZOPC (unsigned long )(0xe7L << 40 | 0xd8L << 0) // Like TM, set CC according to state of selected bits. //---< Vector String Instructions >--- #define VFAE_ZOPC (unsigned long )(0xe7L << 40 | 0x82L << 0) // Find any element #define VFEE_ZOPC (unsigned long )(0xe7L << 40 | 0x80L << 0) // Find element equal #define VFENE_ZOPC (unsigned long )(0xe7L << 40 | 0x81L << 0) // Find element not equal #define VSTRC_ZOPC (unsigned long )(0xe7L << 40 | 0x8aL << 0) // String range compare #define VISTR_ZOPC (unsigned long )(0xe7L << 40 | 0x5cL << 0) // Isolate String //-------------------------------- //-- Miscellaneous Operations -- //-------------------------------- // Execute #define EX_ZOPC (unsigned int )(68L << 24)#define EXRL_ZOPC (unsigned long )(0xc6L << 40 | 0x00L << 32) // z10 // Compare and Swap #define CS_ZOPC (unsigned int )(0xba << 24)#define CSY_ZOPC (unsigned long )(0xebL << 40 | 0x14L)#define CSG_ZOPC (unsigned long )(0xebL << 40 | 0x30L)// Interlocked-Update #define LAA_ZOPC (unsigned long )(0xebL << 40 | 0xf8L) // z196 #define LAAG_ZOPC (unsigned long )(0xebL << 40 | 0xe8L) // z196 #define LAAL_ZOPC (unsigned long )(0xebL << 40 | 0xfaL) // z196 #define LAALG_ZOPC (unsigned long )(0xebL << 40 | 0xeaL) // z196 #define LAN_ZOPC (unsigned long )(0xebL << 40 | 0xf4L) // z196 #define LANG_ZOPC (unsigned long )(0xebL << 40 | 0xe4L) // z196 #define LAX_ZOPC (unsigned long )(0xebL << 40 | 0xf7L) // z196 #define LAXG_ZOPC (unsigned long )(0xebL << 40 | 0xe7L) // z196 #define LAO_ZOPC (unsigned long )(0xebL << 40 | 0xf6L) // z196 #define LAOG_ZOPC (unsigned long )(0xebL << 40 | 0xe6L) // z196 // System Functions #define STCKF_ZOPC (unsigned int )(0xb2 << 24 | 0x7c << 16)#define STFLE_ZOPC (unsigned int )(0xb2 << 24 | 0xb0 << 16)#define ECTG_ZOPC (unsigned long )(0xc8L <<40 | 0x01L << 32) // z10 #define ECAG_ZOPC (unsigned long )(0xebL <<40 | 0x4cL) // z10 // Execution Prediction #define PFD_ZOPC (unsigned long )(0xe3L <<40 | 0x36L) // z10 #define PFDRL_ZOPC (unsigned long )(0xc6L <<40 | 0x02L << 32) // z10 #define BPP_ZOPC (unsigned long )(0xc7L <<40) // branch prediction preload -- EC12 #define BPRP_ZOPC (unsigned long )(0xc5L <<40) // branch prediction preload -- EC12 // Transaction Control #define TBEGIN_ZOPC (unsigned long )(0xe560L << 32) // tx begin -- EC12 #define TBEGINC_ZOPC (unsigned long )(0xe561L << 32) // tx begin (constrained) -- EC12 #define TEND_ZOPC (unsigned int )(0xb2f8 << 16) // tx end -- EC12 #define TABORT_ZOPC (unsigned int )(0xb2fc << 16) // tx abort -- EC12 #define ETND_ZOPC (unsigned int )(0xb2ec << 16) // tx nesting depth -- EC12 #define PPA_ZOPC (unsigned int )(0xb2e8 << 16) // tx processor assist -- EC12 // Crypto and Checksum #define CKSM_ZOPC (unsigned int )(0xb2 << 24 | 0x41 << 16) // checksum. This is NOT CRC32 #define KM_ZOPC (unsigned int )(0xb9 << 24 | 0x2e << 16) // cipher #define KMC_ZOPC (unsigned int )(0xb9 << 24 | 0x2f << 16) // cipher #define KMA_ZOPC (unsigned int )(0xb9 << 24 | 0x29 << 16) // cipher #define KMF_ZOPC (unsigned int )(0xb9 << 24 | 0x2a << 16) // cipher #define KMCTR_ZOPC (unsigned int )(0xb9 << 24 | 0x2d << 16) // cipher #define KMO_ZOPC (unsigned int )(0xb9 << 24 | 0x2b << 16) // cipher #define KIMD_ZOPC (unsigned int )(0xb9 << 24 | 0x3e << 16) // SHA (msg digest) #define KLMD_ZOPC (unsigned int )(0xb9 << 24 | 0x3f << 16) // SHA (msg digest) #define KMAC_ZOPC (unsigned int )(0xb9 << 24 | 0x1e << 16) // Message Authentication Code // Various #define TCEB_ZOPC (unsigned long )(237L << 40 | 16)#define TCDB_ZOPC (unsigned long )(237L << 40 | 17)#define TAM_ZOPC (unsigned long )(267)#define FLOGR_ZOPC (unsigned int )(0xb9 << 24 | 0x83 << 16)#define POPCNT_ZOPC (unsigned int )(0xb9e1 << 16)#define AHHHR_ZOPC (unsigned int )(0xb9c8 << 16)#define AHHLR_ZOPC (unsigned int )(0xb9d8 << 16)// OpCode field masks #define RI_MASK (unsigned int )(0xff << 24 | 0x0f << 16)#define RRE_MASK (unsigned int )(0xff << 24 | 0xff << 16)#define RSI_MASK (unsigned int )(0xff << 24)#define RIE_MASK (unsigned long )(0xffL << 40 | 0xffL)#define RIL_MASK (unsigned long )(0xffL << 40 | 0x0fL << 32)#define BASR_MASK (unsigned int )(0xff << 8)#define BCR_MASK (unsigned int )(0xff << 8)#define BRC_MASK (unsigned int )(0xff << 24 | 0x0f << 16)#define LGHI_MASK (unsigned int )(0xff << 24 | 0x0f << 16)#define LLI_MASK (unsigned int )(0xff << 24 | 0x0f << 16)#define II_MASK (unsigned int )(0xff << 24 | 0x0f << 16)#define LLIF_MASK (unsigned long )(0xffL << 40 | 0x0fL << 32)#define IIF_MASK (unsigned long )(0xffL << 40 | 0x0fL << 32)#define BRASL_MASK (unsigned long )(0xffL << 40 | 0x0fL << 32)#define TM_MASK (unsigned int )(0xff << 24)#define TMY_MASK (unsigned long )(0xffL << 40 | 0xffL)#define LB_MASK (unsigned long )(0xffL << 40 | 0xffL)#define LH_MASK (unsigned int )(0xff << 24)#define L_MASK (unsigned int )(0xff << 24)#define LY_MASK (unsigned long )(0xffL << 40 | 0xffL)#define LG_MASK (unsigned long )(0xffL << 40 | 0xffL)#define LLGH_MASK (unsigned long )(0xffL << 40 | 0xffL)#define LLGF_MASK (unsigned long )(0xffL << 40 | 0xffL)#define SLAG_MASK (unsigned long )(0xffL << 40 | 0xffL)#define LARL_MASK (unsigned long )(0xff0fL << 32)#define LGRL_MASK (unsigned long )(0xff0fL << 32)#define LE_MASK (unsigned int )(0xff << 24)#define LD_MASK (unsigned int )(0xff << 24)#define ST_MASK (unsigned int )(0xff << 24)#define STC_MASK (unsigned int )(0xff << 24)#define STG_MASK (unsigned long )(0xffL << 40 | 0xffL)#define STH_MASK (unsigned int )(0xff << 24)#define STE_MASK (unsigned int )(0xff << 24)#define STD_MASK (unsigned int )(0xff << 24)#define CMPBRANCH_MASK (unsigned long )(0xffL << 40 | 0xffL)#define REL_LONG_MASK (unsigned long )(0xff0fL << 32)public :// Condition code masks. Details: // - Mask bit#3 must be zero for all compare and branch/trap instructions to ensure // future compatibility. // - For all arithmetic instructions which set the condition code, mask bit#3 // indicates overflow ("unordered" in float operations). // - "unordered" float comparison results have to be treated as low. // - When overflow/unordered is detected, none of the branch conditions is true, // except for bcondOverflow/bcondNotOrdered and bcondAlways. // - For INT comparisons, the inverse condition can be calculated as (14-cond). // - For FLOAT comparisons, the inverse condition can be calculated as (15-cond). enum branch_condition {// Specific names. Make use of lightweight sync. // Full and lightweight sync operation. // arithmetic compare instructions // arithmetic load and test, insert instructions // Mask bit#3 must be zero for future compatibility. // arithmetic calculation instructions // Mask bit#3 indicates overflow if detected by instr. // Mask bit#3 = 0 (overflow is not handled by compiler). // float comparisons // float comparisons // float comparisons // float comparisons // float comparisons // float comparisons // float comparisons // unsigned arithmetic calculation instructions // Mask bit#0 is not used by these instructions. // There is no indication of overflow for these instr. // bcondLogZero_Borrow = 8, // This CC is never generated. /* bcondLogZero_Borrow | */ bcondLogNotZero_Borrow, // Vector compare instructions // All vector elements evaluate true // Some vector elements evaluate true, some false // All vector elements evaluate false // string search instructions // bit test instructions // for tmll enum Condition {// z/Architecture // Rounding mode for float-2-int conversions. enum RoundingMode {// Mode taken from FPC register. // Vector Register Element Type. enum VRegElemType {
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2026-04-02
