/* * Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved. * Copyright (c) 2021, Azul Systems, Inc. All rights reserved. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * * This code is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License version 2 only, as * published by the Free Software Foundation. * * This code is distributed in the hope that it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * version 2 for more details (a copy is included in the LICENSE file that * accompanied this code). * * You should have received a copy of the GNU General Public License version * 2 along with this work; if not, write to the Free Software Foundation, * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. * * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA * or visit www.oracle.com if you need additional information or have any * questions. *
*/
// Most of the runtime stubs have this simple frame layout. // This class exists to make the layout shared in one place. // Offsets are for compiler stack slots, which are jints. enum layout { // The frame sender code expects that rbp will be in the "natural" place and // will override any oopMap setting for it. We must therefore force the layout // so that it agrees with the frame sender code. // we don't expect any arg reg save area so aarch64 asserts that // frame::arg_reg_save_area_bytes == 0
rfp_off = 0,
rfp_off2,
return_off, return_off2,
framesize
};
};
// FIXME -- this is used by C1 class RegisterSaver { constbool _save_vectors; public:
RegisterSaver(bool save_vectors) : _save_vectors(save_vectors) {}
OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words); void restore_live_registers(MacroAssembler* masm);
// Offsets into the register save area // Used by deoptimization when it is managing result register // values on its own
int reg_offset_in_bytes(Register r); int r0_offset_in_bytes() { return reg_offset_in_bytes(r0); } int rscratch1_offset_in_bytes() { return reg_offset_in_bytes(rscratch1); } int v0_offset_in_bytes();
// Total stack size in bytes for saving sve predicate registers. int total_sve_predicate_in_bytes();
// Capture info about frame layout // Note this is only correct when not saving full vectors. enum layout {
fpu_state_off = 0,
fpu_state_end = fpu_state_off + FPUStateSizeInWords - 1, // The frame sender code expects that rfp will be in // the "natural" place and will override any oopMap // setting for it. We must therefore force the layout // so that it agrees with the frame sender code.
r0_off = fpu_state_off + FPUStateSizeInWords,
rfp_off = r0_off + (Register::number_of_registers - 2) * Register::max_slots_per_register,
return_off = rfp_off + Register::max_slots_per_register, // slot for return address
reg_save_size = return_off + Register::max_slots_per_register};
};
int RegisterSaver::reg_offset_in_bytes(Register r) { // The integer registers are located above the floating point // registers in the stack frame pushed by save_live_registers() so the // offset depends on whether we are saving full vectors, and whether // those vectors are NEON or SVE.
int slots_per_vect = FloatRegister::save_slots_per_register;
#if COMPILER2_OR_JVMCI if (_save_vectors) {
slots_per_vect = FloatRegister::slots_per_neon_register;
int RegisterSaver::v0_offset_in_bytes() { // The floating point registers are located above the predicate registers if // they are present in the stack frame pushed by save_live_registers(). So the // offset depends on the saved total predicate vectors in the stack frame. return (total_sve_predicate_in_bytes() / VMRegImpl::stack_slot_size) * BytesPerInt;
}
#if COMPILER2_OR_JVMCI if (_save_vectors) { int extra_save_slots_per_register = 0; // Save upper half of vector registers if (use_sve) {
extra_save_slots_per_register = sve_vector_size_in_slots - FloatRegister::save_slots_per_register;
} else {
extra_save_slots_per_register = FloatRegister::extra_save_slots_per_neon_register;
} int extra_vector_bytes = extra_save_slots_per_register *
VMRegImpl::stack_slot_size *
FloatRegister::number_of_registers;
additional_frame_words += ((extra_vector_bytes + total_predicate_in_bytes) / wordSize);
} #else
assert(!_save_vectors, "vectors are generated only by C2 and JVMCI"); #endif
int frame_size_in_bytes = align_up(additional_frame_words * wordSize +
reg_save_size * BytesPerInt, 16); // OopMap frame size is in compiler stack slots (jint's) not bytes or words int frame_size_in_slots = frame_size_in_bytes / BytesPerInt; // The caller will allocate additional_frame_words int additional_frame_slots = additional_frame_words * wordSize / BytesPerInt; // CodeBlob frame size is in words. int frame_size_in_words = frame_size_in_bytes / wordSize;
*total_frame_words = frame_size_in_words;
// Save Integer and Float registers.
__ enter();
__ push_CPU_state(_save_vectors, use_sve, sve_vector_size_in_bytes, total_predicate_in_bytes);
// Set an oopmap for the call site. This oopmap will map all // oop-registers and debug-info registers as callee-saved. This // will allow deoptimization at this safepoint to find all possible // debug-info recordings, as well as let GC find all oops.
OopMapSet *oop_maps = new OopMapSet();
OopMap* oop_map = new OopMap(frame_size_in_slots, 0);
for (int i = 0; i < Register::number_of_registers; i++) { Register r = as_Register(i); if (i <= rfp->encoding() && r != rscratch1 && r != rscratch2) { // SP offsets are in 4-byte words. // Register slots are 8 bytes wide, 32 floating-point registers. int sp_offset = Register::max_slots_per_register * i +
FloatRegister::save_slots_per_register * FloatRegister::number_of_registers;
oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset + additional_frame_slots), r->as_VMReg());
}
}
for (int i = 0; i < FloatRegister::number_of_registers; i++) {
FloatRegister r = as_FloatRegister(i); int sp_offset = 0; if (_save_vectors) {
sp_offset = use_sve ? (total_predicate_in_slots + sve_vector_size_in_slots * i) :
(FloatRegister::slots_per_neon_register * i);
} else {
sp_offset = FloatRegister::save_slots_per_register * i;
}
oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset), r->as_VMReg());
}
return oop_map;
}
void RegisterSaver::restore_live_registers(MacroAssembler* masm) { #ifdef COMPILER2
__ pop_CPU_state(_save_vectors, Matcher::supports_scalable_vector(),
Matcher::scalable_vector_reg_size(T_BYTE), total_sve_predicate_in_bytes()); #else #if !INCLUDE_JVMCI
assert(!_save_vectors, "vectors are generated only by C2 and JVMCI"); #endif
__ pop_CPU_state(_save_vectors); #endif
__ ldp(rfp, lr, Address(__ post(sp, 2 * wordSize)));
__ authenticate_return_address();
}
// Is vector's size (in bytes) bigger than a size saved by default? // 8 bytes vector registers are saved by default on AArch64. // The SVE supported min vector size is 8 bytes and we need to save // predicate registers when the vector size is 8 bytes as well. bool SharedRuntime::is_wide_vector(int size) { return size > 8 || (UseSVE > 0 && size >= 8);
}
// --------------------------------------------------------------------------- // Read the array of BasicTypes from a signature, and compute where the // arguments should go. Values in the VMRegPair regs array refer to 4-byte // quantities. Values less than VMRegImpl::stack0 are registers, those above // refer to 4-byte stack slots. All stack slots are based off of the stack pointer // as framesizes are fixed. // VMRegImpl::stack0 refers to the first slot 0(sp). // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. // Register up to Register::number_of_registers are the 64-bit // integer registers.
// Note: the INPUTS in sig_bt are in units of Java argument words, // which are 64-bit. The OUTPUTS are in 32-bit units.
// The Java calling convention is a "shifted" version of the C ABI. // By skipping the first C ABI register we can call non-static jni // methods with small numbers of arguments without having to shuffle // the arguments at all. Since we control the java ABI we ought to at // least get some advantage out of it.
int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
VMRegPair *regs, int total_args_passed) {
uint int_args = 0;
uint fp_args = 0;
uint stk_args = 0; // inc by 2 each time
for (int i = 0; i < total_args_passed; i++) { switch (sig_bt[i]) { case T_BOOLEAN: case T_CHAR: case T_BYTE: case T_SHORT: case T_INT: if (int_args < Argument::n_int_register_parameters_j) {
regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
} else {
regs[i].set1(VMRegImpl::stack2reg(stk_args));
stk_args += 2;
} break; case T_VOID: // halves of T_LONG or T_DOUBLE
assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
regs[i].set_bad(); break; case T_LONG:
assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half"); // fall through case T_OBJECT: case T_ARRAY: case T_ADDRESS: if (int_args < Argument::n_int_register_parameters_j) {
regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
} else {
regs[i].set2(VMRegImpl::stack2reg(stk_args));
stk_args += 2;
} break; case T_FLOAT: if (fp_args < Argument::n_float_register_parameters_j) {
regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
} else {
regs[i].set1(VMRegImpl::stack2reg(stk_args));
stk_args += 2;
} break; case T_DOUBLE:
assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half"); if (fp_args < Argument::n_float_register_parameters_j) {
regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
} else {
regs[i].set2(VMRegImpl::stack2reg(stk_args));
stk_args += 2;
} break; default:
ShouldNotReachHere(); break;
}
}
return align_up(stk_args, 2);
}
// Patch the callers callsite with entry to compiled code if it exists. staticvoid patch_callers_callsite(MacroAssembler *masm) {
Label L;
__ ldr(rscratch1, Address(rmethod, in_bytes(Method::code_offset())));
__ cbz(rscratch1, L);
__ enter();
__ push_CPU_state();
// VM needs caller's callsite // VM needs target method // This needs to be a long call since we will relocate this adapter to // the codeBuffer and it may not reach
staticvoid gen_c2i_adapter(MacroAssembler *masm, int total_args_passed, int comp_args_on_stack, const BasicType *sig_bt, const VMRegPair *regs,
Label& skip_fixup) { // Before we get into the guts of the C2I adapter, see if we should be here // at all. We've come from compiled code and are attempting to jump to the // interpreter, which means the caller made a static call to get here // (vcalls always get a compiled target if there is one). Check for a // compiled target. If there is one, we need to patch the caller's call.
patch_callers_callsite(masm);
__ bind(skip_fixup);
int words_pushed = 0;
// Since all args are passed on the stack, total_args_passed * // Interpreter::stackElementSize is the space we need.
int extraspace = total_args_passed * Interpreter::stackElementSize;
__ mov(r19_sender_sp, sp);
// stack is aligned, keep it that way
extraspace = align_up(extraspace, 2*wordSize);
if (extraspace)
__ sub(sp, sp, extraspace);
// Now write the args into the outgoing interpreter space for (int i = 0; i < total_args_passed; i++) { if (sig_bt[i] == T_VOID) {
assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); continue;
}
// offset to start parameters int st_off = (total_args_passed - i - 1) * Interpreter::stackElementSize; int next_off = st_off - Interpreter::stackElementSize;
// Say 4 args: // i st_off // 0 32 T_LONG // 1 24 T_VOID // 2 16 T_OBJECT // 3 8 T_BOOL // - 0 return address // // However to make thing extra confusing. Because we can fit a Java long/double in // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter // leaves one slot empty and only stores to a single slot. In this case the // slot that is occupied is the T_VOID slot. See I said it was confusing.
VMReg r_1 = regs[i].first();
VMReg r_2 = regs[i].second(); if (!r_1->is_valid()) {
assert(!r_2->is_valid(), ""); continue;
} if (r_1->is_stack()) { // memory to memory use rscratch1 int ld_off = (r_1->reg2stack() * VMRegImpl::stack_slot_size
+ extraspace
+ words_pushed * wordSize); if (!r_2->is_valid()) { // sign extend??
__ ldrw(rscratch1, Address(sp, ld_off));
__ str(rscratch1, Address(sp, st_off));
} else {
__ ldr(rscratch1, Address(sp, ld_off));
// Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG // T_DOUBLE and T_LONG use two slots in the interpreter if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { // ld_off == LSW, ld_off+wordSize == MSW // st_off == MSW, next_off == LSW
__ str(rscratch1, Address(sp, next_off)); #ifdef ASSERT // Overwrite the unused slot with known junk
__ mov(rscratch1, (uint64_t)0xdeadffffdeadaaaaull);
__ str(rscratch1, Address(sp, st_off)); #endif/* ASSERT */
} else {
__ str(rscratch1, Address(sp, st_off));
}
}
} elseif (r_1->is_Register()) { Register r = r_1->as_Register(); if (!r_2->is_valid()) { // must be only an int (or less ) so move only 32bits to slot // why not sign extend??
__ str(r, Address(sp, st_off));
} else { // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG // T_DOUBLE and T_LONG use two slots in the interpreter if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { // jlong/double in gpr #ifdef ASSERT // Overwrite the unused slot with known junk
__ mov(rscratch1, (uint64_t)0xdeadffffdeadaaabull);
__ str(rscratch1, Address(sp, st_off)); #endif/* ASSERT */
__ str(r, Address(sp, next_off));
} else {
__ str(r, Address(sp, st_off));
}
}
} else {
assert(r_1->is_FloatRegister(), ""); if (!r_2->is_valid()) { // only a float use just part of the slot
__ strs(r_1->as_FloatRegister(), Address(sp, st_off));
} else { #ifdef ASSERT // Overwrite the unused slot with known junk
__ mov(rscratch1, (uint64_t)0xdeadffffdeadaaacull);
__ str(rscratch1, Address(sp, st_off)); #endif/* ASSERT */
__ strd(r_1->as_FloatRegister(), Address(sp, next_off));
}
}
}
void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm, int total_args_passed, int comp_args_on_stack, const BasicType *sig_bt, const VMRegPair *regs) {
// Note: r19_sender_sp contains the senderSP on entry. We must // preserve it since we may do a i2c -> c2i transition if we lose a // race where compiled code goes non-entrant while we get args // ready.
// Adapters are frameless.
// An i2c adapter is frameless because the *caller* frame, which is // interpreted, routinely repairs its own esp (from // interpreter_frame_last_sp), even if a callee has modified the // stack pointer. It also recalculates and aligns sp.
// A c2i adapter is frameless because the *callee* frame, which is // interpreted, routinely repairs its caller's sp (from sender_sp, // which is set up via the senderSP register).
// In other words, if *either* the caller or callee is interpreted, we can // get the stack pointer repaired after a call.
// This is why c2i and i2c adapters cannot be indefinitely composed. // In particular, if a c2i adapter were to somehow call an i2c adapter, // both caller and callee would be compiled methods, and neither would // clean up the stack pointer changes performed by the two adapters. // If this happens, control eventually transfers back to the compiled // caller, but with an uncorrected stack, causing delayed havoc.
if (VerifyAdapterCalls &&
(Interpreter::code() != NULL || StubRoutines::code1() != NULL)) { #if 0 // So, let's test for cascading c2i/i2c adapters right now. // assert(Interpreter::contains($return_addr) || // StubRoutines::contains($return_addr), // "i2c adapter must return to an interpreter frame");
__ block_comment("verify_i2c { ");
Label L_ok; if (Interpreter::code() != NULL)
range_check(masm, rax, r11,
Interpreter::code()->code_start(), Interpreter::code()->code_end(),
L_ok); if (StubRoutines::code1() != NULL)
range_check(masm, rax, r11,
StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(),
L_ok); if (StubRoutines::code2() != NULL)
range_check(masm, rax, r11,
StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(),
L_ok); constchar* msg = "i2c adapter must return to an interpreter frame";
__ block_comment(msg);
__ stop(msg);
__ bind(L_ok);
__ block_comment("} verify_i2ce "); #endif
}
// Cut-out for having no stack args. int comp_words_on_stack = align_up(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord; if (comp_args_on_stack) {
__ sub(rscratch1, sp, comp_words_on_stack * wordSize);
__ andr(sp, rscratch1, -16);
}
// Will jump to the compiled code just as if compiled code was doing it. // Pre-load the register-jump target early, to schedule it better.
__ ldr(rscratch1, Address(rmethod, in_bytes(Method::from_compiled_offset())));
#if INCLUDE_JVMCI if (EnableJVMCI) { // check if this call should be routed towards a specific entry point
__ ldr(rscratch2, Address(rthread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())));
Label no_alternative_target;
__ cbz(rscratch2, no_alternative_target);
__ mov(rscratch1, rscratch2);
__ str(zr, Address(rthread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())));
__ bind(no_alternative_target);
} #endif// INCLUDE_JVMCI
// Now generate the shuffle code. for (int i = 0; i < total_args_passed; i++) { if (sig_bt[i] == T_VOID) {
assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); continue;
}
// Pick up 0, 1 or 2 words from SP+offset.
assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(), "scrambled load targets?"); // Load in argument order going down. int ld_off = (total_args_passed - i - 1)*Interpreter::stackElementSize; // Point to interpreter value (vs. tag) int next_off = ld_off - Interpreter::stackElementSize; // // //
VMReg r_1 = regs[i].first();
VMReg r_2 = regs[i].second(); if (!r_1->is_valid()) {
assert(!r_2->is_valid(), ""); continue;
} if (r_1->is_stack()) { // Convert stack slot to an SP offset (+ wordSize to account for return address ) int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size; if (!r_2->is_valid()) { // sign extend???
__ ldrsw(rscratch2, Address(esp, ld_off));
__ str(rscratch2, Address(sp, st_off));
} else { // // We are using two optoregs. This can be either T_OBJECT, // T_ADDRESS, T_LONG, or T_DOUBLE the interpreter allocates // two slots but only uses one for thr T_LONG or T_DOUBLE case // So we must adjust where to pick up the data to match the // interpreter. // // Interpreter local[n] == MSW, local[n+1] == LSW however locals // are accessed as negative so LSW is at LOW address
// ld_off is MSW so get LSW constint offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
next_off : ld_off;
__ ldr(rscratch2, Address(esp, offset)); // st_off is LSW (i.e. reg.first())
__ str(rscratch2, Address(sp, st_off));
}
} elseif (r_1->is_Register()) { // Register argument Register r = r_1->as_Register(); if (r_2->is_valid()) { // // We are using two VMRegs. This can be either T_OBJECT, // T_ADDRESS, T_LONG, or T_DOUBLE the interpreter allocates // two slots but only uses one for thr T_LONG or T_DOUBLE case // So we must adjust where to pick up the data to match the // interpreter.
// this can be a misaligned move
__ ldr(r, Address(esp, offset));
} else { // sign extend and use a full word?
__ ldrw(r, Address(esp, ld_off));
}
} else { if (!r_2->is_valid()) {
__ ldrs(r_1->as_FloatRegister(), Address(esp, ld_off));
} else {
__ ldrd(r_1->as_FloatRegister(), Address(esp, next_off));
}
}
}
__ mov(rscratch2, rscratch1);
__ push_cont_fastpath(rthread); // Set JavaThread::_cont_fastpath to the sp of the oldest interpreted frame we know about; kills rscratch1
__ mov(rscratch1, rscratch2);
// 6243940 We might end up in handle_wrong_method if // the callee is deoptimized as we race thru here. If that // happens we don't want to take a safepoint because the // caller frame will look interpreted and arguments are now // "compiled" so it is much better to make this transition // invisible to the stack walking code. Unfortunately if // we try and find the callee by normal means a safepoint // is possible. So we stash the desired callee in the thread // and the vm will find there should this case occur.
Register holder = rscratch2; Register receiver = j_rarg0; Register tmp = r10; // A call-clobbered register not used for arg passing
// ------------------------------------------------------------------------- // Generate a C2I adapter. On entry we know rmethod holds the Method* during calls // to the interpreter. The args start out packed in the compiled layout. They // need to be unpacked into the interpreter layout. This will almost always // require some stack space. We grow the current (compiled) stack, then repack // the args. We finally end in a jump to the generic interpreter entry point. // On exit from the interpreter, the interpreter will restore our SP (lest the // compiled code, which relies solely on SP and not FP, get sick).
__ bind(ok); // Method might have been compiled since the call site was patched to // interpreted; if that is the case treat it as a miss so we can get // the call site corrected.
__ ldr(rscratch1, Address(rmethod, in_bytes(Method::code_offset())));
__ cbz(rscratch1, skip_fixup);
__ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
__ block_comment("} c2i_unverified_entry");
}
address c2i_entry = __ pc();
// Class initialization barrier for static methods
address c2i_no_clinit_check_entry = NULL; if (VM_Version::supports_fast_class_init_checks()) {
Label L_skip_barrier;
uint int_args = 0;
uint fp_args = 0;
uint stk_args = 0; // inc by 2 each time
for (int i = 0; i < total_args_passed; i++) { switch (sig_bt[i]) { case T_BOOLEAN: case T_CHAR: case T_BYTE: case T_SHORT: case T_INT: if (int_args < Argument::n_int_register_parameters_c) {
regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
} else { #ifdef __APPLE__ // Less-than word types are stored one after another. // The code is unable to handle this so bailout. return -1; #endif
regs[i].set1(VMRegImpl::stack2reg(stk_args));
stk_args += 2;
} break; case T_LONG:
assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half"); // fall through case T_OBJECT: case T_ARRAY: case T_ADDRESS: case T_METADATA: if (int_args < Argument::n_int_register_parameters_c) {
regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
} else {
regs[i].set2(VMRegImpl::stack2reg(stk_args));
stk_args += 2;
} break; case T_FLOAT: if (fp_args < Argument::n_float_register_parameters_c) {
regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
} else { #ifdef __APPLE__ // Less-than word types are stored one after another. // The code is unable to handle this so bailout. return -1; #endif
regs[i].set1(VMRegImpl::stack2reg(stk_args));
stk_args += 2;
} break; case T_DOUBLE:
assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half"); if (fp_args < Argument::n_float_register_parameters_c) {
regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
} else {
regs[i].set2(VMRegImpl::stack2reg(stk_args));
stk_args += 2;
} break; case T_VOID: // Halves of longs and doubles
assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
regs[i].set_bad(); break; default:
ShouldNotReachHere(); break;
}
}
int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
VMRegPair *regs,
VMRegPair *regs2, int total_args_passed)
{ int result = c_calling_convention_priv(sig_bt, regs, regs2, total_args_passed);
guarantee(result >= 0, "Unsupported arguments configuration"); return result;
}
void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { // We always ignore the frame_slots arg and just use the space just below frame pointer // which by this time is free to use switch (ret_type) { case T_FLOAT:
__ strs(v0, Address(rfp, -wordSize)); break; case T_DOUBLE:
__ strd(v0, Address(rfp, -wordSize)); break; case T_VOID: break; default: {
__ str(r0, Address(rfp, -wordSize));
}
}
}
void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { // We always ignore the frame_slots arg and just use the space just below frame pointer // which by this time is free to use switch (ret_type) { case T_FLOAT:
__ ldrs(v0, Address(rfp, -wordSize)); break; case T_DOUBLE:
__ ldrd(v0, Address(rfp, -wordSize)); break; case T_VOID: break; default: {
__ ldr(r0, Address(rfp, -wordSize));
}
}
} staticvoid save_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
RegSet x; for ( int i = first_arg ; i < arg_count ; i++ ) { if (args[i].first()->is_Register()) {
x = x + args[i].first()->as_Register();
} elseif (args[i].first()->is_FloatRegister()) {
__ strd(args[i].first()->as_FloatRegister(), Address(__ pre(sp, -2 * wordSize)));
}
}
__ push(x, sp);
}
staticvoid restore_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
RegSet x; for ( int i = first_arg ; i < arg_count ; i++ ) { if (args[i].first()->is_Register()) {
x = x + args[i].first()->as_Register();
} else {
;
}
}
__ pop(x, sp); for ( int i = arg_count - 1 ; i >= first_arg ; i-- ) { if (args[i].first()->is_Register()) {
;
} elseif (args[i].first()->is_FloatRegister()) {
__ ldrd(args[i].first()->as_FloatRegister(), Address(__ post(sp, 2 * wordSize)));
}
}
}
staticvoid verify_oop_args(MacroAssembler* masm, const methodHandle& method, const BasicType* sig_bt, const VMRegPair* regs) { Register temp_reg = r19; // not part of any compiled calling seq if (VerifyOops) { for (int i = 0; i < method->size_of_parameters(); i++) { if (sig_bt[i] == T_OBJECT ||
sig_bt[i] == T_ARRAY) {
VMReg r = regs[i].first();
assert(r->is_valid(), "bad oop arg"); if (r->is_stack()) {
__ ldr(temp_reg, Address(sp, r->reg2stack() * VMRegImpl::stack_slot_size));
__ verify_oop(temp_reg);
} else {
__ verify_oop(r->as_Register());
}
}
}
}
}
__ ldr(rscratch1, Address(rthread, JavaThread::cont_entry_offset()));
__ str(rscratch1, Address(sp, ContinuationEntry::parent_offset()));
__ mov(rscratch1, sp); // we can't use sp as the source in str
__ str(rscratch1, Address(rthread, JavaThread::cont_entry_offset()));
return map;
}
// on entry c_rarg1 points to the continuation // sp points to ContinuationEntry // c_rarg3 -- isVirtualThread staticvoid fill_continuation_entry(MacroAssembler* masm) { #ifdef ASSERT
__ movw(rscratch1, ContinuationEntry::cookie_value());
__ strw(rscratch1, Address(sp, ContinuationEntry::cookie_offset())); #endif
// i2i entry used at interp_only_mode only
interpreted_entry_offset = __ pc() - start;
{
#ifdef ASSERT
Label is_interp_only;
__ ldrw(rscratch1, Address(rthread, JavaThread::interp_only_mode_offset()));
__ cbnzw(rscratch1, is_interp_only);
__ stop("enterSpecial interpreter entry called when not in interp_only_mode");
__ bind(is_interp_only); #endif
// Read interpreter arguments into registers (this is an ad-hoc i2c adapter)
__ ldr(c_rarg1, Address(esp, Interpreter::stackElementSize*2));
__ ldr(c_rarg2, Address(esp, Interpreter::stackElementSize*1));
__ ldr(c_rarg3, Address(esp, Interpreter::stackElementSize*0));
__ push_cont_fastpath(rthread);
__ enter();
stack_slots = 2; // will be adjusted in setup
OopMap* map = continuation_enter_setup(masm, stack_slots); // The frame is complete here, but we only record it for the compiled entry, so the frame would appear unsafe, // but that's okay because at the very worst we'll miss an async sample, but we're in interp_only_mode anyway.
// Now write the args into the outgoing interpreter space bool has_receiver = false; Register receiver_reg = noreg; int member_arg_pos = -1; Register member_reg = noreg; int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid); if (ref_kind != 0) {
member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument
member_reg = r19; // known to be free at this point
has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind);
} elseif (iid == vmIntrinsics::_invokeBasic) {
has_receiver = true;
} elseif (iid == vmIntrinsics::_linkToNative) {
member_arg_pos = method->size_of_parameters() - 1; // trailing NativeEntryPoint argument
member_reg = r19; // known to be free at this point
} else {
fatal("unexpected intrinsic id %d", vmIntrinsics::as_int(iid));
}
if (member_reg != noreg) { // Load the member_arg into register, if necessary.
SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs);
VMReg r = regs[member_arg_pos].first(); if (r->is_stack()) {
__ ldr(member_reg, Address(sp, r->reg2stack() * VMRegImpl::stack_slot_size));
} else { // no data motion is needed
member_reg = r->as_Register();
}
}
if (has_receiver) { // Make sure the receiver is loaded into a register.
assert(method->size_of_parameters() > 0, "oob");
assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object");
VMReg r = regs[0].first();
assert(r->is_valid(), "bad receiver arg"); if (r->is_stack()) { // Porting note: This assumes that compiled calling conventions always // pass the receiver oop in a register. If this is not true on some // platform, pick a temp and load the receiver from stack.
fatal("receiver always in a register");
receiver_reg = r2; // known to be free at this point
__ ldr(receiver_reg, Address(sp, r->reg2stack() * VMRegImpl::stack_slot_size));
} else { // no data motion is needed
receiver_reg = r->as_Register();
}
}
// Figure out which address we are really jumping to:
MethodHandles::generate_method_handle_dispatch(masm, iid,
receiver_reg, member_reg, /*for_compiler_entry:*/ true);
}
// --------------------------------------------------------------------------- // Generate a native wrapper for a given method. The method takes arguments // in the Java compiled code convention, marshals them to the native // convention (handlizes oops, etc), transitions to native, makes the call, // returns to java state (possibly blocking), unhandlizes any result and // returns. // // Critical native functions are a shorthand for the use of // GetPrimtiveArrayCritical and disallow the use of any other JNI // functions. The wrapper is expected to unpack the arguments before // passing them to the callee. Critical native functions leave the state _in_Java, // since they block out GC. // Some other parts of JNI setup are skipped like the tear down of the JNI handle // block and the check for pending exceptions it's impossible for them // to be thrown. //
nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm, const methodHandle& method, int compile_id,
BasicType* in_sig_bt,
VMRegPair* in_regs,
BasicType ret_type) { if (method->is_continuation_native_intrinsic()) { int exception_offset = -1;
OopMapSet* oop_maps = new OopMapSet(); int frame_complete = -1; int stack_slots = -1; int interpreted_entry_offset = -1; int vep_offset = -1; if (method->is_continuation_enter_intrinsic()) {
gen_continuation_enter(masm,
method,
in_sig_bt,
in_regs,
exception_offset,
oop_maps,
frame_complete,
stack_slots,
interpreted_entry_offset,
vep_offset);
} elseif (method->is_continuation_yield_intrinsic()) {
gen_continuation_yield(masm,
method,
in_sig_bt,
in_regs,
oop_maps,
frame_complete,
stack_slots,
vep_offset);
} else {
guarantee(false, "Unknown Continuation native intrinsic");
}
#ifdef ASSERT if (method->is_continuation_enter_intrinsic()) {
assert(interpreted_entry_offset != -1, "Must be set");
assert(exception_offset != -1, "Must be set");
} else {
assert(interpreted_entry_offset == -1, "Must be unset");
assert(exception_offset == -1, "Must be unset");
}
assert(frame_complete != -1, "Must be set");
assert(stack_slots != -1, "Must be set");
assert(vep_offset != -1, "Must be set"); #endif
if (method->is_method_handle_intrinsic()) {
vmIntrinsics::ID iid = method->intrinsic_id();
intptr_t start = (intptr_t)__ pc(); int vep_offset = ((intptr_t)__ pc()) - start;
// First instruction must be a nop as it may need to be patched on deoptimisation
__ nop();
gen_special_dispatch(masm,
method,
in_sig_bt,
in_regs); int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period
__ flush(); int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually return nmethod::new_native_nmethod(method,
compile_id,
masm->code(),
vep_offset,
frame_complete,
stack_slots / VMRegImpl::slots_per_word,
in_ByteSize(-1),
in_ByteSize(-1),
(OopMapSet*)NULL);
}
address native_func = method->native_function();
assert(native_func != NULL, "must have function");
// An OopMap for lock (and class if static)
OopMapSet *oop_maps = new OopMapSet();
intptr_t start = (intptr_t)__ pc();
// We have received a description of where all the java arg are located // on entry to the wrapper. We need to convert these args to where // the jni function will expect them. To figure out where they go // we convert the java signature to a C signature by inserting // the hidden arguments as arg[0] and possibly arg[1] (static method)
int argc = 0;
out_sig_bt[argc++] = T_ADDRESS; if (method->is_static()) {
out_sig_bt[argc++] = T_OBJECT;
}
for (int i = 0; i < total_in_args ; i++ ) {
out_sig_bt[argc++] = in_sig_bt[i];
}
// Now figure out where the args must be stored and how much stack space // they require. int out_arg_slots;
out_arg_slots = c_calling_convention_priv(out_sig_bt, out_regs, NULL, total_c_args);
if (out_arg_slots < 0) { return NULL;
}
// Compute framesize for the wrapper. We need to handlize all oops in // incoming registers
// Calculate the total number of stack slots we will need.
// First count the abi requirement plus all of the outgoing args int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
// Now the space for the inbound oop handle area int total_save_slots = 8 * VMRegImpl::slots_per_word; // 8 arguments passed in registers
int oop_handle_offset = stack_slots;
stack_slots += total_save_slots;
// Now any space we need for handlizing a klass if static method
int klass_slot_offset = 0; int klass_offset = -1; int lock_slot_offset = 0; bool is_static = false;
if (method->is_synchronized()) {
lock_slot_offset = stack_slots;
stack_slots += VMRegImpl::slots_per_word;
}
// Now a place (+2) to save return values or temp during shuffling // + 4 for return address (which we own) and saved rfp
stack_slots += 6;
// Ok The space we have allocated will look like: // // // FP-> | | // |---------------------| // | 2 slots for moves | // |---------------------| // | lock box (if sync) | // |---------------------| <- lock_slot_offset // | klass (if static) | // |---------------------| <- klass_slot_offset // | oopHandle area | // |---------------------| <- oop_handle_offset (8 java arg registers) // | outbound memory | // | based arguments | // | | // |---------------------| // | | // SP-> | out_preserved_slots | // //
// Now compute actual number of stack words we need rounding to make // stack properly aligned.
stack_slots = align_up(stack_slots, StackAlignmentInSlots);
int stack_size = stack_slots * VMRegImpl::stack_slot_size;
// First thing make an ic check to see if we should even be here
// We are free to use all registers as temps without saving them and // restoring them except rfp. rfp is the only callee save register // as far as the interpreter and the compiler(s) are concerned.
// Verified entry point must be aligned
__ align(8);
__ bind(hit);
int vep_offset = ((intptr_t)__ pc()) - start;
// If we have to make this method not-entrant we'll overwrite its // first instruction with a jump. For this action to be legal we // must ensure that this first instruction is a B, BL, NOP, BKPT, // SVC, HVC, or SMC. Make it a NOP.
__ nop();
// Generate a new frame for the wrapper.
__ enter(); // -2 because return address is already present and so is saved rfp
__ sub(sp, sp, stack_size - 2*wordSize);
// Frame is now completed as far as size and linkage. int frame_complete = ((intptr_t)__ pc()) - start;
// We use r20 as the oop handle for the receiver/klass // It is callee save so it survives the call to native
constRegister oop_handle_reg = r20;
// // We immediately shuffle the arguments so that any vm call we have to // make from here on out (sync slow path, jvmti, etc.) we will have // captured the oops from our caller and have a valid oopMap for // them.
// ----------------- // The Grand Shuffle
// The Java calling convention is either equal (linux) or denser (win64) than the // c calling convention. However the because of the jni_env argument the c calling // convention always has at least one more (and two for static) arguments than Java. // Therefore if we move the args from java -> c backwards then we will never have // a register->register conflict and we don't have to build a dependency graph // and figure out how to break any cycles. //
// Record esp-based slot for receiver on stack for non-static methods int receiver_offset = -1;
// This is a trick. We double the stack slots so we can claim // the oops in the caller's frame. Since we are sure to have // more args than the caller doubling is enough to make // sure we can capture all the incoming oop args from the // caller. //
OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
// Mark location of rfp (someday) // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, vmreg(rfp));
int float_args = 0; int int_args = 0;
#ifdef ASSERT bool reg_destroyed[Register::number_of_registers]; bool freg_destroyed[FloatRegister::number_of_registers]; for ( int r = 0 ; r < Register::number_of_registers ; r++ ) {
reg_destroyed[r] = false;
} for ( int f = 0 ; f < FloatRegister::number_of_registers ; f++ ) {
freg_destroyed[f] = false;
}
#endif/* ASSERT */
// For JNI natives the incoming and outgoing registers are offset upwards.
GrowableArray<int> arg_order(2 * total_in_args);
VMRegPair tmp_vmreg;
tmp_vmreg.set2(r19->as_VMReg());
for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) {
arg_order.push(i);
arg_order.push(c_arg);
}
int temploc = -1; for (int ai = 0; ai < arg_order.length(); ai += 2) { int i = arg_order.at(ai); int c_arg = arg_order.at(ai + 1);
__ block_comment(err_msg("move %d -> %d", i, c_arg));
assert(c_arg != -1 && i != -1, "wrong order"); #ifdef ASSERT if (in_regs[i].first()->is_Register()) {
assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "destroyed reg!");
} elseif (in_regs[i].first()->is_FloatRegister()) {
assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding()], "destroyed reg!");
} if (out_regs[c_arg].first()->is_Register()) {
reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
} elseif (out_regs[c_arg].first()->is_FloatRegister()) {
freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding()] = true;
} #endif/* ASSERT */ switch (in_sig_bt[i]) { case T_ARRAY: case T_OBJECT:
__ object_move(map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
((i == 0) && (!is_static)),
&receiver_offset);
int_args++; break; case T_VOID: break;
case T_FLOAT:
__ float_move(in_regs[i], out_regs[c_arg]);
float_args++; break;
// point c_arg at the first arg that is already loaded in case we // need to spill before we call out int c_arg = total_c_args - total_in_args;
// Pre-load a static method's oop into c_rarg1. if (method->is_static()) {
// load oop into a register
__ movoop(c_rarg1,
JNIHandles::make_local(method->method_holder()->java_mirror()));
// Now handlize the static class mirror it's known not-null.
__ str(c_rarg1, Address(sp, klass_offset));
map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
// Now get the handle
__ lea(c_rarg1, Address(sp, klass_offset)); // and protect the arg if we must spill
c_arg--;
}
// Change state to native (we save the return address in the thread, since it might not // be pushed on the stack when we do a stack traversal). // We use the same pc/oopMap repeatedly when we call out
// RedefineClasses() tracing support for obsolete method entry if (log_is_enabled(Trace, redefine, class, obsolete)) { // protect the args we've loaded
save_args(masm, total_c_args, c_arg, out_regs);
__ mov_metadata(c_rarg1, method());
__ call_VM_leaf(
CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
rthread, c_rarg1);
restore_args(masm, total_c_args, c_arg, out_regs);
}
// Lock a synchronized method
// Register definitions used by locking and unlocking
constRegister swap_reg = r0; constRegister obj_reg = r19; // Will contain the oop constRegister lock_reg = r13; // Address of compiler lock object (BasicLock) constRegister old_hdr = r13; // value of old header at unlock time constRegister tmp = lr;
Label slow_path_lock;
Label lock_done;
if (method->is_synchronized()) {
Label count; constint mark_word_offset = BasicLock::displaced_header_offset_in_bytes();
// Get the handle (the 2nd argument)
__ mov(oop_handle_reg, c_rarg1);
// Get address of the box
--> --------------------
--> maximum size reached
--> --------------------
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