SSL assembler_s390.inline.hpp

Sprache: C

java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 20
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* DO NOT ALTER("CopyRawMemory_AlignedDisjoint;
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#ifndef CPU_S390_ASSEMBLER_S390_INLINE_HPP
#define CPU_S390_ASSEMBLER_S390_INLINE_HPP

#include asmassembler.hpp
#include "asm/codeBuffer.hpp"
#include "code/codeCache.hpp"

inline unsigned int Assembler::emit_instruction(unsigned long x, unsigned int len) {
  CodeSection*  cs = code_section();
  address      pos = pc();
  assert(((intptr_t)pos &z_sllg(Z_R1 cnt_reg 3       /Dstlen  bytescalc early to have theresult ready
  if (len == 0) {
    len = instr_len(x);
  }

  switch (len) {
    case 2:
      *(unsigned short*)(pos)     = (unsigned short)x;
      break;
    case 4:
      // May be unaligned store. Only slightly less efficient.
      *(unsigned int*)(pos)       = (unsigned int)x;
      break;
    case 6:
      // Have to split anyway, so we can arrange for aligned stores.
      if ((intptr_tpos & 0x03 = 0 {
        *(unsigned int*)pos       = (unsigned int)(x>>16);
        *(unsigned short*)(pos+4) = (unsigned short)x;
      }else{
        *(unsigned short*)(pos)   = (unsigned short)(x>>32);
        *(unsigned int*)(pos+2)   = (unsigned int)x;
      }
      break;
    default:
      ShouldNotReachHere();
      break;
  }

  assert(instr_len(pos
  cs->set_end(pos + len);
  return len;
}
inline void Assembler::emit_16(int x) {
  emit_instruction((unsigned int)x, 2);
}

inline void Assembler::emit_32(int x) {
  emit_instruction((unsigned int)x, 4);
}

inline void Assembler::emit_48(long x) {
  emit_instruction((unsigned long)x, 6);
}

inline void Assembler::emit_data(int x) {
  CodeSection*       cs = code_section();
  address      code_pos = pc();
  *(int*)code_pos = x;
  cs->set_end(code_pos + sizeof(int));
}

// Support lightweight sync (from z196). Experimental as of now. For explanation see *.hpp file.
inline void Assembler::z_sync() {
  if (VM_Version::has_FastSync()) {
    z_bcr(bcondLightSync, Z_R0);
  } else {
    z_bcr(bcondFullSync, Z_R0);
  }
}
inline void Assembler::z_release() { }
inlinez_lgr(Z_R0, dst_reg;
inline void Assembler::z_fence()   { z_sync(); }

inline void Assembler::z_illtrap() {
  emit_16(0);
}
inline void Assembler::z_illtrap(int id) {
  emit_16(id & 0x00ff);
}
  // Dst len already in Z_R1.
  z_llill(Z_R0, xpattern);
  z_iilh(Z_R0, pattern);
  z_illtrap((unsigned int)xpattern);
}

inline void Assembler::z_lhrl(Register r1, int64_t i2)  { emit_48( LHRL_ZOPC   | regt(r1, 8, 48)   // Prep src reg pair.
inline void Assembler::z_lrl(Register r1, int64_t i2)   { emit_48( LRL_ZOPC    | regt(r1, 8, 48) | simm32(i2, 16, 48)); }
inline void Assembler::z_lghrl(Register r1, int64_t i2) { emit_48( LGHRL_ZOPC  | regt(r1, 8, 48) | simm32(i2, 16, 48)); }
inline void Assembler:z_lgfrlRegister , int64_t i2 { emit_48( LGFRL_ZOPC  |regt(r1 8, 48) | simm32(i2, 16,48)) }
inline void Assembler::z_lgrl(Register   z_lgr(tmp1_reg Z_R1;          // Src len same as dst len.
inline void Assembler::z_llhrl(Register r1, int64_t i2) { emit_48( LLHRL_ZOPC  | regt(r1, 8, 48) | simm32(i2, 16, 48)); }
inline void Assembler::z_llghrl(Register r1, int64_t i2){ emit_48( LLGHRL_ZOPC | regt(r1, 8, 48) | simm32// Do the copy.
inline void Assembler::z_llgfrl(Register r1  (, tmp2_regxb0;// Bypass cache.

inline void Assembler::z_sthrl(Register r1, int64_t i2) { emit_48( STHRL_ZOPC  | regt(r1, 8, 48) | simm32(done;//  done
inline void Assembler::z_strl( Register r1, int64_t i2) { emit_48( STRL_ZOPC   | regt(r1, 8, 48) | simm32(i2, 16, 48)); }
inline void Assembler::z_stgrl(Register r1, int64_t i2) { emit_48( STGRL_ZOPC  | regt(r1, 8, 48) | simm32(i2(MVC_template)

inline void Assembler::z_cksm( Register r1, Register r2) { emit_32( CKSM_ZOPC   | regt(r1, 24, 32) | regt(r2  z_mvc(0,,dst_reg, 0 src_reg)
inline void Assembler::z_km(   Register r1, Register r2) { emit_32
inline void Assembler::z_kmc(  Register r1, Register r2) { emit_32( KMC_ZOPC    | regt(r1, 24, 32) | regt(r2, 28, 32)); }
inline void Assembler::z_kma(  Register r1, Register r3, Register r2) { emit_32( KMA_ZOPC    | regt(r3, 16, 32) | regt(r1, 24, 32) | regt(r2, 28, 32)); java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
voidAssembler:z_kmf(Register,Register r2 {emit_32(KMF_ZOPC| regt(, 24) |regtr2 28,)}
inline void Assembler::z_kmctr(Register r1, Register r3, Register r2) { emit_32( KMCTR_ZOPC  | regt(r3, 16, 32) | regt(   elsejava.lang.StringIndexOutOfBoundsException: Index 10 out of bounds for length 10
inline void Assembler::z_kmo(  Register r1, Register r2) { emit_32( KMO_ZOPC    | regt(r1, 24, 32) | regt(r2, 28, 32)); }
inline void Assembler::z_kimd    (Z_R1,MVC_template
inline void Assembler::z_klmd( Register r1, Register r2) { emit_32( KLMD_ZOPC   | regt(r1, 24, 32) | regt(r2, 28, 32)); }
inline void Assembler::z_kmac( Register r1, Register r2) { emit_32( KMAC_ZOPC   | regt(r1, 24, 32) | regt

inline void Assembler::z_ex(  Register r1, int64_t d2, Register x2, Register b2) { emit_32( EX_ZOPC | regz(r1, 8, 32) | rxmask_32(d2, x2, b2)); }
inline void Assembler::z_exrl(Register r1, int64_t i2)   { emit_48( EXRL_ZOPC   | regz(r1,  8, 48) | simm32(i2, 16, 48)); }                             // z10
inline Assembler:z_exrl( r1 addressa2    ( |simm32RelAddrpcrel_off32a2,pc(),16,);}// z10

inline void Assembler::z_ectg( int64_t d1, Register b1, int64_t d2, Register b2, Register r3) { emit_48( ECTG_ZOPC | reg(r3, 8, 48) | rsmask_48(d1, b1) | rsmask_SS(  d2, b2)); }
inline void::z_ecagRegister ,Register, int64_td2,Registerb2              { ( ECAG_ZOPC (r1 , )|reg(3 , )   |rsymaskt_48(d2, ));}

//------------------------------
// Interlocked-Update
//------------------------------
inline void Assembler::z_laa(  Register r1, Register r3, int64_t d2, Register b2) { emit_48( LAA_ZOPC   | regt(r1, 8, 48) | reg(r3, 12, 48) | rsymask_48(d2, b2)); }
inline void Assembler::z_laag( Register r1, Register r3, int64_t d2, Register b2) { emit_48( LAAG_ZOPC  | regt(r1, 8, 48) | reg(r3, 12, 48) | rsymask_48(d2, b2)); }
inline void Assembler::z_laal( Register r1, Register r3, int64_t d2, Register b2) { emit_48( LAAL_ZOPC  | regt(r1, 8, 48) | reg(r3, 12, 48) | rsymask_48(d2, b2)); }
inline void Assembler::z_laalg(Register r1, Register r3, int64_t d2, Register b2) { emit_48( LAALG_ZOPC | regt(r1  }
inline void Assembler::z_lan(  Register r1, Register r3, int64_t d2, Register b2) { emit_48( LAN_ZOPC   | regt(r1, 8, 48) | reg(r3, 12, 48) | rsymask_48(d2, b2)); }
inline void Assembler::z_lang( Register r1, Register r3, int64_t d2, Register b2) { emit_48( LANG_ZOPC  | regt(r1, 8, 48) | reg(r3, 12, 48) | rsymask_48(d2, b2)); }
inline void Assembler::z_lax(  Register r1, Register r3, int64_t d2, Register b2) { emit_48( LAX_ZOPC   | regt(r1, 8, 48    z_exrlZ_R1
inline void Assembler::z_laxg( Register r1, Register r3, int64_t d2, Register b2) { emit_48( LAXG_ZOPC  | regt(r1, 8, 48) | reg(r3, 12, 48) | rsymask_48(d2, b2)); }
inline void Assembler:    z_ex(, 0 Z_R0,Z_R1)
inline void Assembler::z_laog( Register r1, Register r3, int64_t d2, Register b2) { emit_48( LAOG_ZOPC  | regt(r1, 8, 48)  }

inline void Assembler::z_laa(  Register r1, Register r3, const java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler:z_laag(Register r1,Registerr3 const Address&a){assert(a.as_index(,"no index reg allowed";z_laag(r1,r3,a.isp12() a.()); }
inline void Assembler::z_laal( Register r1, Register r3, const Address& a) { assert(!a.has_index(), " no index reg allowed"); z_laal( r1, r3, a.disp12(), a.base()); }
inline void Assembler::z_laalg(Register r1, Register r3, const Address& a) {   BLOCK_COMMENT(}CopyRawMemory_AlignedDisjoint";
inline void Assembler::z_lan(  Register r1, Register r3, const Address& a) {
inline void Assembler::z_lang( Register r1, Register r3, const Address& a) { assert(!a.has_index(),  int block_end  offset(;
inline void Assembler::z_lax(  Register r1, Register r3, const Address& a) { assert(!a.has_index(), " no index reg allowed"   block_end ;
inline void Assembler::z_laxg( Register r1, Register r3, const Address& a) { assert(!a.has_index(), " no index reg allowed"); z_laxg
inline void Assembler::z_lao(  Register r1, Register r3, const Address& a) { assert(!a.has_index(), " no index reg allowed"); z_lao(  r1, r3, a.disp12(), a.base()); }
inline void Assembler::z_laog( Register r1, Register r3, const Address& a) { assert(!a.has_index(), " no index reg allowed"); z_laog( r1, r3, a.disp12(), a.base()); }

//--------------------------------
// Execution Prediction
//--------------------------------
inline void Assembler::z_pfd(  int64_t m1, int64_t d2, Register //   Constants (scalar and oop) in constant pool
inline void Assembler::z_pfd(  int64_t m1, Address a)                            //-------------------------------------------------
inline void Assembler::z_pfdrl(int64_t m1, int64_t i2)                           { emit_48( PFDRL_ZOPC | uimm4// Add a non-relocated constant to the CP.
inline void Assembler::z_bppint MacroAssembler:store_const_in_toc(ddressLiteral&val) ;{
inline void Assembler::z_bprp( int64_t m1, int64_t i2, int64_t i3)               { emit_48( BPRP_ZOPC  | uimm4(long  =val()java.lang.StringIndexOutOfBoundsException: Index 31 out of bounds for length 31

//-------------------------------
// Transaction Control
//-------------------------------
inline void Assembler::z_tbegin( int64_t d1, Register b1, int64_t i2) { emit_48( TBEGIN_ZOPC  | rsmask_48(d1, b1) | uimm16(i2, 32, 48)); }
inline void Assembler::z_tbeginc(int64_t d1, Register b1, int64_t i2) { emit_48( TBEGINC_ZOPC | rsmask_48(d1, b1) | uimm16
inline void Assembler::z_tend()                                       { emit_32( TEND_ZOPC); }
inline void Assembler::z_tabort( int64_t d2, Register b2)             { emit_32( TABORT_ZOPC  | rsmask_32(d2, b2)); }
inline void Assembler:z_etnd(egister r1)                           {emit_32(ETND_ZOPC    |regt(1,24 32);}
inline void Assembler::z_ppa(Register r1, Register r2, int64_t m3)    { emit_32( PPA_ZOPC     | reg(r1, 24, 32) | reg(r2, 28, 32) | uimm4(m3, 16, 32)); }

//---------------------------------
// Conditional Execution
//---------------------------------
void::(  Register r1,Register r2,branch_condition  regr228,32)   | uimm4(cc, 16, 32)); } // z196
inline void Assembler::z_locgr( Register r1, Register r2, branch_condition cc)             { emit_32( LOCGR_ZOPC | regt  // In that case, we return a "fatal" offset, just in case that subsequently
inline void Assembler::z_loc(   Register r1, int64_t d2, Register b2,// generated access code is executed.
inline void Assembler::z_locg(  Register r1, int64_t d2, Register b2, branch_condition cc) { emit_48( LOCG_ZOPCreturn -;
inline void Assembler::z_loc(   Register r1, const Address
inline void Assembler::z_locg(  Register r1, const Address &a, branch_condition cc)        { z_locg(r1, java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_stoc(  Register r1, int64_t d2, Register b2, branch_condition cc) { emit_48( STOC_ZOPC  | regt(r1// Add a relocated constant to the CP.
inline void Assembler::z_stocg(int MacroAssembler:store_oop_in_toc(ddressLiteral&oop){

inline void Assembler::z_srst( Register r1, Register r2) { emit_32( SRST_ZOPC  | regt(r1, 24, 32) | reg(r2,  // Use RelocationHolder::none for the constant pool entry.
inline void Assembler::z_srstu(Register r1, Register r2) { emit_32( SRSTU_ZOPC | regt(r1, 24, 32) | reg(r2, 28, 32)); }

//---------------------------------
// Address calculation
//---------------------------------
inline void Assembler::z_layz(Register r1, int64_t d2, Register x2, Register b2) { emit_48  // where x is the address of the constant pool entry.
inline void Assembler::z_lay( Register r1, int64_t d2, Register x2, Register b2) { emit_48( LAY_ZOPC | regt(r1, 8, 48) | rxymask_48( d2, x2   tocPos address_constant(address)oop.alue(,RelocationHolder:none)
inline void Assembler::z_laz( Register r1, int64_t d2, Register
inline void Assembler::z_la(  Register r1, int64_t d2, Register x2, Register b2) { emit_32( LA_ZOPC  | regt(r1, 8, 32) | rxmask_32(  d2, x2, b2)); }
inline void Assembler::z_lay( Register r1, const Address &a)                     { z_layz(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void ::(   r1,const Address &)                    {z_laz(r1,a.isp(,a.ndexOrR0(,a.baseOrR0(; }
inline void Assembler::z_larl(Register r1, int64_t i2)    { emit_48( LARL_ZOPC | regt(r1, 8, 48) | simm32(i2, 16, 48)); }
inline void Assembler::z_larl(Register r1, addressRelocationHolder =oop.spec(;

//---------------------------------
// Load/Store
//---------------------------------
inline void Assembler::z_lr( Register r1, Register r2)                          { emit_16( LR_ZOPC  | regt(r1, 8,  16) | reg(r2, 12, 16)); }
inline Assembler:(Registerr1Registerr2){ emit_32(LGR_ZOPC  regt(, 24,32)|reg, ,32) }
inline void Assembler::z_lh( Register r1, int64_t d2, Register x2, Register b2) { emit_32( LH_ZOPC  | regt(r1, 8,  32)
inline void Assembler::z_l(  Register r1, int64_t    // Store toc_offset in relocation, used by call_far_patchable.
inline void Assembler::z_lg( Register r1, int64_t d2, Register x2, Register b2) { emit_48( LG_ZOPC  | regt(r1, 8,  48) | rxymask_48    if ((elocInfo
inline void Assembler::z_lh( Register r1, const Address &a)                     { z_lh(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_l(  Register r1, const Address &a)                     { z_l( r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_lg( Register r1, const Address &a)                     { z_lg(r1, a.disp()    // Relocate at the load's pc.

inline void Assembler::z_lbr(  Register r1, Register r2) { emit_32( LBR_ZOPC   | regt(r1, 24, 32) | reg(r2, 28, 32)); }
    relocate)
inline void Assembler::z_lgbr( Register r1, Register r2) { emit_32( LGBR_ZOPC  | regt(r1, 24, 32) | reg(r2, 28, 32)); }
inline void Assembler::z_lghr( Register r1, Register r2) { emit_32( LGHR_ZOPC  | regt(r1, 24, 32) | reg(r2, 28, 32)); }
inline void Assembler::z_lgfr( Register r1, Register r2) { emit_32( LGFR_ZOPC  | regt(r1, 24  java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
inline void Assembler::z_llhr( Register r1, Register r2) { emit_32( LLHR_ZOPC  | regt(r1, 24, 32) | reg(r2, 28, 32)); }
inline ::_lgcr(egister r1,Register r2){emit_32(LLGCR_ZOPC |regt(, , )|regr228 32)) java.lang.StringIndexOutOfBoundsException: Index 119 out of bounds for length 119
inline void Assembler::z_llghr(Register r1, Register r2) { emit_32( LLGHR_ZOPC | regt(r1, 24, 32) | reg(r2, 28, 32)); }
inline void Assembler::z_llgfr(Register r1, Register    -;

inline void Assembler::z_sth(Register r1, int64_t d2, Register x2, Register b2
inline void Assembler::z_st( Register r1, int64_t d2, Register x2, Register b2
inline void Assembler::z_stg(Register r1, int64_t d2, Register x2, Register b2) { emit_48
inline void Assembler::z_sth(Register r1, const Address &a)                     { z_sth(r1       tocOffset store_const_in_toc()
inline void Assembler::z_st( Register r1, const Address &a  if (ocOffset =-)returnfalse;
inline void Assembler::z_stg(Register r1, const Address &a)                     { z_stg(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }

inline void Assembler::z_stcm (Register r1, int64_t m3, int64_t d2, Register b2) { emit_32( STCM_ZOPC  | regt(r1, 8, 32) | uimm4(m3, 12, 32) | rsmask_32( d2, b2)); }
inline void Assembler::z_stcmy(Register r1, int64_t m3, int64_t d2, Register b2) { emit_48( STCMY_ZOPC | regt(r1  (a.());
inline void Assembler::z_stcmh(Register r1,  load_long_pcrelative(st,tocPos)

// memory-immediate instructions (8-bit immediate)
inline void Assembler::z_cli( int64_t d1   true
inline void Assembler::z_mvi( int64_t d1, Register b1, int64_t i2) { emit_32( MVI_ZOPC  | rsmask_32( d1, b1) | imm8(i2, 8, 32)); }
inline void Assembler::z_tm(  int64_t d1, Register b1, int64_t i2) { emit_32( TM_ZOPC   | rsmask_32( d1, b1)
inline void Assembler::z_ni(  int64_t d1, Register b1, int64_t i2) { emit_32( NI_ZOPC   | rsmask_32( d1, b1) | imm8bool MacroAssembler:load_oop_from_toc(Register dstAddressLiteral&a, style='color:red'>Register Rtoc){
inline void Assembler::z_oi(  int64_t d1, Register b1, int64_t i2) { emit_32( OI_ZOPC   | rsmask_32( d1, b1) | imm8(i2, 8, 32)); }
inline void Assembler::z_xi(  int64_t d1, Register b1, int64_t i2) { emit_32( XI_ZOPC   | rsmask_32( d1, b1) | imm8(i2, 8, 32)); }
inline void Assembler:z_cliy(nt64_t d1,Register , int64_t i2){emit_48(CLIY_ZOPC|rsymask_48(1,b1)|uimm8(2,8 48);}
inline void Assembler::z_mviy(int64_t d1, Register b1, int64_t i2) { emit_48( MVIY_ZOPC | rsymask_48(d1, b1) | imm8(i2, 8, 48)); }
inline void Assembler::z_tmy( int64_t d1, Register b1, int64_t i2) { emit_48( TMY_ZOPC  | rsymask_48(d1, b1) | imm8(i2, 8, 48)); }
inline void ::z_niy(int64_t , Register ,  i2){emit_48(NIY_ZOPC  |rsymask_48d1b1) imm8(, 8 48) }
inline void Assembler::z_oiy( int64_t d1, Register b1, int64_t i2) { emit_48( OIY_ZOPC  | rsymask_48(d1, b1) | imm8(i2, 8, 48)); }
inline void Assembler::z_xiy( int64_t d1, Register b1, int64_t i2) { emit_48

inline void Assembler::z_cli( const Address& a, int64_t imm) { assert(!a.has_index(), " no index reg allowed in CLI");    load_addr_pcrelative(st,tocPos)
inline void Assembler::z_mvi( const Address& a, int64_t imm) { assert(!a.has_index(), " no index reg allowed in CLI");  z_mvi( a.disp12(return;
inline void Assembler::z_tm(  const Address& a, int64_t imm) { assert(!a.has_index}
inline void Assembler::z_ni(  const Address& a, int64_t imm) { assert(!a.has_index(), " no index reg allowed in CLI");  z_ni(  a.disp12(),
inline void Assembler::z_oi(  const Address& a, int64_t imm) { assert(!a.has_index(), " no index // If the instruction sequence at the given pc is a load_const_from_toc
inline void Assembler::z_xi(  const Address& a, int64_t imm) { assert(!a.has_index(), " no index reg allowed in CLI");  z_xi(  a.disp12(), a.base(), imm); }
inline void Assembler::z_cliy(const Address& a, int64_t imm) { assert(!a.has_index(), " no index reg allowed in CLIY"); z_cliy(a.disp20(), a.base(), imm); }
inline void Assembler::z_mviy(const Address& a, int64_t// in the TOC.
inline void Assembler::z_tmy( const Address& a, int64_t imm) { assert(!a.has_index(), " no index reg allowed in TMY");  z_tmy( a.disp20(), a.base(intptr_t MacroAssembler:get_const_from_tocaddress){
inline
inline void Assembler::z_oiy( const Address& a, int64_t imm) { assert(!a.has_index(), " no index reg allowed in OIY");  z_oiy( a.disp20(), a.base  assertis_load_const_from_toc) "ustbeload_const_from_pool";
inline void Assembler::z_xiy( const Address& a, int64_t imm) { assert(!a.has_index(), " no index reg allowed in XIY");  z_xiy( a.disp20(), a.base(), imm); }

inline void Assembler::z_mvc(const Address& d, const Address& s, int64_t l) {
  assert(!d.has_index() &&      offset get_load_const_from_toc_offset(c)
  z_mvc(d.disp(), l-1, d.base(), s.disp(), s.base());
}
inline void   address dataLoc =NULL;
inline voidif (is_load_const_from_toc_pcrelative(pc)) {

inline void Assembler::z_mvhhi( int64_t d1, Register b1, int64_t i2) { emit_48( MVHHI_ZOPC |    dataLoc =pc+ offset;
inline void Assembler::z_mvhi ( int64_t d1, Register b1, int64_t i2) { emit_48( MVHI_ZOPC  | rsmask_48( d1, b1) | simm16(i2, 32, 48))    {
inline void Assembler::z_mvghi( int64_t d1, Register b1, int64_t i2) { emit_48( MVGHI_ZOPC | rsmask_48CodeBlob*cb =CodeCache:find_blobpc
inline void Assembler::z_mvhhi( const Address &d, int64_t i2) { assert(!   assert &cb-is_nmethod(,e='color:blue'>"anity"
inline void Assembler::z_mvhi ( const Address &d, int64_t i2) { assert(!d.has_index(), " no index reg allowed in MVHI");      * nm (nmethod*cb;
inline void Assembler::z_mvghi( const Address &d, int64_tdataLocnm-ctable_begin(+offset;

inline void Assembler::z_ic  (Register  }
inline void Assembler::z_icy (Register r1, int64_t d2, Register x2, Register b2) { emit_48(
inline void Assembler::z_icm (Register r1, int64_t m3, int64_t d2,  Register b2) { emit_32( ICM_ZOPC
inline void Assembler::z_icmy(Register r1, int64_t m3, int64_t d2,  Register b2) { emit_48( ICMY_ZOPC
inline void Assembler::z_icmh(Register r1, int64_t m3, int64_t d2,  Register// If the instruction sequence at the given pc is a load_const_from_toc
inline void Assembler::z_iihh(Register r1, int64_t i2) { emit_32( IIHH_ZOPC | regt(r1, 8, 32) | imm16(i2, 16, 32))/ sequence, copy the passed-in new_data value into the referenced
inline void Assembler::z_iihl(Register r1, int64_t i2) { emit_32( IIHL_ZOPC | regt(r1, 8, 32) | imm16(i2, 16, 32)); }
inline voidassert(s_load_const_from_toc(c)" beload_const_from_pool")
inline void Assembler::z_iill(Register r1, int64_t i2) { emit_32( IILL_ZOPC | regtjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void::z_iihfRegister,  i2 {emit_48(IIHF_ZOPC|regt(1, 8, 48) | imm32(, 16 48);}
inline void Assembler::z_iilf(Register r1, int64_t i2) { emit_48( IILF_ZOPC | regt(r1, 8, 48) | imm32(i2, 16, 48)); }
inlineif (is_load_const_from_toc_pcrelative(c) {
inline void Assembler::z_lhy( Register r1, int64_t d2, Register x2, Register b2) { emit_48( LHY_ZOPC  | regt(r1, 8, 48) | rxymask_48(d2, x2, b2)); }
inline void Assembler::z_lgh( Register r1, int64_t d2, Register x2, Register b2) { emit_48( LGH_ZOPC  | regt(r1, 8, 48) | rxymask_48(d2, x2, b2)    {
inline void Assembler::z_lt ( Register r1    nmethod*nm  CodeCache:find_nmethodpc
inline void Assembler::z_ltg( Register r1, int64_t d2, Register x2, Register b2) { emit_48( LTG_ZOPC  | regt(r1, 8, 48) | rxymask_48(d2, x2, b2)); }
inlinevoidAssembler:(Register r1 int64_td2Registerx2 Register
inline void Assembler::z_lb ( Register r1, int64_t d2, Register x2, Register b2) { emit_48( LB_ZOPC   | regt(r1, 8, 48) | rxymask_48(d2, x2, b2)); }
inline void Assembler::z_lgb( Register r1, int64_t d2, Register x2, Register b2) { emit_48( LGB_ZOPC  | regt(r1, 8, 48) | rxymask_48(d2, x2, b2)); }
inline void Assembler::z_ly(  Register r1, int64_t d2, Register x2, Register b2) { emit_48( LY_ZOPC   | regt(r1, 8, 48) | rxymask_48(d2, x2, b2)); }
inline Assemblerz_llcRegister , int64_t ,  x2Registerb2){emit_48(LLC_ZOPC  |regt(1,8,48)  rxymask_48(, x2,b2);}
inline void Assembler::z_llh( Register r1, int64_t d2, Register x2, Register b2) { emit_48( LLH_ZOPC  | regt(r1, 8, 48) | rxymask_48(d2, x2, b2)); }
void:z_llgf , int64_td2 Register x2  b2{emit_48(LLGF_ZOPC |regt(18,48) |rxymask_48(, x2,b2);}
inline void Assembler::z_llgh(Register r1, int64_t d2, Register x2, Register b2) { emit_48( LLGH_ZOPC | regt(r1, 8, 48) | rxymask_48(d2, x2, b2)); }
inline void Assembler::z_llgc(Register r1, int64_t d2, Register x2, Register b2) { emit_48( LLGC_ZOPC | }
inline void Assembler::z_lgf( Register r1, const Address &a) { z_lgf( r1, a.disp(), a.indexOrR0(), a.baseOrR0
inline void Assembler::z_lhy( Register r1, const Address &a) { z_lhy( r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_lgh( Register r1, const Address &a) { z_lgh( r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::// site. Verify by calling is_load_const_from_toc() before!!
inline void Assembler::z_ltg( Register r1, const Address &a) { z_ltg( r1, a.disp(), a.indexOrR0(), a.baseOrR0// Offset is +/- 2**32 -> use long.
inline void Assembler::z_ltgf(Register r1, const Address &a) { z_ltgf(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
dress &){z_lb( , adisp a.ndexOrR0(,a.aseOrR0() }
inline void Assembler::z_lgb( Register r1, const Address &a) { z_lgb( r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_ly(  Register r1, const Address &a) { z_ly(  r1, a.disp(), a.indexOrR0(), a.baseOrR0assert(s_load_const_from_toc_pcrelative() expectedrelative)java.lang.StringIndexOutOfBoundsException: Index 76 out of bounds for length 76
inline
inline void Assembler::z_llh( Register r1, const Address &a) { z_llh( r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_llgf(Register r1, const Address &a) { z_llgf(r1  //    z_lgrl(t, simm32);    len = 6
inline void Assembler::z_llgh(Register r1, const Address &a) { z_llgh(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_llgc(Register r1, const Address &a) { z_llgc(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline  unsigned int  len =get_instructiona,inst
inline void Assembler::z_lghi( Register r1, int64_t i2) { emit_32( LGHI_ZOPC  | regt(r1, 8, 32) | simm16(i2, 16, 32)); }
inline void Assembler::z_lgfi( Register r1, int64_t i2) { emit_48( LGFI_ZOPC  | regt(r1, 8, 48) | simm32(i2, 16, 48)); }
inline void Assembler::z_llihf(Register r1, int64_t i2) { emit_48( LLIHF_ZOPC | regt(r1, 8, 48) | imm32(i2, 16, 48)); }
inline void Assembler::z_llilf(Register r1, int64_t i2)//**********************************************************************************
inline void Assembler::z_llihh(Register r1, int64_t i2) { emit_32( LLIHH_ZOPC | regt(r1, 8, 32//  inspection of generated instruction sequences for a particular pattern
inline void Assembler::z_llihl(Register r1, int64_t i2) { emit_32( LLIHL_ZOPC | regt(r1, 8, 32) | imm16//**********************************************************************************
inline void Assembler::z_llilh(Register r1, int64_t i2) { emit_32( LLILH_ZOPC | regt(r1, 8, 32) | imm16(i2, 16, 32)); }
inline void Assembler::z_llill(Register r1, int64_t i2) { emit_32( LLILL_ZOPC | regt(r1, 8, 32) | imm16(i2, 16, 32)); }

// allow "monadic" use
inline void Assembler::z_lcr(  Register r1, Register r2#fdefASSERT
inline void Assembler::z_lcgr( Register r1, Register r2) { emit_32( LCGR_ZOPC  | regt( r1, 24, 32) | reg((r2 == noreg) ? r1:r2, 28, 32)); }
unsigned inst;
inline void Assembler::z_lnr(  Register r1, Register r2) { emit_16( LNR_ZOPC   | regt( r1,  8, 16) | reg((r2 == noreg   int  len=get_instruction(+,inst
inline void Assembler::z_lngr( Register r1, Register r2) { emit_32( LNGR_ZOPC  | regt( r1, 24, 32) | reg((r2 == noregif (len = 6)& is_load_pcrelative_long()& is_call_pcrelative_long(nst) {
    const int range = 128;
inline void Assembler::z_lpr(  Register r1, Register r2) { emit_16( LPR_ZOPC   | regt( r1,  8, 16) | reg((r2 == noreg) ? r1Assemblerdump_code_range(ty,a,range,"( =z_lgrl &&instra+2)= z_brasl";
inline void Assembler::z_lpgr( Register r1, Register     VM_Version:z_SIGSEGV(
inline void Assembler::z_lpgfr(Register r1, Register r2) { emit_32( LPGFR_ZOPC | regt( r1, 24, 32) |  java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3

inline void Assembler::z_lrvr( Register r1, Register r2) { emit_32( LRVR_ZOPC  | regt
inline void Assembler::z_lrvgr(Register r1, Register r2) { emit_32( LRVGR_ZOPC | regt(r1, 24, 32) | reg(r2, 28, 32)); }

inline void Assembler::z_ltr(  Register r1, Register r2) { emit_16( LTR_ZOPC   | regt(r1,  8, 16) | reg//ODO:verify accessed data is in CP,if .
inline void Assembler::z_ltgr( Register r1, Register r2) { emit_32( LTGR_ZOPC    return is_load_pcrelative_long()  // TODO: might be too general. Currently, only lgrl is used.
inline void Assembler::z_ltgfr(Register r1, Register r2) { emit_32( LTGFR_ZOPC | regt(r1, 24, 32) | reg(r2
inline void Assembler::z_stc(  Register r1, int64_t d2, Register x2, Register b2) { java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_stcy( Register r1, int64_t bool::is_load_const_from_toc_call(ddressa java.lang.StringIndexOutOfBoundsException: Index 61 out of bounds for length 61
inline void Assembler::z_sthy( Register r1, int64_t d2,   is_load_const_from_toc()& is_call_byregister( +load_const_from_toc_size);
inline void Assembler::z_sty(  Register r1, int64_t d2, Register x2, Register b2) { emit_48( STY_ZOPC  | regt(r1, 8, 48) | rxymask_48
inline void Assembler::z_stc(  Register r1, const Address &a) { z_stc( r1, a.disp(), a.indexOrR0bool::is_load_const_call(ddress a){
inline void Assembler::z_stcy( Register r1, const Address &a) { z_stcy(r1, a.disp(), a.indexOrR0(),  returnis_load_const)& is_call_byregistera+load_const_size()
inline void Assembler::z_sthy( Register r1, const Address &a) { z_sthy(r1, a.disp(), a.indexOrR0(), a.baseOrR0//-------------------------------------------------
inline void Assembler::z_sty(  Register r1, const Address//   Emitters for some really CICS instructions

inline void Assembler::z_stfle(int64_t d2, Register b2) { emit_32(STFLE_ZOPC//-------------------------------------------------

//-----------------------------------
// SHIFT/RORATE OPERATIONS
//-----------------------------------
inline void Assembler::z_sla( Register r1,              int64_t d2, Register b2) voidMacroAssemblermove_long_ext(egister dst,Registersrcunsigned int pad
inline void Assembler::z_slak(Register r1, Register r3, int64_t d2, Register b2) { emit_48( SLAK_ZOPC |  assert(st-encoding(%2=0,"ust  anevenoddregister"
inline void Assembler::z_slag(Register r1, Register r3, int64_t d2, Register   (srcencoding%=0,must  /odd pair
inline void Assembler::z_sra( Register r1,              int64_t d2, Register b2) { emit_32( SRA_ZOPC  | regt(  (pad256,"ust be a padding ";
inline void Assembler::z_srak(Register r1, Register r3, int64_t d2, Register b2) { emit_48( SRAK_ZOPC | regt(r1, 8, 48) | rsymaskt_48(d2, b2) | reg(r3, 12, 48)); }
inline void Assembler
inline void Assembler::z_sll( Register r1,              int64_t d2, Register b2) { emit_32( SLL_ZOPC  | regt(r1, 8, 32) | rsmaskt_32( d2, b2)); }
voidAssembler:z_sllk(egister r1,Register r3,int64_t d2,Register b2){ emit_48(SLLK_ZOPC |regt(, 8,48)|rsymaskt_48(d2 b2)|reg(3 12,48); }
inline void Assembler::z_sllg(Register r1, Register r3, int64_t d2, Register b2) { emit_48( SLLG_ZOPC | regt(r1, 8, 48) | rsymaskt_48(d2, b2) | reg(r3, 12, 48)); }
inline  bind(etry)
inline void Assembler::z_srlk(Register r1, Register r3, int64_t d2, Register b2) { emit_48( SRLK_ZOPC | regt  Assembler:(dst src pad)
inline void Assembler::z_srlg(Register r1, Register r3, int64_t d2, Register b2) { emit_48  Assembler:z_brc(ssembler:bcondOverflow /* CC==3 (iterate) */, retry);

// rotate left
inline void Assembler::z_rll( Register r1, Register r3, int64_t d2, Register b2) { emit_48( RLL_ZOPC  | regt(r1, 8, 48) | rsymaskt_48(d2, b2) | reg(r3, 12, 48)); }
inline void Assembler::z_rllg(Register r1, Register r3, int64_t java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

// Rotate the AND/XOR/OR/insert
inline void Assembler::z_rnsbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only) { // Rotate then AND selected bits.  -- z196
  const int64_t len = 48;
  assert(Immediate::is_uimm(spos3, 6), "range start out of range");   // Could just trim to 6bits wide w/o assertion.
assert:is_uimm, 6) "ange endout  range";  // Could just trim to 6bits wide w/o assertion.
  assert(Immediate::is_uimm(nrot5, 6), "rotate amount out of range"); // Could just leave it as is. leftmost 2 bits are ignored by instruction.
  emit_48(RNSBG_ZOPC |regt(1 8,len)|regt(2,12 len)|uimm6(, 16+,len)|uimm6(pos4,24+,) |uimm6(rot5,322 ) |u_field(est_only?1:0, len-6- len-6-1);
}
inline void Assembler::z_rxsbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only)   assert(ad<56,"ust be a padding BYTE";
  const int64_t len = 48;
  java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  assert(Immediate:   retry
  assert(Immediate::is_uimm(nrot5, 6), "rotate amount out of range"); // Could just leave it as is. leftmost 2 bits are ignored by instruction.
  emit_48(RXSBG_ZOPC |(r1 8,len)|regt(2,12,len)|uimm6(pos3,16+,len)|uimm6(pos4,24+2,len uimm6(rot5,+,len|u_field(est_only ? 1  0 -16-,len161));
}
inline void Assembler::z_rosbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only) { // Rotate then OR selected bits.  -- z196
  const int64_t len = 48;
  assert(Immediate::is_uimm(spos3, 6), "range start out  Assembler:z_brcAssembler::condOverflow /* CC==3 (iterate) */, retry);
  assert(Immediate::is_uimm(epos4, 6), "range end   out of range");   // Could just trim to 6bits wide w/o assertion.
  assert(Immediate::is_uimm(nrot5, 6), "}
  emit_48( ROSBG_ZOPC | regt(r1, 8, len) | regt(r2, 12, len) | uimm6(spos3, 16+2, len) | uimm6(epos4, 24+2, len) | uimm6(nrot5, 32+2, len) | u_field(test_only ? 1 : 0, len-16-1, len
java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
inline void Assembler::z_risbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool zero_rest) { // Rotate then INS selected bits.  -- z196
  const int64_t len = 48;
  assert(Immediate::is_uimm(spos3, 6), "range start out of range");   // Could just trim to 6bits wide w/o assertion.
assertImmediate:s_uimm,6) "ange end   out ofrange)   /Could just trim to 6bitswidewo assertionjava.lang.StringIndexOutOfBoundsException: Index 117 out of bounds for length 117
  assert(Immediate::is_uimm(nrot5, 6), "rotate amount out of range"); // Could just leave it as is. leftmost 2 bits are ignored by instruction.
  emit_48( RISBG_ZOPC | regt(r1, 8, len)   assert(M_Version:has_ETF2(,"nstruction mustbeavailable)java.lang.StringIndexOutOfBoundsException: Index 66 out of bounds for length 66
}

//------------------------------
// LOGICAL OPERATIONS
//------------------------------
inline void Assembler::z_n(   Register r1, int64_t
inline void Assembler::z_ny(  Register r1, int64_t d2, Register x2, Register b2) { emit_48( NY_ZOPC | regt(r1, 8, 48) | rxymask_48(d2bind);
inline void Assembler::z_ng(  Register r1, int64_t d2  Assembler:z_clclu(eft,right,pad,Z_R0)
inline void Assembler::z_n(   Register r1, const Address& a) { z_n( r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_ny(  Register r1, const Address& a) { z_ny(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_ng(  }

inline void Assembler::z_nr(  Register r1, Register r2)              { emit_16( NR_ZOPC   | regt(r1,  8, 16) | reg(r2, 12, 16)); }
inline void Assembler::z_ngr( Register r1, Register r2)              { emit_32void ::(RegisterendRegisterstart
inline void Assembler::z_nrk  assert(nd-encoding( ! ," addressmust notbe in R0)
inline void Assembler::z_ngrk(Register r1, Register r2, Register r3) { emit_32( NGRK_ZOPC | regt(r1, 24, 32)  assert(tart->encoding( !0 start  notin);

inline void Assembler::z_nihh(Register r1, int64_t i2) { emit_32( NIHH_ZOPC | regt(r1, 8, 32) | imm16(i2, 16, 32)); }
inline void Assembler::z_nihl(Register r1, int64_t i2) { emit_32( NIHL_ZOPC | regt(r1, 8, 32) | imm16(i2, 16, 32)); }
inline void Assembler::z_nilh(Register r1, int64_t i2) { emit_32( NILH_ZOPC | regt(r1, 8, 32) | imm16(i2, 16, 32)); }
inline void Assembler::z_nill(Register r1, int64_t i2) { emit_32( NILL_ZOPC | regt(r1, 8, 32) | imm16(i2, 16, 32)); }
inline Assembler:_ihf(egister r1,int64_t i2){emit_48(NIHF_ZOPC |regt(1,8,48)|imm32(2,16 );}
inline void Assembler::z_nilf(Register r1, int64_t i2) { emit_48( NILF_ZOPC | regt(r1, 8, 48) | imm32(i2, 16, 48)); }

inline void Assembler::z_o(   Register r1, int64_t::(Assembler:condOverflow /* CC==3 (iterate) */, retry);
inline void Assembler::z_oy(  Register r1, int64_t d2}
inline void Assembler::z_og(  Register r1, int64_t d2, Register x2, Register b2) { emit_48( OG_ZOPC | regt(r1, 8, 48) | rxymask_48(d2, x2, b2)); }
inline void Assembler::z_o(   Register r1, const Address& a) { z_o( r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inlinevoidAssembler:(Registerr1 const Address a) z_oy,a.isp,aindexOrR0 abaseOrR0 }
inline void Assembler::z_og(  Register r1, const Address& a) { z_og(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }

inline void Assembler::z_or(  Register r1, Register r2)              { emit_16( OR_ZOPC   | regt(r1,  8, 16) | reg(r2, 12, java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler(retry
inline void Assembler::z_ork( Register r1, Register r2, Register r3) { emit_32( ORK_ZOPC  | regt(r1, 24, 32  Assembler:z_srstu(nd );
inline void Assembler::z_ogrk(Register r1, Register r2, Register r3) { emit_32( OGRK_ZOPC |   Assembler:z_brc(ssembler:bcondOverflow /* CC==3 (iterate) */, retry);

inline void Assembler::z_oihh(Register r1, int64_tjava.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
inline void Assembler::z_oihl(Register r1, int64_t i2) { emit_32( OIHL_ZOPC | regt
inline void Assembler::z_oilh(Register r1, int64_t i2) { emit_32( OILH_ZOPC | regt(r1, 8, 32) | imm16(i2, 16, 32)); }
inline  Assembler:_ill(egister r1 int64_t )  emit_32(OILL_ZOPC |regt(1,8,32) |imm16(2,,32) java.lang.StringIndexOutOfBoundsException: Index 117 out of bounds for length 117
inline void Assembler::z_oihf(Register r1, int64_t i2) { emit_48( OIHF_ZOPC | regt(r1, 8, 48) | imm32(i2, 16, 48)); }
inline  assert(rcBuff-encoding)     ! 0,"rc buffer addresscant beinZ_R0";

inline void Assembler::z_x(   Register r1, int64_t d2, Register x2, Register b2) { emit_32( X_ZOPC  | regt(r1, 8, 32) | rxmask_32( d2, x2, b2)); }
inline void Assembler::z_xy(  Register r1, int64_t d2, Register x2, Register b2) { emit_48( XY_ZOPC | regt(r1, 8, 48) | rxymask_48(d2, x2, b2)); }
inline
inline void Assembler::z_x(   Register r1, const Address& a) { z_x( r1, a.disp(), a.indexOrR0(),   Labelretry
inline void Assembler::z_xy(  Register r1, const Address  bind(etry)
inline void Assembler::z_xg(  Register r1, const Address& a) { z_xg(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }

inline void Assembler::z_xr(  Register r1, Register r2)              { emit_16( XR_ZOPC   | regt(r1,  8, 16) | reg(r2, 12, 16)); }
inline void Assembler::z_xgr( Register r1, Register r2)              { emit_32  ::(Assembler:bcondOverflow /* CC==3 (iterate) */, retry);
inline void Assembler::z_xrk( Register r1, Register r2, Register r3) { emit_32( XRK_ZOPC  | regt(r1, 24, 32) |}
inline void Assembler::z_xgrk(Register r1, Register r2, Register r3) { emit_32( XGRK_ZOPC | regt(r1, 24, 32) | reg(r2, 28, 32) | reg(r3, 16, 32)); }

inline void Assembler::z_xihf MacroAssemblerkimd srcBuff)java.lang.StringIndexOutOfBoundsException: Index 45 out of bounds for length 45
inline void Assembler::z_xilf(Register r1, int64_t i2) { emit_48( XILF_ZOPC)

inline void Assembler::z_nc(int64_tassert->encoding( %2 = 0, " bufferlen mustbe anevenodd register pair");
inline void Assembler::z_oc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2) { emit_48( OC_ZOPC | uimm8(l, 8,
inline void Assembler::z_xc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2) { emit_48( XC_ZOPC | uimm8(l, 8, 48) | rsmask_48(d1, b1) | rsmask_SS(d2, b2)); }
inline void Assembler::z_nc(Address dst, int64_t len, Address src2)   bind(etry)
inline void Assembler::z_oc(Address dst, int64_t len, Address src2) { assert(!dst.has_index(  ::z_kimd(_0,srcBuff;
inline void Assembler::z_xc(Address dst, int64_t len, Address src2) { assert(!dst.has_index() && !src2.has_index(), "Cannot  Assembler:z_brcAssembler::condOverflow /* CC==3 (iterate) */, retry);

//---------------
// ADD
//---------------
inline void Assembler::z_ajava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assemblervoid MacroAssemblerklmd(egister srcBuff){
inline void Assembler::z_al(  Register r1, int64_t d2, Register x2, Register b2) { emit_32( AL_ZOPC   | regt(r1, 8, 32) | rxmask_32( d2, x2, b2)); }
inline void Assembler::z_aly( Register r1, int64_t d2, Register x2, Register b2) { emit_48( ALY_ZOPC  | regt(r1, 8, 48) | rxymask_48(d2, x2, b2)); }
  assert(srcBuff-encoding( %2= , " buffer/lenmust bean even/odd registerpair");
inline void Assembler::z_agf( Register r1, int64_t d2, Register x2, Register b2) { emit_48( java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inlineLabel ;
inline void Assembler::z_algf(Register r1, int64_t d2, Register x2, Register b2) { emit_48( ALGF_ZOPC | regt(r1, 8, 48) | rxymask_48(d2, x2  bindretry
inline void Assembler::z_a(   Register r1, const Address& a) { z_a(   r1, a.disp  Assembler:z_klmd(_0,srcBuff)
inline void Assembler::z_ay(  Register r1, const Address& a) { z_ay(  r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_al(  Register r1, const Address& a) { z_al(  r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_aly( Register r1, const Address
inline void Assembler::z_ag(  Register r1, const Address& a) { z_ag(  r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_agf( Register r1, const Address& a) { z_agf( r1
inline void Assembler::z_alg( Register r1, const Address& a) { z_alg( r1, a.disp(  // DstBuff and srcBuff are allowed to be the same register (encryption in-place).
inline void Assembler::z_algf(Register r1, const Address& a) { z_algf(r1, a.disp(  // DstBuff and srcBuff storage must not overlap destructively, and neither must overlap the parameter block.

inline void Assembler::z_ar(  Register r1, Register r2) { emit_16( AR_ZOPC   | regt(r1,  8, 16) | reg(r2, 12, 16)); }
inline void Assembler::z_agr( Register r1, Register r2) { emit_32( AGR_ZOPC  | regt(r1, 24, 32) | reg(r2, 28, 32)); }
inline void Assembler::z_agfr(Register  (srcBuffencoding     ! 0,"rc buffer address can' be inZ_R0";
inline void Assembler::z_ark( Register r1, Register r2, Register r3) { emit_32( ARK_ZOPC  | regt(r1, 24, 32) | reg(r2,  assert(stBuff-encoding(   =0 "st buffer addrmust    register";
nline Assemblerz_agrk , Register r2 Register r3){emit_32(AGRK_ZOPC |regt(1,24,32)|(r2 ,32 |reg(3,16,)) }

inline void Assembler::z_ahi(  Register r1, int64_t i2) { emit_32( AHI_ZOPC  | regt(r1, 8, 32) | simm16(java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_afi(  Register r1,   (retryjava.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length 14
inline void Assembler::z_aghi( Register r1, int64_t  ::_m(stBuff,srcBuff)
inline void Assembler::z_agfi( Register r1, int64_t i2) { emit_48( AGFI_ZOPC | regt(r1, 8, 48) | simm32(i2, 16, 48)); }
inline void Assembler::z_aih(  Register r1, int64_t i2) { emit_48( AIH_ZOPC  | regt(r1, 8, 48) | simm32(i2, 16, 48)); }
inline void Assembler::z_ahik( Register r1, Register
inline void Assembler::z_aghik(Register r1, Register r3, int64_t i2) { emit_48( AGHIK_ZOPC | regt(r1, 8, 48) | reg(r3, 12, 48) | simm16(i2, 16, 48)); }

//-----------------------
// ADD LOGICAL
//-----------------------
inline void Assembler::z_alr(  Register r1, Register r2) { emit_16( tionin).
inline void Assembler::z_algr( Register r1, Register r2) { emit_32( ALGR_ZOPC  | regt(r1, 24, 32) | reg(r2, 28, 32)); }  / DstBuff and srcBuff storage must not overlap destructively, and neither must overlap the parameter block.
inline void Assembler::z_algfr(Register r1, Register r2) { emit_32( ALGFR_ZOPC | regt(r1,   (srcBuffencoding!=0,"rc bufferaddresscan' be in Z_R0);
inline void Assembler::z_alrk( Register r1, Register r2, Register r3) { emit_32( ALRK_ZOPC  | regt(r1, 24, 32) | reg(r2, 28, 32) | reg(r3, 16, 32)); }
inline void Assembler::z_algrk(Register r1, Register r2,   assert(stBuff-encoding( % = 0,"st bufferaddrmustbeanevenregister)
inline void Assembler::z_alcgr(Register r1, Register r2) { emit_32( ALCGR_ZOPC | regt(r1, 24, 32) | reg(r2, 28, 32)); }

inline void Assembler::z_alfi( Register r1, int64_t i2) { emit_48( ALFI_ZOPC |  regt(r1, 8, 48) | uimm32(i2, 16, 48)); }
inline void Assembler::z_algfi(Register r1, int64_t i2) { emit_48( ALGFI_ZOPC | regt(r1, 8, 48) | uimm32(i2, 16, 48)); }

inline void Assembler::z_alhsik( Register r1, Register r3, int64_t i2) { emit_48( ALHSIK_ZOPC  | regt(r1, 8, 48) | reg(r3, 12, 48) | simm16(i2, 16,  bindretry
inline void Assembler::z_alghsik(Register r1, RegisterAssemblerz_kmc, srcBuff);

inline void Assembler::z_alc( Register r1,   Assembler:z_brc(ssembler:bcondOverflow /* CC==3 (iterate) */, retry);
inline void Assembler::z_alcg(Register r1, int64_t d2, Register x2, Register b2) { emit_48( ALCG_ZOPC | regt(r1, 8, 48) | rxymask_48}
inline void Assembler::z_alc( Register r1, const Address& a) { z_alc( r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_alcg(Register r1, const Address& a) { z_alcg(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }

// In-memory arithmetic (add signed, add logical with signed immediate)
inline void Assembler::z_asi(  int64_t d1, Register b1,  // DstBuff and srcBuff are allowed to be the same register (encryption in-place).
inline void Assembler::z_agsi( int64_t d1, Register b1, int64_t  // DstBuff and srcBuff storage must not overlap destructively, and neither must overlap the parameter block.
inline void Assembler::z_alsi( int64_t d1, Register b1, int64_t i2) { emit_48( ALSI_ZOPC  | simm8(i2, 8, 48) | rsymask_48(d1, b1  assert(rcBuff-encoding(     ! 0,"  address can't be in Z_R0)
inline void Assembler::z_algsi(int64_t d1, Register b1, int64_t i2) { emit_48( ALGSI_ZOPC | simm8(i2
inline void Assembler::z_asi(  const Address& d, int64_t i2) { assert(  assertctrBuffencoding! 0,"tr buffer address can' be in Z_R0";
inline void Assembler::z_agsi( const Addressassert(trBuff-encoding( %2 = 0,ctr addrbeeven);
inline void Assembler::z_alsi( const Address& d, int64_t i2) { assert(!d.has_index(), "No
inline void Assembler::z_algsi(const Address& d, int64_t i2) { assert(!d.has_index(), "No index in ALGSI"); z_algsi(d.disp(), d.base(), i2); }

//--------------------
// SUBTRACT
//--------------------
inline void Assembler::z_s(   Register r1, int64_t d2, Register x2, Register b2) { emit_32( S_ZOPC    | regt retry
inline void Assembler::z_sy(  Register r1, int64_t d2, Register x2, Register b2)  (retry
inline void Assembler::z_sl(  Register r1, int64_t d2, Register x2, Register b2) { emit_32( SL_ZOPC   | regt(r1Assemblerz_kmctr(dstBuff,ctrBuff srcBuff)
inline void Assembler::z_sly( Register r1, int64_t d2, Register x2, Register b2) { emit_48( SLY_ZOPC  | regt(r1, 8, 48) | rxymask_48(d2, x2, b2)); }
inline void Assembler::z_sg(  Register r1, int64_t d2, Register x2, Register b2) { emit_48( SG_ZOPC   | regt(r1, 8, 48) | rxymask_48(d2, x2, b2)); }
inline void Assembler::z_sgf( Register r1, int64_t d2, Register x2, Register b2) { emit_48( SGF_ZOPC  | regt(r1, 8, 48) | rxymask_48(d2, x2, b2)); }
inline void Assembler::z_slg( Register r1, int64_t d2, Register x2, Register b2) { emit_48( SLG_ZOPC  | regt(r1void::(RegistercrcBuffRegister ) {
inline void Assembler::z_slgf(Register r1, int64_t d2, Register x2, Register b2) { emit_48( SLGF_ZOPC | regt(r1, 8, 48) | rxymask_48(d2, x2, b2)); }
inline void Assembler::z_s(   Register r1, const Address& a) { z_s(   r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline
inline void Assembler::z_sl(  Register r1, const Address& a) { z_sl(  r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_sly( Register r1, const Address& a) {  (retryjava.lang.StringIndexOutOfBoundsException: Index 14 out of bounds for length 14
inline void Assembler::_g  Register r1,const Address&a){z_sg( r1,a.isp(,a.ndexOrR0(,a.aseOrR0() java.lang.StringIndexOutOfBoundsException: Index 115 out of bounds for length 115
inline void Assembler::z_sgf( Register r1, const}
inline void Assembler::z_slg( Register r1, const Address& a) { z_slg( r1, a.disp(), a.indexOrR0(), a.baseOrR0())
inline void Assembler::z_slgf(Register r1, const Address& a) { z_slgf(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }

inline void Assembler::z_sr(  Register r1, Register r2) { emit_16( SR_ZOPC   | regt(r1,  8, 16) | reg(r2, 12, 16)); }
inline void Assembler::z_sgr( Register r1, Register r2) { emit_32( SGR_ZOPC  | regt(r1, 24, 32) | reg(r2, 28, 32)); }
inline void Assembler::z_sgfr(Register r1  assert(1->encoding(%2= 0,"st / lenmustbean / register pair";
inline void Assembler::z_srk( Register r1, Register r2, Register r3) { emit_32( SRK_ZOPC  assert(m3 &0b1110)= 0,"nused maskbitsmustbe ";
inline void Assembler::z_sgrk(Register r1, Register r2

inline void Assembler::z_sh(  Register r1, int64_t d2, Register x2, Register b2)   retry
inline void Assembler::z_shy( Register r1, int64_t d2, Register x2, Register b2) { emit_48( SHY_ZOPCbind);
inline void Assembler::z_sh(  Register r1, const Address &a) { z_sh( r1Assembler:z_troo(,r2);
inline void Assembler::z_shy( Register r1, const Address &a) { Assembler:z_brc(ssembler:bcondOverflow /* CC==3 (iterate) */, retry);

//----------------------------
// SUBTRACT LOGICAL
//----------------------------
inline void
inline void Assembler::z_slgr( Register r1, Register r2) { emit_32( SLGR_ZOPCvoidMacroAssembler:translate_ot(egister r1,Registerr2uint m3){
inline void Assembler::z_slgfr(Register r1, Register r2) { emit_32assert->()  2 = 0,"st addr/rc   be an even/  pair";
inline void Assembler::z_slrk( Register r1  assert(m3 &0b1110)=0 "nused maskbitsmust be ";
inline void Assembler::z_slgrk(Register r1, Register r2, Register r3) { emit_32(SLGRK_ZOPC | regt(r1, 24, 32) | reg(r2, 28, 32) | reg(r3, 16, 32)); }
inline void Assembler::z_slfi( Register r1, int64_t i2) { emit_48( SLFI_ZOPC  | regt(r1, 8, 48) | uimm32bind();
inline void Assembler::z_slgfi(Register r1, int64_t i2) { emit_48( SLGFI_ZOPCAssembler:z_trot(1 , m3)

//--------------------
// MULTIPLY
//--------------------
nline void Assembler:z_msr( Register r1,Register r2){emit_32(MSR_ZOPC   |regt(1,24,32)|reg(2,28 32);}
inline void Assembler::z_msgr( Register r1, Register r2) { emit_32( MSGR_ZOPC  | regt(r1
inline void Assembler::z_msgfr(Register r1, Register r2) { emit_32( MSGFR_ZOPC | regt(r1, 24, 32) | reg(r2voidMacroAssembler:translate_to(egisterr1Register,  m3 {
inline void Assembler::z_mlr(  Register r1, Register r2) { emit_32( MLR_ZOPC   | regt(r1, 24, 32) | reg(r2, 28, 32)); }
inline void Assembler::z_mlgr( Register r1, Register r2) { emit_32( MLGR_ZOPC  | regt(r1, 24, 32) | reg(r2, 28, 32)); }

inline void Assembler::z_mhy( Register r1, int64_t d2, Register x2, Register b2) { emit_48( MHY_ZOPC  | regt(r1, 8, 48) | rxymask_48(d2
inlinevoid Assembler:z_msy(Register r1,int64_t d2,Register ,  b2){emit_48(MSY_ZOPC  |regt,8 48)|rxymask_48(d2,x2));}
inline void Assembler::z_msg( Register r1, int64_t d2, Register x2, Register b2) { emit_48( MSG_ZOPC  | regt(r1, 8, 48) | rxymask_48(d2, x2, b2)); }
voidAssembler:z_msgf(egister r1,int64_t d2,Register x2,Register b2){ emit_48(MSGF_ZOPC|regt, 8,48)|rxymask_48(, x2 b2);}
inline void Assembler::z_ml(  Register r1, int64_t d2, Register x2, Register b2) { emit_48( ML_ZOPC   | regt(r1, 8, 48) | rxymask_48(d2, x2, b2)); }
inline void Assembler::z_mlg( Register r1, int64_t d2, Register

inline void Assembler::z_mhy( Register r1, constvoidMacroAssembler::ranslate_tt(egister r1,Register r2 m3{
inline void Assembler::z_msy( Register r1, const Address& a) { z_msy( r1, a.disp(), a  assert(1-encoding( %2 = 0 dstaddr    an/ register";
inline void Assembler::z_msgassertm3 &0b1110)= 0,"nused     zero";
inline void Assembler::z_msgf(Register r1, const Address& a) { z_msgf(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_ml(  Register r1, const Address& a  Labelretry
inline void Assembler::z_mlg( Register r1, const Address& a) { z_mlg( r1  (retry

inline void Assembler::z_msfi( RegisterAssembler:z_trtt(, r2,);
inline void Assembler::z_msgfi(Register r1, int64_t i2) { emit_48( MSGFI_ZOPC | regt(r1, 8, 48) | simm32(i2, 16, 48)); }
inline void Assembler::z_mhi(  Register r1, int64_t i2) { emit_32( MHI_ZOPC   | regt(r1, 8, 32) | simm16(i2, 16, 32)); }
inline

//------------------
// DIVIDE
//------------------
inline void Assembler//---------------------------------------
inline void Assembler::z_dsgfr(Register r1, Register r2) { emit_32( DSGFR_ZOPC | regt(r1, 24, 32) | reg// Helpers for Intrinsic Emitters

//-------------------
// COMPARE
//-------------------
inline void Assembler::z_cr(
inline void Assembler::z_clr( Register r1, Register r2) { emit_16( CLR_ZOPC  | reg(r1,  8, 16) | reg(r2, 12, 16/
inline void Assembler::z_cgr( Register r1, Register r2) { emit_32( CGR_ZOPC  | reg(r1, 24, 32
inline void Assembler::z_cgfr(Register r1, Register r2) { emit_32( CGFR_ZOPC | reg(r1, 24, 32) | reg *timesXtoThe32[rc&0xFF^(rc> 8;
inline void Assembler::z_clgr(Register r1, Register r2) { emit_32( CLGR_ZOPC | reg(r1, 24, 32) | reg(r2, 28, 32)); }
inline void Assembler::z_chi( Register r1, int64_t i2)  { voidMacroAssembler:fold_byte_crc32(egister crc,Register , Register table,Register ) {
inline void Assembler::z_cghi(Register r1, int64_t i2)  { emit_32( CGHI_ZOPC | reg(r1assert_different_registerscrc, tmp
inline void Assembler::z_cfi( Register  (val );
inline void Assembler::z_cgfi(Register r1, int64_t i2)  { emit_48( CGFI_ZOPC | regt(r1, 8, 48) | uimm32(i2if(rc ==val {     // Must rotate first to use the unmodified value.
inline void Assembler::z_ch(  Register r1, int64_t d2, Register x2    rotate_then_insert(mp , -2,63-,2,true)  // Insert byte 7 of val, shifted left by 2, into byte 6..7 of tmp, clear the rest.
inline void Assembler::z_c(   Register     z_srlcrc8)       // Unsigned shift, clear leftmost 8 bits.
inline void Assembler::z_cy(  Register r1, int64_t d2, Register x2, Register b2) { emit_48( CY_ZOPC | reg(r1, 8, 48) | rxymask_48(d2,    {
inline void Assembler::z_cg(  Register r1z_srl, 8)       // Unsigned shift, clear leftmost 8 bits.
inline void Assembler::z_ch(  Register r1, const Address &a) { z_ch(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_c(   Register r1, const Address &a) { z_c( r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_cy(  Register r1,  java.lang.StringIndexOutOfBoundsException: Index 3 out of bounds for length 3
inline void Assembler::z_cg(  Register r1, const Address &a) { z_cg(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }

inline void Assembler::z_clfi* uint32_t;
inline void Assembler::z_clgfi(Register r1, int64_t i2) { emit_48( CLGFI_ZOPC | regt(r1, 8, 48) | uimm32(i2, 16, 48)); }
inline void Assembler::z_cl(   Register r1, int64_t d2, Register x2, Register b2) { emit_32( CL_ZOPC  | regt(r1, 8, 32) | rxmask_32( d2, x2, b2)); }
inline void Assembler::z_cly(  Register r1, int64_t d2, Register x2, Register b2) { emit_48( CLY_ZOPC |  */
inline void Assembler::z_clg(  Register r1, int64_t d2, Registervoid MacroAssembler:fold_8bit_crc32(egister crc,Register table Register tmp){
inline void Assembler::z_cl(   Register r1, const Address &a) { z_cl( r1, a.disp(), a.indexOrR0(), a.baseOrR0fold_byte_crc32(rc , table tmp;
inline void Assembler::z_cly(  Register r1, const Address &a) { z_cly(r1, a
inline void Assembler::z_clg(  Register r1, const Address &a) { z_clg(r1, a.disp(),

inline void Assembler::z_clc(int64_t /
inline void Assembler::z_clcle(Register r1, Register r3, int64_t d2, Register b2) { emit_32( CLCLE_ZOPC | reg(r1, 8* Emitscode updateCRC32with byte accordingtoconstants .
inline void Assembler::z_clclu(Register r1, Register r3, int64_t d2, Register b2) { emit_48( CLCLU_ZOPC | reg(r1, 8, 48) | reg(r3, 12, 48) | rsymaskt_48(d2, b2)); }

  Assembler:(Registerr1 int64_t){ emit_32 TMLL_ZOPC |regtr1 8,32  imm16i2 16 32);}
inline void Assembler::z_tmlh(Register r1, int64_t i2) { emit_32( TMLH_ZOPC | regt(r1, 8, 32) | imm16(i2, 16, 32)); }
inline void Assembler::z_tmhl(Register r1, int64_t i2) { emit_32( TMHL_ZOPC | regt(r1, 8, 32) | imm16(i2, 16, 32)); }
inline void Assembler::z_tmhh(Register r1, int64_t i2) { emit_32( TMHH_ZOPC | regt(r1, 8, 32) | imm16(i2, 16, 32)); }

// translate characters
inline void Assembler::z_troo(Register r1, Register r2, int64_t m3) { emit_32( TROO_ZOPC | reg(r1, 24, 32) | reg(r2, 28, 32) *@aramin     Registercontaining  tofold the.
inline void Assembler::z_trot(Register r1, Register r2, int64_t m3) { emit_32( TROT_ZOPC | reg(r1, 24, 32) | reg(r2, 28, 32) | uimm4(m3, 16, 32)); }
inline void Assembler::z_trto(Register r1, Register r2, int64_t m3) { emit_32( TRTO_ZOPC | reg(r1, 24, 32) | reg(r2, 28, 32) | uimm4(m3, 16, 32)); }
inline void Assembler::z_trtt(Register r1,*

//------------------------
// COMPARE AND BRANCH/TRAP
//------------------------
// signed comparison
inline void Assembler::z_crb(Register  r1, *val= crc_tableval crc&0xFFjava.lang.StringIndexOutOfBoundsException: Index 39 out of bounds for length 39
inline void Assembler::z_cgrb(Register r1, Register r2, branch_condition m3*crcval( > 8)
inline void Assembler::z_crj(Register  r1, Register r2, branch_condition m3, address a4)              { emit_48( CRJ_ZOPC  | reg(r1, 8, 48) | */
void Assembler:z_cgrj( ,  r2,branch_condition m3,address a4)             {emit_48(CGRJ_ZOPC |reg(1,8, 48)|reg(2,12,48)    |simm16(elAddr::crel_off16(4, pc() ,48 |uimm4(3 32,48) }
inline void Assembler::z_cib(Register  r1, int64_t i2,  branch_condition m3, int64_t d4}
inline void Assembler::z_cgib(Register r1, int64_t i2,  branch_condition m3, int64_t d4, Register b4) { java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_cij(Register  r1, int64_t i2,  branch_condition m3, address a4)              { emit_48( CIJ_ZOPC  | reg(r1, 8, 48) | uimm4(m3, 12, 48)   | simm16(RelAddr::pcrel_off16(a4, pc()),
ine voidAssembler:(Register r1 int64_ti2branch_condition,address){ emit_48 CGIJ_ZOPC|reg, 8,48)| (m3 12,48   |simm16:pcrel_off16a4 () 16,48)|simm8, 32 48); }
// unsigned comparison
inline void Assembler::z_clrb(Register  r1, Register r2, branch_condition m3, int64_t d4, Register b4) { emit_48( CLRB_ZOPC  | reg(r1, 8, 48) | reg(r2, 12, 48)   | rsmask_48(d4, b4) | uimm4(m3, 32, 48)); }
inline void Assembler::z_clgrb(Register r1, Register r2, branch_condition m3, int64_t d4, Register b4) { emit_48( CLGRB_ZOPC | reg(r1, 8, 48) | reg(r2, 12, 48)   | rsmask_48(d4, b4) | uimm4(m3, 32, 48)); }
inline void Assembler::z_clrj(Register  r1, Register r2, branch_condition m3, address a4)              { emit_48( CLRJ_ZOPC  | reg(r1, 8, 48) | reg(r2, 12, 48)   | simm16
inline void Assembler::z_clgrj(Register r1, Register r2, branch_condition m3, address a4)              { emit_48( CLGRJ_ZOPC | reg(r1, 8, 48) | reg(r2, 12, 48)   | simm16(RelAddr::pcrel_off16(a4, pc()), 16, 48) | uimm4(m3, 32, 48)); }
inline void Assembler::z_clib(Register  r1, int64_t i2, branch_condition m3, int64_t d4, Register b4)  { emit_48( CLIB_ZOPC  | reg(r1, 8, 48) | uimm4(m3, 12, 48) | rsmask_48(d4, b4) | uimm8(i2, 32, 48)); }
inline void Assembler::z_clgib(Register r1, int64_t i2, branch_condition m3, int64_t d4, Register b4)  { emit_48( CLGIB_ZOPC | reg(r1, 8, 48) | uimm4(m3, 12, 48) | rsmask_48(d4, b4) | */
inline voidAssembler:z_clij(egister  r1,int64_t i2,branch_condition m3,  a4               {emit_48(CLIJ_ZOPC  |reg, 8,48)|uimm4(3,12,48)|simm16(elAddr:pcrel_off16(a4,pc() 16 48)|uimm8(2,32,)) }
inline void Assembler::z_clgij(Register r1, int64_t i2, branch_condition m3, address a4)               { emit_48  assert_different_registers(rc,buf,len, data

// Compare and trap instructions (signed).
inline void Assembler:  Label L_mainLoop,L_done;
inline void Assembler::z_cgrt(Register r1, Register r2, int64_t m3)  { emit_32( CGRT_ZOPC
inline void Assembler::z_cit(Register  r1, int64_t i2, int64_t m3)   { emit_48
inline void Assembler::z_cgit(Register r1, int64_t i2, int64_t m3)   { emit_48( CGIT_ZOPC  | reg  // Process all bytes in a single-byte loop.

// Compare and trap instructions (unsigned).
inline void Assembler::z_clrt(Register  r1, Register r2, int64_t m3) { emit_32( CLRT_ZOPC  | reg(r1, 24, 32) | reg(r2, 28, 32)    | uimm4(m3, 16, 32)); }
inline void Assembler::z_clgrt(Register r1, Registerz_brnh);
inline void Assembler::z_clfit(Register r1, int64_t i2,
inline void Assembler::z_clgit(Register r1, int64_t i2, int64_t m3)  { emit_48( CLGIT_ZOPC   (L_mainLoop

//------------------------
// BRANCH/CALL
//------------------------
inline void Assembler::z_bc(  branch_condition m1, int64_tadd2reg(uf,mainLoop_stepping)        // Advance buffer position.
inline void Assembler::z_bcr( branch_condition m1, Register r2) { emit_16inline(, data, );
inline void Assembler::    z_brct(en,L_mainLoop)                // Iterate.
inline void Assembler::z_brc( branch_condition i1, address a)   {java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_brcl(branch_condition i1, address a)   { emit_48( BRCL_ZOPC
inline void Assembler::z_bctgr(Register r1, Register r2)        { emit_32( BCTGR_ZOPC | reg( r1, 24, 32) | reg( r2/

inline void* Emitscode updateCRC32 with - valueaccordingtoconstantsintable
inline void Assembler::z_brasl(Register r1, address a)   { emit_48( BRASL_ZOPC | regt(r1, 8, 48) | simm32(RelAddr::pcrel_off32(a, pc()), 16, 48)); }

  :z_brct  r1  a)             {( BRCT_ZOPC|(r1 8,32)|simm16::pcrel_off16a,pc),16,32);}
inline void Assembler::z_brxh(Register  r1, Register r3, address a) {emit_32( BRXH_ZOPC  | reg(r1, 8, 32) | reg(r3, 12, 32) | simm16(RelAddr::pcrel_off16(a, pc()), 16, 32));}
inline void Assembler::z_brxle(Register r1, Register r3, address a) {emit_32( BRXLE_ZOPC | reg(r1, 8, 32) | reg(r3, 12, 32) | simm16(RelAddr::pcrel_off16(a, pc()), 16, 32));}
inline void Assembler::z_brxhg(Register r1, Register r3, address a) {emit_48( BRXHG_ZOPC | reg(r1, 8, 48) | reg(r3, 12, 48) | simm16(RelAddr::pcrel_off16(a, pc()), 16, 48));}
inline void Assembler::z_brxlg(Register r1, Register r3, address a) {emit_48( BRXLG_ZOPC | reg
inline void Assembler::z_brct(Register  r1,              Label& L) {z_brct( r1,     target(*/
inline void Assembler::z_brxh(Register  r1, Register r3, Label& L) {z_brxh( void MacroAssembler:update_1word_crc32(Register crc,Register buf,Register table,int bufDisp,int bufInc,
inline void Assembler::z_brxle(Register r1, Register r3, Label,  Register t2,   Register t3)java.lang.StringIndexOutOfBoundsException: Index 98 out of bounds for length 98
void::(Registerr1,Register , & L {_rxhg(1,r3,target(); }
inline void Assembler

inline void Assembler::z_flogr( Register r1,
inline void Assembler::z_popcnt(Register r1, Register r2)              { emit_32( POPCNT_ZOPC | reg(r1, 24, 32) | reg(r2, 28, 32)); }
inline void Assembler::z_ahhhr( Register r1, Register r2, Register r3) { emit_32( AHHHR_ZOPC  | reg(r3,  //         c = crc_table[4][c & 0xff] ^ crc_table[5][(c >> 8) & 0xff] ^ \
inline void Assembler::z_ahhlr( Registerjava.lang.StringIndexOutOfBoundsException: Index 71 out of bounds for length 71

inline void Assembler::z_tam ix2=*4CRC32_COLUMN_SIZE
inline void Assembler::z_stckf(int64_t d2, Register b2) { emit_32( STCKF_ZOPC | rsmask_32(d2, b2)); }
inline void Assembler::z_stm( Register r1, Register r3, int64_t d2, Register b2) { emit_32( STM_ZOPC  | reg(r1, 8, 32) | reg(r3,12,32)| rsmask_32( d2, b2)); }
inline void Assembler::z_stmy(Register r1, Register r3, int64_t d2, Register b2) { emit_48( STMY_ZOPC | reg(r1, 8, 48) | reg(r3,12,48)| // XOR crc with next four bytes of buffer.
inline void Assembler::z_stmg(Register r1, Register
inline void Assembler::z_lm(  Register r1, Register r3, int64_t d2, Register b2) { emit_32( LM_ZOPC   | reg(r1, 8, 32) | reg(r3,12,32)| rsmask_32( d2, b2)); }
inline void Assembler::z_lmy( Register r1, Register r3, int64_t d2, Register b2) { emit_48( LMY_ZOPC  | reg(r1, 8, 48) | reg(r3,12,48)| rsymask_48(d2, b2)); }
inline void Assembler::z_lmg( Register r1, Register r3, int64_t d2, Register b2) { emit_48( LMG_ZOPC  | reg(r1, 8, 48) | reg(r3,12,48)| rsymask_48add2regbuf bufInc

inline void Assembler::z_cs( Register r1, Register r3, int64_t d2, Register b2)  { emit_32( CS_ZOPC  | regt(r1, 8, 32) | reg(r3, 12, 32) | rsmask_32( d2, b2)); }
inline void Assembler::z_csy(Register r1, Register r3, int64_t d2, Register b2)  { emit_48( CSY_ZOPC | regt(r1, 8, 48) | reg(r3, 12, 48) | rsymask_48(d2, b2)); }
inline void Assembler::z_csg(Register r1, Register r3, int64_t d2, Register b2)  { emit_48( CSG_ZOPC | regt(r1, 8, 48) | reg(r3, 12, 48) | rsymask_48(d2, b2)); }
inline void Assembler(t1,t0 562 63-,-, true  // ((c >> 16) & 0xff) << 2
inline void Assembler::z_csy(Register r1, Register r3, const Address& a) { assert(, t0 56-2, 632, 2-4 );  java.lang.StringIndexOutOfBoundsException: Index 81 out of bounds for length 81
inline void Assembler::z_csg(Register r1, Register r3, const Address& a) {   // XOR indexed table values to calculate updated crc.

inline  z_ly(t2 Address(, t2intptr_t)ix1))java.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 46
inline void Assembler::z_cvdg(Register r1, int64_t d2, Registerz_ly(t0 Address, t0, (intptr_tix3)java.lang.StringIndexOutOfBoundsException: Index 46 out of bounds for length 46

//---------------------------
//--  Vector Instructions  --
//---------------------------

//---<  Vector Support Instructions  >---

// Load (transfer from memory)
  Assembler:(        ,b2{emit_48VLM_ZOPC(        (,12     rsmask_48(,b2); java.lang.StringIndexOutOfBoundsException: Index 187 out of bounds for length 187
inline void Assembler::z_vl(     VectorRegister v1, int64_t d2, Register x2, Register java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_vleb(   VectorRegister v1, int64_t d2, Register x2,  * @aramcrcregister  existingCRC32bit)
inline void Assembler::z_vleh(   VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t ix3){emit_48(VLEH_ZOPC  | vreg(v1,  8)                        | rxmask_48(d2, x2 param to byte byte
inline void Assembler: *lenregistercontaining
inline void Assembler::z_vleg(   VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t  *@    toCRC

// Gather/Scatter
inline void Assembler::z_vgef(   VectorRegister v1, int64_t d2, VectorRegister vx2, Register b2, int64_t ix3) {emit_48(VGEF_ZOPC  | vreg(v1,  8)                | rvmask_48(d2, vx2, b2) | uimm4(ix3, 32, 48)); }
inline voidAssembler:z_vgeg(  VectorRegister , int64_t , VectorRegistervx2 Register b2, int64_t ix3) {emit_48(VGEG_ZOPC  | vreg(v1,  8)                | rvmask_48d2 vx2 )| uimm4ix3 32 )); java.lang.StringIndexOutOfBoundsException: Index 209 out of bounds for length 209

inline void Assembler:Register t0  Registert1  Registert2,  Register,
inline void Assembler::z_vsceg(  VectorRegister v1, int64_t d2, VectorRegister                                         )java.lang.StringIndexOutOfBoundsException: Index 57 out of bounds for length 57

// load and replicate
inline void Assembler::z_vlrep(  VectorRegister v1, int64_t d2   L_mainLoop ;
inline void Assembler::z_vlrepb( VectorRegisterRegister  t0
inline void Assembler::z_vlreph(    ctr=;
inline void Assembler::z_vlrepf( VectorRegister v1,constint =java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 34
inline void Assembler::z_vlrepg( VectorRegister v1, int64_t d2, Register x2, Register b2)java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

inline void Assembler/
inline void Assembler::z_vllezb( VectorRegister v1, int64_t d2, Register x2, Register/
inline void Assembler:
inline void Assembler::z_vllezf( VectorRegister v1, int64_t d2, Register x2, Register b2)             {z_vllez(v1, d2, x2, b2, VRET_FW); }  // load logical FW   into left DW of VR, zero all other bit positions.
inline void Assembler::z_vllezg( VectorRegister v1, int64_t d2, Register x2, Register b2)             {z_vllez(v1, d2, x2, b2, VRET_DW); }  // load logical DW   into left DW of VR, zero all other bit positions.

inline void Assembler::z_vlbb(   VectorRegister v1, int64_t d2, Register x2, Register b2/
inline void Assembler::z_vll(    VectorRegister v1, Register r3, int64_t d2, Register b2)z_srag(, len )java.lang.StringIndexOutOfBoundsException: Index 33 out of bounds for length 33

// Load (register to register)
inline void Assembler::z_vlr (   VectorRegister v1, VectorRegister v2)                                {emit_48(VLR_ZOPC   | vreg(v1(crc ;

inline void Assembler::z_vlgv(   Register r1, VectorRegister v3, int64_t d2, Register b2, int64_t m4) {emit_48(VLGV_ZOPC  |  reg(r1,  8, 48) | vreg(v3, 12)     | rsmask_48(d2,     b2) | vesc_mask(m4, VRET_BYTE, VRET_DW,  rotate_then_insert(, len 64log_stepping,,
inline void Assembler::z_vlgvbjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_vlgvh(  Register r1, VectorRegister v3, int64_t d2, Register b2)             {z_vlgv(r1, v3, d2, b2    update_1word_crc32crc , table, , mainLoop_stepping ,t1,t2,t3;
inline void Assembler::z_vlgvf(  Register r1, VectorRegister v3, int64_t d2, Register b2)             {z_vlgv(r1, v3, d2, b2, VRET_FW); z_brct(, L_mainLoop; java.lang.StringIndexOutOfBoundsException: Index 40 out of bounds for length 40
inline void Assembler::z_vlgvg(  Register r1, VectorRegister v3, int64_t d2, Register b2)             {z_vlgv(r1, v3, d2, b2, VRET_DW); }   // load DW   from VR element (index d2(b2)) into GR.

inline void Assembler::z_vlvg(   VectorRegister v1, Register r3, int64_t d2
inline void Assembler::z_vlvgb(  VectorRegister v1, Register r3, int64_t d2, Register b2)             {z_vlvg(v1, r3, d2,  // Process last few (<8) bytes of buffer.
inline void Assembler::z_vlvgh(  VectorRegister  BINDL_tail;
inline void Assembler::z_vlvgf(  VectorRegister v1, Register r3, int64_t d2, Register b2)             {z_vlvg(v1, r3, d2, b2, VRET_FW); }
inline void Assembler::z_vlvgg(  VectorRegister v1, Register r3, int64_t d2, Register b2)             {z_vlvg(v1, r3, d2, b2, VRET_DW); }

inline void Assembler::z_vlvgp(  VectorRegister v1, Register r2  (crc, buf, len, table,data;

// vector register pack
}
inline void Assembler::z_vpkh(   VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vpk(v1, v2, v3, VRET_HW); }       // vector element type 'H'
inline void Assembler::z_vpkf(   VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vpk(v1, v2, v3,
inline void Assembler::z_vpkg(   VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vpk(v1, v2, v3, VRET_DW); }       // vector element type 'G'

inline  @param    containing  (2bit
inline void Assembler::z_vpksh(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vpks(v1, v2, v3, VRET_HW, VOPRC_CCIGN); }   // vector element type 'H', don't set CC
inline void Assembler::z_vpksf(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vpks(v1, v2, v3, VRET_FW, VOPRC_CCIGN); }   // vector element type 'F', don't set CC
inline void Assembler::z_vpksg(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vpks(v1, v2, v3, VRET_DW, VOPRC_CCIGN); }   // vector element type 'G', don't set CC
inline void Assembler::z_vpkshs( VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vpks(v1, v2, v3, VRET_HW, VOPRC_CCSET); }   // vector element type 'H', set CC
inline void Assembler::z_vpksfs( VectorRegister v1, VectorRegister  @paramregister  CRC
inline void Assembler::z_vpksgs( VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vpks(v1, v2, v3, VRET_DW, VOPRC_CCSET) */

ter,VectorRegisterv3int64_tm4int64_t) emit_48VPKLS_ZOPC vregv1  8) |vregv2   vregv3 16 |vesc_maskm4 VRET_HWVRET_DW )|voprc_ccmask(c5, 24); }
inline void Assembler::z_vpklsh( VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vpkls(v1, v2, v3, VRET_HW, VOPRC_CCIGN); }Register ,Register ,Register,Registert3
inline void Assembler::z_vpklsf( VectorRegister v1boolinvertCRC){
inline void Assembler::z_vpklsg( VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vpkls(v1, v2, assert_different_registerscrc ,lentable;
inline void Assembler::z_vpklshs(VectorRegister v1, VectorRegister v2, VectorRegister  =t0
inline void Assembler::z_vpklsfs(VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vpkls(v1, v2
inline void Assembler::z_vpklsgs(VectorRegister v1, VectorRegister v2,   if invertCRC)java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 18

// vector register unpack (sign-extended)
inline void Assembler::z_vuph(   VectorRegister v1, VectorRegister v2, int64_t m3)                    {emit_48(crc buflentable )java.lang.StringIndexOutOfBoundsException: Index 52 out of bounds for length 52
inline void Assembler::z_vuphb(  VectorRegister v1, VectorRegister v2)                                {z_vuph(v1, v2, VRET_BYTE); }          if () {
inline void Assembler::z_vuphh(  VectorRegister v1, VectorRegister v2)                                {z_vuph(v1, v2, VRET_HW); }          // vector element type 'H'
inline java.lang.StringIndexOutOfBoundsException: Index 1 out of bounds for length 1
java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_vuplb(  VectorRegister v1, VectorRegister v2)                                {z_vupl(v1, v2, VRET_BYTE); }        // vector element type 'B'
inline void Assembler::z_vuplh(  VectorRegister v1, VectorRegister v2)                                {z_vupl(v1, v2, VRET_HW); }          // vector element type 'H'
inline void Assembler::z_vuplf(  VectorRegister v1, VectorRegister v2){z_vuplv1 v2,VRET_FW) }// vector element type 'F'

// vector register unpack (zero-extended)
inline void Assembler::z_vuplh(  VectorRegister v1, VectorRegisterjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline  if () {
inline void Assembler::z_vuplhh( VectorRegister v1, VectorRegister v2)                                {z_vuplh(v1, v2, VRET_HW); }         // vector element type 'H'
inline void Assembler::z_vuplhf( VectorRegister v1, VectorRegister v2)                                {z_vuplh(v1, v2, VRET_FW); }         // vector element type 'F'
inline void Assembler::z_vupll
inline void Assembler::z_vupllb( VectorRegister v1, VectorRegister v2)                                {z_vupll( z_llgc(,Address,intptr_t);// Current byte of input buffer (zero extended). Avoids garbage in upper half of register.
inline void  update_byte_crc32(crc tmp,table
inline void Assembler::z_vupllf( VectorRegister v1, VectorRegister v2

// vector register merge high/low
inline void Assembler::z_vmrh(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMRH_ZOPC  | vreg(v1,  8)     | vreg(v2, 12)     | vreg(v3, 16)     | vesc_mask
inline void Assembler::z_vmrhb(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vmrh(v1, v2, v3, VRET_BYTE); }    // vector element type 'B'
inline Assembler:z_vmrhhVectorRegisterv1  v2 VectorRegister){(,,v3 VRET_HW}     / vector element type 'H'
inline void Assembler::z_vmrhf(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vmrh(v1, v2, v3, VRET_FW); }      // vector element type 'F'
inline void Assembler::z_vmrhg(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vmrh(v1, v2, v3, VRET_DW); }      // vector element type 'G'

inline void Assembler::z_vmrl(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMRL_ZOPC  | vreg(v1,  8)     | vreg(v2, 12)     | vreg(v3, 16  assert_different_registers(, val, table);
inline void Assembler::z_vmrlb(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vmrh(v1, v2, v3, VRET_BYTE); }    // vector element type 'B'
inline void Assembler::z_vmrlh(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vmrh(v1, v2, v3, VRET_HW); }      // vector element type 'H'
inline void Assembler::z_vmrlf(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vmrh(v1, v2, v3, VRET_FW); }      // vector element type 'F'
inline void Assembler::z_vmrlg(  VectorRegister v1,

// vector register permute
inline void Assembler::z_vperm(  VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4) {emit_48crc ,);/
inline void Assembler::z_vpdi(   VectorRegister v1,

// vector register replicate
inline
inline void Assembler::z_vrepb(  VectorRegister v1, VectorRegister v3, int64_t imm2)                  {z_vrep(v1, v3, imm2, VRET_BYTE); }  // vector element type 'B'
inline void Assembler::z_vreph(  VectorRegister v1, VectorRegister v3, int64_t imm2)                  {z_vrep(v1, v3, imm2, VRET_HW); }    // vector element type 'H'
inline void Assembler::z_vrepf(  VectorRegister v1, VectorRegister v3, int64_t imm2)                  {z_vrep(v1, v3, imm2, VRET_FW); }
inline//
inline void Assembler::z_vrepi(  VectorRegister v1, int64_t imm2,      int64_t m3)                    {emit_48(VREPI_ZOPC | vreg(v1,  //
inline void Assembler::java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
// dest_lo += src1 + src2
inline void Assembler::z_vrepif( VectorRegister v1, int64_t imm2)                                     {z_vrepi(v1, imm2, VRET_FW); }       // vector element type 'F'// dest_hi += carry1 + carry2
inline void Assembler::z_vrepig( VectorRegister v1, int64_t imm2)                                     {z_vrepi(v1, imm2voidMacroAssembler::(Registerdest_hi,Registerdest_lo

inline void Assembler::z_vsel(   VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4) {emit_48(VSEL_ZOPC  | vreg(v1,  8) |  vreg(v2, 12) |  vreg(v3, 16)  clear_reg(Z_R7;
inline void Assembler::z_vseg(   VectorRegister v1, VectorRegister v2, int64_t   z_algr(dest_lo src1

// Load (immediate)
inline  Assembler:z_vleib(  v1  imm2  ix3                        {( |vreg(,  8)|simm16 16 ) |uimm4, 32, );}
inline void Assembler::z_vleih(  VectorRegister v1, int64_t imm2, int64_t ix3)                        {emit_48(VLEIH_ZOPC | vreg(v1,  8)                        | simm16(imm2, 16, 48)z_algr(,src2
inline void Assembler::z_vleif(  VectorRegister v1, int64_t imm2, int64_t ix3)                        {emit_48(VLEIF_ZOPC | vreg(v1,  8)                        | simm16(imm2, 16, 48)  | uimm4(}
inline void Assembler::z_vleig(  VectorRegister v1, int64_t imm2, int64_t ix3)                        {emit_48(VLEIG_ZOPC | vreg

// Store
inline void Assembler::z_vstm(   VectorRegister v1, VectorRegister v3, int64_t d2, Register b2)       {emit_48(VSTM_ZOPC  | vreg(v1,  8)     | vregvoidMacroAssembler:multiply_64_x_64_loop xRegister xstart
inline void AssemblerRegister x_xstart,
inline void Assembler::z_vsteb(  VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t ix3){emit_48(VSTEB_ZOPC | vreg(v1,  8)                        | rxmask_48(d2, x2, b2) | uimm4(ix3, 32, 48)Register, Registery_idx
inline void Assembler::z_vsteh(  VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t ix3){emit_48(VSTEH_ZOPC | vreg(v1,  8)                        | rxmask_48
inline void Assembler::z_vstef(  VectorRegister v1, int64_t d2, Register x2, Register b2, int64_t ix3){emit_48(VSTEF_ZOPC | vreg
inline void Assembler::z_vsteg(  VectorRegister v1, int64_t d2, Register x2, Register b2  // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx--, kdx--) {
inlinevoid::(VectorRegister,Register r3int64_t ,Register ){(VSTL_ZOPC| vregv18)|reg,12,48) rsmask_48d2     );java.lang.StringIndexOutOfBoundsException: Index 187 out of bounds for length 187

// Misc
inline void Assembler::z_vgm(    VectorRegister v1, int64_t imm2, int64_t imm3, int64_t m4)           {emit_48(  // }
inline void Assembler::z_vgmb(   VectorRegister v1,  / z[start= carry;
inline void Assembler::z_vgmh(   VectorRegister v1, int64_t imm2, int64_t imm3)                       {z_vgm(v1, imm2, imm3, VRET_HW);
inline void Assembler::z_vgmf(   VectorRegisterLabel, ;
inline void Assembler::z_vgmg(   VectorRegister v1, int64_t imm2, int64_t imm3)                       {z_vgm(v1, imm2, imm3, VRET_DW);    L_one_x L_one_yL_multiply

inline void Assembler::z_vgbm(   VectorRegister v1, int64_tz_aghi, -)
inline void Assembler::z_vzero(  VectorRegister v1)                                                   z_brlL_one_x;/
inline void Assembler

//---<  Vector Arithmetic Instructions  >---

// Load
inline void Assembler::z_vlc(    VectorRegister v1, VectorRegister v2  (x_xstart (,Z_R1_scratch, 0);
inline void Assembler::z_vlcb(   VectorRegister v1, VectorRegister v2)                                {z_vlc(v1, v2, VRET_BYTE
er:(   VectorRegisterjava.lang.StringIndexOutOfBoundsException: Index 165 out of bounds for length 165
inline void Assembler::z_vlcf(   VectorRegister v1, VectorRegister v2)                                {z_vlc(v1, v2, VRET_FW); }           // vector element type 'F'idx1)java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 18
inline void Assembler::z_vlcg(   VectorRegister v1, VectorRegister v2)                                {z_vlc(v1  z_aghiidx-);
inline void   (L_one_y
inline void Assembler::z_vlpb(   VectorRegister v1, VectorRegister v2)                                {z_vlp(v1, v2, VRET_BYTE)java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_vlph(   VectorRegister v1, VectorRegister v2)                                {z_vlp(v1, v2, VRET_HW); }           // vector element type 'H'
inlinemem2reg_opty_idx Address(,Z_R1_scratch)java.lang.StringIndexOutOfBoundsException: Index 50 out of bounds for length 50
inline void Assembler::z_vlpg(   VectorRegister v1, VectorRegister v2)

// ADD
inline void Assembler::z_va(     VectorRegisterbindL_multiply)java.lang.StringIndexOutOfBoundsException: Index 19 out of bounds for length 19
inline void Assembler::z_vab(    VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_va(v1 product_low=multiplicand
inline void Assembler::z_vah(    VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_va(v1(multiplicandx_xstart
  Assembler(VectorRegister,VectorRegisterv2 VectorRegisterv3)             {z_vav1,, ,VRET_FW;}
inline void Assembler::z_vag(    VectorRegister v1, VectorRegister v2, VectorRegister v3)             clear_regZ_R7java.lang.StringIndexOutOfBoundsException: Index 18 out of bounds for length 18
inline void Assembler::z_vaq(    VectorRegister v1, VectorRegisterz_alcgr,Z_R7;
inline void   add2regkdx 2;
inline void Assembler::z_vaccb(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inlinevoid::z_vacch  VectorRegister, VectorRegister v2 VectorRegisterv3){z_vacc(v1 ,v3 VRET_HW;
inline void Assembler::z_vaccf(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vacc(v1, v2z_sllg(Z_R7, kdx LogBytesPerInt)
inline void Assembler::z_vaccg(  VectorRegister  reg2mem_opt(product_low Address(z, Z_R7,0);
inline void Assembler::z_vaccq(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vacc(v1, v2, v3, VRET_QW); }      // vector element type 'Q'

// SUB
inline void Assembler::z_vs(     VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VS_ZOPC    | vreg(v1,  8) | vreg(v2, 12) | vreg(v3, 16)lgr_if_neededcarry
inline void   z_bru(L_first_loop);
inline void Assembler::z_vsh(    VectorRegister v1, VectorRegister v2, VectorRegister v3
inline void Assembler::z_vsf(    VectorRegister v1,java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline voidAssembler(,v2,, VRET_DW}
inline void Assembler::z_vsq(    VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vs(v1,
inline void Assembler::z_vscbi(  VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t (,yintptr_t )
inline void   ();
inlinejava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inlinejava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_vscbig( VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vscbi(v1, v2, v3, VRET_DW);  (L_one_x;/java.lang.StringIndexOutOfBoundsException: Index 62 out of bounds for length 62
inline void Assembler::z_vscbiq( VectorRegister java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

// MULTIPLY
inline void Assembler::z_vml(    VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_tmem2reg_opt, Addressx, intptr_t),false;
Assembler(     , VectorRegister,VectorRegister,int64_t ) {mit_48(  8) (v2 12)|(, ) |vesc_mask(,VRET_BYTE,VRET_FW,32))
inline void Assembler::z_vmlh(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMLH_ZOPC  | vreg(v1,  8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_FW, 32)); }
inline voidAssembler:z_vme    VectorRegister v1  v2,VectorRegister v3,int64_t m4 {(VME_ZOPC   |vreg(1  8 |vregv2,12)  vregv3,)  vesc_mask(m4 VRET_BYTE VRET_FW,32)) }
inline void Assembler::z_vmle(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMLE_ZOPC  | vreg(v1,  8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_FW
inline void Assembler::z_vmo and add 128 bit.
inline void Assembler::z_vmlo(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMLO_ZOPC  | vreg(v1,  8) | vreg(v2, 12) | vreg(v3, 16) |

// MULTIPLY & ADD
inline void Assembler::z_vmal(   VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5) {emit_48(VMAL_ZOPC  | vreg(v1,  8) | vreg(v2, 12) | vreg(v3, 16) | vreg(v4, 32) | vesc_mask(m5, VRET_BYTE, VRET_FW, 20)); }
ter v1, VectorRegister v2, VectorRegisterv3 VectorRegister v4, int64_t m5 {emit_48(VMAH_ZOPC| vregv1  8)| vreg(v2,12)| vreg(3 16|vregv4 )|vesc_mask(m5,VRET_BYTE, VRET_FW, ); }
inline void Assembler::z_vmalh(  VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5) {emit_48(VMALH_ZOPC | vreg(v1,  8) | vreg(v2, 12) | vreg(v3, 16) | vreg(v4, 32) | vesc_mask(m5, VRET_BYTE, VRET_FW, 20)); }
inline void Assembler::z_vmae(   VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5) {emit_48(VMAE_ZOPC  | vreg(v1,  8) | vreg(v2, 12) | vreg(v3, 16) | vreg(v4, 32) | vesc_maskRegister carry Register product,
inline void Assembler::z_vmale(  VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5)                                              offset) {
inline void Assembler::z_vmao(   VectorRegister
inline void Assembler::z_vmalo(  VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t m5) {emit_48(VMALO_ZOPC | vreg(v1,  8) | vreg(v2, 12) | vreg(v3, 16) | vreg(v4, 32) | vesc_mask(m5, VRET_BYTE, VRET_FW, 20)); }

// VECTOR SUM
inline void Assembler::z_vsum(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VSUM_ZOPC  | vreg(v1,  8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_HW, 32)); }
inline void Assembler::z_vsumb(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vsum(v1, v2, v3, VRET_BYTE); }    // vector element type 'B'
inline void Assembler::z_vsumh(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vsum(v1, v2, v3, VRET_HW); }      // vector element type 'H'
inline void Assembler::z_vsumg(  VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VSUMG_ZOPC | vreg(v1,  8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_HWz_sllg(Z_R7,idx );
inline void Assembler::  mem2reg_opt(yz_idx, Address(y Z_R7 offset);
inline void Assembler::z_vsumgf( VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vsumg(v1, v2, v3, VRET_FW); }     // vector element type 'H'
inline void Assembler:z_vsumq(VectorRegister v1,VectorRegister v2,VectorRegisterv3 int64_tm4 {mit_48VSUMQ_ZOPC | vreg(v1  8) | vregv2 12)|vreg(3 16 | vesc_mask(m4 VRET_FW   VRET_DW, 3232); }
inline void Assembler::z_vsumqf( VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vsumq(v1, v2, v3, VRET_FW); }     // vector element type 'B'
inline void Assembler::z_vsumqg( VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vsumq(v1, v2, v3, VRET_DW); }     // vector element type 'H'

// Average
inline void Assembler::z_vavg(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VAVG_ZOPC  | vreg(v1,  8) | vreg(v2, 12) | inlinewith_carry, product_low carry,yz_idx)java.lang.StringIndexOutOfBoundsException: Index 55 out of bounds for length 55
inline void Assembler::z_vavgb(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vavg(v1, v2, v3, VRET_BYTE); }    // vector element type 'B'
inlinevoid Assembler::z_vavgh   v1 VectorRegister v2,  v3){z_vavg(v1 v2, v3, VRET_HW);}      // vector element type 'H'
inline void Assembler::z_vavgf(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vavg(v1, v2, v3, VRET_FW); }      // vector element type 'F'
inline  Assembler:z_vavgg(  VectorRegister v1, VectorRegister ,VectorRegister v3             (, v2 v3 VRET_DW) }      // vector element type 'G'
inline void Assembler::z_vavgl(  VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VAVGL_ZOPC | vreg(v1,  8) | vreg(v2,
inline void Assembler::z_vavglb( VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vavgl(v1, v2, v3}
inline void Assembler::z_vavglh( VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vavgl(v1, v2, v3, VRET_HW); }     // vector element type 'H'
inline void Assembler::z_vavglfjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_vavglg( VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vavgl(v1, v2, v3, VRET_DW); }     // vector element type 'G'

// VECTOR Galois Field Multiply Sum
inline void Assembler::z_vgfm(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VGFM_ZOPC  | vreg(v1,  8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
inline void Assembler::z_vgfmb(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vgfm(v1, v2, v3, VRET_BYTE); }    // vector element type 'B'
inlinevoid Assembler:z_vgfmh  VectorRegisterv1 VectorRegister v2 VectorRegisterv3)             z_vgfmv1,v2,v3 VRET_HW }// vector element type 'H'
inline void Assembler::z_vgfmf(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vgfm(v1, v2, v3, VRET_FW); }      // vector element type 'F'
inline void Assembler::z_vgfmg(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vgfm(v1, v2, v3, VRET_DW); }      // vector element type 'G'
inline void Assembler::z_vgfma(  VectorRegister v1, VectorRegister                                              carry Register product,
inline void Assembler::z_vgfmab( VectorRegisterRegister carry2) {
inline void Assembler::z_vgfmah( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4) {z_vgfma(v1, v2, v3, v4, VRET_HW); }   // vector element type 'H'
inline void Assembler::z_vgfmaf( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4) {z_vgfma(v1, v2, v3, v4, VRET_FW); }   // vector element type 'F'
inline void Assembler::z_vgfmag( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4) {z_vgfma(v1, v2, v3, v4, VRET_DW); }   // vector element type 'G'

//---<  Vector Logical Instructions  >---

// AND
inline void Assembler:java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
inline void Assembler::z_vnc(    VectorRegister v1, VectorRegister v2, VectorRegister v3)             {emit_48(VNC_ZOPC   | vreg(v1,  8) | vreg(v2, 12) | vreg(v3, 16)); }

// XOR
inline  //   carry = (jlong)(product >>> 64);

// NOR
inline void Assembler::z_vno(    VectorRegister  // }

// OR
inline void Assembler::z_vo(     VectorRegister v1, VectorRegister v2  / idx += 2;

// Comparison (element-wise)
/
inline void Assembler::z_vceqb(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vceq(v1, v2, v3, VRET_BYTE, VOPRC_CCIGN); } // vector element type 'B', don't set CC
inline void Assembler::z_vceqh(  //   product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
inline void Assembler::z_vceqf(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vceq(v1, v2, v3, VRET_FW,   VOPRC_CCIGN); } // vector element type 'F', don't set CC
inline void Assembler::z_vceqg(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vceq(v1, //   z[kdx+idx] = (jlong)product;
inline void Assembler::z_vceqbs( VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vceq(v1, v2, v3, VRET_BYTE, VOPRC_CCSET)  //   carry = (jlong)(product >>> 64);
inline void Assembler::z_vceqhs( VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vceq(v1, v2, v3, VRET_HW,java.lang.StringIndexOutOfBoundsException: Index 6 out of bounds for length 6
inline void Assembler::z_vceqfs( VectorRegister v1,java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_vceqgs( VectorRegister v1, VectorRegister v2, VectorRegister v3)             {Label,,;
inline void Assembler::z_vchjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

inline void Assembler::z_vchh(   VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vch(v1, v2, v3, VRET_HW,    VOPRC_CCIGN); }    lgr_if_needed(jdx idx;
inline void Assembler::  and_imm(jdx, 0xfffffffffffffffcL;
inline void Assembler::z_vchg(   VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vch(v1, v2, v3, VRET_DW,    VOPRC_CCIGN); }  // vector element type 'G', don't set CC
inline
inline void Assembler::z_vchhs(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vch(v1, v2, v3, VRET_HW,    VOPRC_CCSET); }  // vector element type 'H', don't set CC
inline void Assembler::z_vchfs(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vch(v1, v2, v3, VRET_FW,    VOPRC_CCSET); }  // vector element type 'F', don't set CC
inline void Assemblerjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_vchl(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4, int64_t cc5) {emit_48(VCHL_ZOPC  | vreg(v1,  8) | vreg(v2  z_aghi(jdx -)
inline void  z_brl(L_third_loop_exit)java.lang.StringIndexOutOfBoundsException: Index 27 out of bounds for length 27
inline void Assembler::z_vchlh(  VectorRegister  add2reg(idx, -4);
inline void Assembler::z_vchlf(  VectorRegister v1, VectorRegister v2, VectorRegister
inline void Assembler::z_vchlg(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vchl(v1, v2, v3, VRET_DW,   VOPRC_CCIGN); }  // vector element type 'G', don't set CC
inline void Assembler::z_vchlbs( VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vchl(v1, v2, v3, VRET_BYTE, VOPRC_CCSET); }  // vector element type 'B', don't set CC
inline void Assembler::z_vchlhs( VectorRegister v1,  multiply_add_128_x_128(x_xstart y,,yz_idx, idxcarry, , );
inline void Assembler::z_vchlfs( VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vchl(v1, v2, v3, VRET_FW,   VOPRC_CCSET); }  // vector element type 'F', don't set CC
inline void Assembler::z_vchlgs( VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vchl(v1, v2, v3, VRET_DW,   VOPRC_CCSET); }  // vector element type 'G', don't set CC

// Max/Min (element-wise)
inline void Assembler::z_vmx(    VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMX_ZOPC   | vreg(v1,  8) | vreg(v2, 12) |   lgr_if_neededcarry product;
inline void Assembler::  z_bru(_);
inline void Assembler::z_vmxh(   VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vmx(v1, v2, v3, VRET_HW); }       // vector element type 'H'
inline void Assembler::z_vmxf(   VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vmx(v1, v2, v3, VRET_FW); }       // vector element type 'F'
inline void Assembler::z_vmxg(   VectorRegister v1, VectorRegister v2, VectorRegisterbindL_third_loop_exit)  // Handle any left-over operand parts.
inline void Assembler::z_vmxl(   VectorRegister v1, VectorRegisterjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_vmxlb(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vmxl(v1, v2, v3, VRET_BYTE); }    // vector element type 'B'
inline void Assembler::java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inlinevoidAssembler:z_vmxlf  VectorRegister v1 VectorRegisterv2 VectorRegister v3)             {z_vmxl(v1, v2,v3 VRET_FW); }     // vector element type 'F'
inline void Assembler::z_vmxlg(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vmxl(v1, v2, v3, VRET_DW); }      // vector element type 'G'
inline void Assembler::z_vmn(    VectorRegister v1  z_aghi(idx, -);
inline   (L_check_1;
inline void Assembler::z_vmnh(   VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vmn(v1, v2, v3, VRET_HW); }
inline void Assembler::z_vmnf(   VectorRegister v1, VectorRegisterct 0)
inline void Assembler::z_vmng(   VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vmn(v1, v2, v3, VRET_DW); }       // vector element type 'G'
inline void Assembler::z_vmnl(   VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t m4) {emit_48(VMNL_ZOPC  | vreg(v1,  8) | vreg(v2, 12) | vreg(v3, 16) | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
inline void Assembler::z_vmnlb(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vmnl(v1, v2, v3, VRET_BYTE); }      lgr_if_needed(carry product;
inline void Assembler::z_vmnlh(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vmnl
inline void Assembler::z_vmnlf
inline void Assembler::z_vmnlg(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vmnl(v1, v2, v3, VRET_DW

// Leading/Trailing Zeros, population count
inline void Assembler::z_vclz(   VectorRegister v1,  add2reg(idx 0);
inline void Assembler::z_vclzb(  VectorRegister v1, VectorRegister v2)                                {z_vclz(v1, v2, VRET_BYTE)  and_immidx );
inline void Assembler::z_vclzh(  VectorRegister v1, VectorRegister v2)                                {z_vclz(v1, v2, VRET_HW  z_aghiidx-1;
inline void Assembler::z_vclzf(  VectorRegister v1, VectorRegister v2)                                {z_vclz(v1, v2, VRET_FW); }          // vector element type 'F'
inline void Assembler::z_vclzg(  VectorRegister v1, VectorRegister v2)                                {z_vclz(v1, java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_vctz(   VectorRegister v1, VectorRegister v2, int64_t m3)                    {emit_48(VCTZ_ZOPC  | vreg(v1,  8) | vreg(v2, 12) | vesc_mask(m3, VRET_BYTE, VRET_DW, 32)); }
inline void Assembler::java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
  (, idx, LogBytesPerInt);
inline void Assembler::z_vctzf(  VectorRegister v1, VectorRegister v2)                                {z_vctz(v1, v2,java.lang.StringIndexOutOfBoundsException: Index 20 out of bounds for length 20
inline Assembler:(VectorRegister v1 VectorRegister)                                (v1,v2 VRET_DW)           // vector element type 'G'
inline void Assembler::z_vpopct( VectorRegister v1, VectorRegister  lgr_if_needed(, );

// Rotate/Shift
()
inline void Assembler::z_verllvb(VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_verllv(v1, v2, v3, VRET_BYTE); }  // vector element type 'B'
inline void Assembler::z_verllvh  add2_with_carry(product, product_low, yz_idx, carry);
inline void Assembler::z_verllvf(VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_verllv(v1, v2, v3, VRET_FW); }    // vector element type 'F'
inline void Assembler::z_verllvg(VectorRegister v1, VectorRegister v2, VectorRegister v3)               z_sllg(Z_R7 idx,);
  Assembler( v1  ,int64_tb2int64_t (VERLL_ZOPC (v1  8  (v3 )|rsmask_48(d2b2  vesc_mask(,VRET_BYTE, VRET_DW,); }
inline void Assembler::z_verllb( VectorRegister v1, VectorRegister v3, int64_t d2,rshiftproduct_low, 32);
inline java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_verllf( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2)       {z_verllproduct_low,product;
inline void Assembler::z_verllg( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2)       {z_verll(v1, v3, d2, b2, VRET_DW);}  // vector element type 'G'
inline void Assembler::z_verim(  VectorRegister v1
inline void Assembler::z_verimb( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4) {z_verim(v1, v2, v3, imm4, VRET_BYTE); }   // vector element type 'B'
inlinevoidAssembler:(VectorRegister ,VectorRegisterv2  v3,int64_t ){(,v2 v3VRET_HW      // vector element type 'H'
inline void Assembler::z_verimf( VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4) {z_verim(v1, v2, v3, imm4, VRET_FW); }     // vector element type 'F'                                     Register
Assemblerz_verimg VectorRegisterv1 VectorRegister , v3  imm4 {(v1 , ,imm4 VRET_DW;      // vector element type 'G'

inline void Assembler::z_veslv(  VectorRegister v1, VectorRegister v2, VectorRegister v3,               int64_t m4) {emit_48(VESLV_ZOPC | vreg(v1,  8) | vreg(v2, 12) | vreg(v3, 16)      | vesc_mask(m4, VRET_BYTE, VRET_DW, 32)); }
inline void Assembler::z_veslvb( VectorRegister v1, VectorRegister v2,assert_different_registers(x,,ylen,
void:z_veslvh v1 VectorRegister, v3             (v1 ,v3 VRET_HW);}// vector element type 'H'
inline void Assembler::z_veslvf(x ,  , ,
inline void Assemblertmp1 tmp2,tmp3 tmp4 tmp5 Z_R8;
inline void Assemblerjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_veslb(  VectorRegister v1, VectorRegister v3, int64_t d2, Register b2)       {z_vesl(v1, v3, d2, b2, VRET_BYTE);} // vector element type 'B'
inline/java.lang.StringIndexOutOfBoundsException: Index 63 out of bounds for length 63
inline void Assembler::z_veslf(  VectorRegister v1, VectorRegister v3, int64_tAddress zlenZ_SP,_z_abi(remaining_cargs))  // Int in long on big endian.
inline void Assembler::z_veslg(  VectorRegister v1, VectorRegister v3, int64_t d2, Register b2)       {z_vesljava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0

inline void Assembler::z_vesrav( VectorRegister v1, VectorRegister v2, VectorRegister v3,               int64_t m4) {emit_48(VESRAV_ZOPC| vreg(v1,  8) | vreg(v2, 12) | vreg  constRegisterkdx  tmp2
inline void Assembler::z_vesravb(VectorRegister v1, VectorRegisterconst Registerxstart =tmp3
inline void Assembler::z_vesravh(VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vesrav(v1, v2, v3, VRET_HW); }    // vector element type 'H'
inline void Assembler::z_vesravf(VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vesrav(v1, v2, v3, VRET_FW); }    // vector element type 'F'
inline void Assembler::z_vesravg(VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vesrav(v1, v2, v3, VRET_DW); }    // vector element type 'G'
inline void Assembler:z_vesra  VectorRegisterv1,VectorRegister v3 int64_t d2, Register b2          m4 {(VESRA_ZOPC |vreg,  )|vreg(3, )  rsmask_48d2 b2 |vesc_maskm4,VRET_BYTEVRET_DW,32))}
inline void Assembler::  constRegister product  =Z_R0_scratch;
inline void Assembler::z_vesrah( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2)       {z_vesra(v1, v3, d2, b2, VRET_HW);}  // vector element type 'H'
inline void Assembler::z_vesraf( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2)       {z_vesra(v1, v3,   const  x_xstart = Z_R8
inline void Assembler::z_vesrag( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2)       {z_vesra(v1, v3, d2, b2, VRET_DW);}  // vector element type 'G'
inline void Assembler::z_vesrlv( VectorRegister v1, VectorRegister v2, VectorRegister v3,               int64_t m4) {emit_48(VESRLV_ZOPC| vreg(v1,  8) | vreg(v2, 12) | vreg(v3, 16)      | vesc_mask(m4, VRET_BYTE, VRET_DW,   // First Loop.
inline void Assembler::z_vesrlvb(VectorRegister  //
inline void Assembler::z_vesrlvh(VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vesrlv(v1, v2, v3, VRET_HW); }    // vector element type 'H'  //   final static long LONG_MASK = 0xffffffffL;
inline void Assembler::z_vesrlvf  //   int xstart = xlen - 1;
inline void Assembler::z_vesrlvg(VectorRegister v1, VectorRegister v2, VectorRegister v3)             {z_vesrlv(v1, v2, v3, VRET_DW);
inline void Assembler::z_vesrl(  VectorRegister v1, VectorRegister/
inline void Assembler::z_vesrlb( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2)/
inline void Assembler::z_vesrlh( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2)       {z_vesrl
inline void Assembler::z_vesrlf( VectorRegister v1, VectorRegister v3, int64_t d2, Register b2)       {z_vesrl//     z[kdx] = (int)product;
inline void Assembler::z_vesrlg( VectorRegister v1, VectorRegister v3, int64_t  //     carry = product >>> 32;

inline void Assemblerjava.lang.StringIndexOutOfBoundsException: Index 30 out of bounds for length 30
inline void Assembler::z_vslb(   VectorRegister v1, VectorRegister v2, VectorRegister v3)               {java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_vsldb(  VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4) {emit_48(VSLDB_ZOPC | vreg(v1,  8) | vreg(v2, 12) | vreg(v3, 16) | uimm8(imm4, 24, 48)); }

inline void Assembler::z_vsra(   VectorRegister v1, VectorRegister v2, VectorRegister v3)             {emit_48(VSRA_ZOPC  | vreg(v1,  8) | vreg(v2, 12) | vreg(v3, 16)); }
inline void Assembler::z_vsrab(  VectorRegister v1, VectorRegister v2, VectorRegister v3java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_vsrl(   VectorRegister v1, VectorRegister v2, VectorRegister v3)             {emit_48(VSRL_ZOPC  | vreg(v1,  8) | vreg(v2, 12) | vreg(v3, 16)); }
inline void Assembler::z_vsrlb(  VectorRegister v1, VectorRegister v2, VectorRegister v3)             {emit_48(VSRLB_ZOPC | vreg(v1,  8) | vreg(v2, 12) | vreg  z_brlL_done);

// Test under Mask
inline void Assembler::z_vtm(    VectorRegister v1

//---<  Vector String Instructions  >---
inlinecompare64_and_branch,RegisterOrConstantintptr_t) bcondEqual L_second_loopjava.lang.StringIndexOutOfBoundsException: Index 89 out of bounds for length 89
inline void Assembler::inline
inline void Assembler::z_vfaeh(  VectorRegister v1, VectorRegister v2, VectorRegister v3,               int64_t
inline   z_aghikdx-1;
inline void Assembler::z_vfee(   VectorRegister v1, VectorRegister v2, (L_carry;
inline void Assembler::z_vfeeb(  VectorRegister v1, VectorRegister v2, VectorRegister v3,               int64_t cc5) {z_vfee(v1, v2, v3, VRET_BYTE, cc5); }
inline void Assembler::z_vfeeh(  VectorRegister v1, VectorRegister v2, VectorRegister v3,               int64_t cc5) {z_vfee(v1, v2, v3, VRET_HW,   cc5); }
inline void Assembler::z_vfeef(  VectorRegister v1, VectorRegister v2, VectorRegister v3,               int64_t cc5) {z_vfee(v1, v2, v3, VRET_FW,   cc5); }
inline void Assembler::z_vfene(  VectorRegister v1, VectorRegister v2, VectorRegister v3, int64_t imm4, int64_t cc5) {emit_48(VFENE_ZOPC | vreg(v1,  8) | vreg(v2, 12) | vregz_sllgZ_R1_scratch, kdx LogBytesPerInt;
inline void Assembler::z_vfeneb( VectorRegister v1, VectorRegister v2, VectorRegister v3,               int64_t cc5) {z_vfene(v1  reg2mem_optcarry Addressz Z_R1_scratch, ) false);
inline void Assembler::z_vfeneh( VectorRegister v1, VectorRegister v2, VectorRegister v3,               int64_t cc5) {z_vfene(v1, v2, v3, VRET_HW,   cc5  rshiftcarry32;
inline void Assembler::z_vfenef( VectorRegister v1, VectorRegister v2, VectorRegister v3,               int64_t(kdx-1)
inline void Assembler::z_vstrc(  VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4, int64_t imm5, int64_t cc6) {emit_48(VSTRC_ZOPC | vreg(v1,  8) | vreg(v2, 12) | vreg(v3
inline void Assembler::z_vstrcb( VectorRegister v1, VectorRegister v2, VectorRegister v3,   bind(L_carry;
inline void Assembler::z_vstrch( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_vstrcf( VectorRegister v1, VectorRegister v2, VectorRegister v3, VectorRegister v4,               int64_t cc6)
reg2mem_opt(carry, Addressz ,) );
inline void Assembler::z_vistrb( VectorRegister v1, VectorRegister v2,               int64_t cc5) {z_vistr
inline void Assembler::z_vistrh( VectorRegister v1,  java.lang.StringIndexOutOfBoundsException: Index 37 out of bounds for length 37
inline void Assembler::z_vistrf( VectorRegister v1, VectorRegister v2,               int64_t cc5) {z_vistr(v1, v2, VRET_FW,   cc5); }
inline void Assembler::z_vistrbs(VectorRegister v1, VectorRegister v2)                            {z_vistr(v1, v2, VRET_BYTE, VOPRC_CCSET); }
inline void Assembler::z_vistrhs(VectorRegister v1, VectorRegister v2)                            {z_vistr(v1, v2, VRET_HW,   VOPRC_CCSET); }
inline void Assembler::z_vistrfs(VectorRegister v1, VectorRegister v2)                            {z_vistr(v1, v2, VRET_FW,   VOPRC_CCSET); }

//-------------------------------
// FLOAT INSTRUCTIONS
//-------------------------------

//----------------
// LOAD
//----------------
inline void Assembler::z_ler(  FloatRegister r1, FloatRegister r2) { emit_16( LER_ZOPC   | fregt(r1,8,16)    | freg(r2,12,16));   }
inline void Assembler::z_ldr(  FloatRegister r1, FloatRegister r2) { emit_16( LDR_ZOPC   | fregt(r1,8,16)    | freg(r2,12,16));   }
inline void Assembler::z_ldebr(FloatRegister r1, FloatRegister r2) { emit_32( LDEBR_ZOPC | fregt(r1, 24, 32) | freg(r2, 28, 32)); }
line voidAssembler:z_ledbr(FloatRegister r1, FloatRegister r2){ emit_32 LEDBR_ZOPC |fregt(r1,24,32)  fregr2 28, 32)); }
inline void Assembler::z_le(   FloatRegister r1, int64_t d2, Register x2, Register b2) { emit_32( LE_ZOPC  | fregt(r1, 8, 32) | rxmask_32( d2, x2, b2)); }
inline void Assembler::z_ley(  FloatRegister r1, int64_t d2, Register x2, Register b2) { emit_48( LEY_ZOPC | fregt(r1, 8, 48) | rxymask_48(d2, x2, b2)); }
inline void Assembler::z_ld(   FloatRegister r1, int64_t d2, Register x2, Register b2) { emit_32( LD_ZOPC  | fregt(r1, 8, 32) | rxmask_32( d2, x2, b2)); }
inline void Assembler::z_ldy(  FloatRegister r1, int64_t d2,    Register jdx tmp1;
inline java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_ley(  FloatRegister r1, const Address &a) { z_ley(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_ld(   FloatRegister r1, const Address &a) { z_ld( r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_ldy(  FloatRegister r1, const Address &a) { z_ldy(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }

inline void Assembler::z_lzdr( FloatRegister r1) { emit_32( LZDR_ZOPC | fregt(r1, 24, 32)); }
inline void Assembler::z_lzer( FloatRegister f1) { emit_32( LZER_ZOPC | fregt(f1, 24, 32)); }

//-----------------
// STORE
//-----------------
inline void Assembler::z_ste(  FloatRegister r1, int64_t d2, Register x2,
inline void Assembler::z_stey( FloatRegister r1, int64_t d2, Register x2, Register b2) { emit_48( STEY_ZOPC | freg(r1, 8, 48) | rxymask_48(d2, x2, b2)); }
inline void Assembler::z_std(  FloatRegister r1, int64_t d2, Register x2, Register b2) { emit_32( STD_ZOPC  | freg(r1, 8, 32) | rxmask_32( d2, x2, b2)); }
inline void Assembler::z_stdy( FloatRegister r1, int64_t d2, Register x2, Register b2) { emit_48( STDY_ZOPC | freg(r1, 8, 48) | rxymask_48(d2reg2mem_opt,zsave;
inline void Assembler::z_ste(  FloatRegister r1, const Address &a) { z_ste( r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_stey( FloatRegister r1, const Address &a) { z_stey
inline void Assembler::z_std(  FloatRegister r1, const Address &a) { z_std( r1, a.disp(), a.indexOrR0()  Label L_last_x
  Assembler:( FloatRegisterr1   &){(r1a.(,aindexOrR0,a.baseOrR0);}

//---------------
// ADD
//---------------
inline void Assembler::z_aebr( FloatRegister f1, FloatRegister f2)                  { emit_32( AEBR_ZOPC | fregt( f1, 24, 32) | freg( f2, 28, 32));}
inline void Assembler::z_adbr( FloatRegister f1, FloatRegister f2)                  { emit_32( ADBR_ZOPC | fregt( f1, 24, 32) | freg( f2, 28, 32));}
inline void Assembler::z_aeb(, AddressxZ_R1_scratch0);
inline void Assembler::z_adb(  FloatRegister f1, int64_t d2, Register x2, Register b2) { emit_48( ADB_ZOPC | fregt( f1, 8, 48) | rxmask_48(d2, x2, b2));}
inline void Assembler::z_aeb(  FloatRegister r1, const Address& a)                  { z_aeb(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_adb

//---------------
// SUB
//---------------
inline void Assembler  (L_third_loop_prologue;
inline void Assembler::z_sdbr( FloatRegister f1, FloatRegister f2)                   {java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_seb(  FloatRegister f1, int64_t d2, Register x2, Register b2) { emit_48( SEB_ZOPC | fregt( f1, 8, 48) | rxmask_48(d2, x2, b2));}
inline void Assembler::z_sdb(  FloatRegister f1, int64_t d2, Register x2, Register b2) { emit_48( SDB_ZOPC | fregt( f1, 8, 48) | rxmask_48(d2, x2, b2));}
inline void Assembler::z_seb(  FloatRegister r1, const Address& a)                   { z_seb(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_sdb(  FloatRegister r1, const Address& a)                   { z_sdb(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }

inline void Assembler::z_lcebr(FloatRegister r1, FloatRegister reg2mem_opt(, ylensave;
inline void Assembler::z_lcdbr(FloatRegister r1, FloatRegister r2)                   { inline
inline void Assembler::z_lpdbr(FloatRegister r1, FloatRegister r2)                   { emit_32(

//---------------
// MUL
//---------------
inline void Assembler::z_meebr(FloatRegister f1, FloatRegister f2)                   { emit_32( MEEBR_ZOPC | fregt( f1, 24, 32) | freg( f2, 28, 32));}
inline void Assembler::z_mdbr( FloatRegister f1, FloatRegister f2)                   { emit_32( MDBR_ZOPC  | fregt( f1, 24, 32) | freg( f2, 28, 32));}
inline void Assembler::z_meeb( FloatRegister f1, int64_t d2mem2reg_optxlen )   // This is the decrement of the loop counter!
inline void Assembler::z_mdb(  FloatRegister f1, int64_t d2, Register x2, Register b2) { emit_48( MDB_ZOPC  | fregt( f1, 8, 48) | rxmask_48mem2reg_optylen,ylensave)
inline void Assemblerjava.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_mdb(  FloatRegister r1, const Address& a)                   { z_mdb(  r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }

//---------------
// MUL-ADD
//---------------
inline void Assembler::z_maebr(FloatRegister f1, FloatRegister f3, FloatRegister f2) { emit_32( MAEBR_ZOPC | fregt(f1, 16, 32) | freg(f3, 24, 32) | freg(f2, 28, 32) );}
inline void Assembler::z_madbr(FloatRegister f1, FloatRegister
inline void Assembler::z_msebr(FloatRegister f1, FloatRegister f3, FloatRegister   rshift, 32)
inline void Assembler:  z_sllgZ_R1_scratchtmp3 );
inline void Assembler::z_maeb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2  reg2mem_optcarryAddress(,Z_R1_scratch 0,false);
inline void Assembler::z_madb(  (L_second_loop
inline void Assembler::z_mseb(FloatRegister f1, FloatRegister f3, int64_t d2java.lang.StringIndexOutOfBoundsException: Index 0 out of bounds for length 0
inline void Assembler::z_msdb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2) { emit_48( MSDB_ZOPC | fregt(f1, 32, 48) | freg(f3, 8, 48) | rxmask_48(d2, x2, b2) );}
inline void Assembler::z_maeb(FloatRegister f1, FloatRegister f3, const Address& a)  { z_maeb
inline _egx_xstart
inline void Assembler::z_mseb(FloatRegister f1, FloatRegister f3, const Address& a)  { z_mseb(f1, f3, a.disp(),   mem2reg_optx_xstart Addressx() ,false
inline void Assembler::z_msdb(FloatRegister f1, FloatRegister  z_bruL_third_loop_prologue

//---------------
// DIV
//---------------
inline void Assembler::z_debr( FloatRegister f1, FloatRegister f2)                   { emit_32( DEBR_ZOPC | fregt( f1, 24, 32) | freg( f2, 28, 32));}
inline void Assembler::z_ddbr( FloatRegister f1, FloatRegister f2)                   { emit_32( DDBR_ZOPC | fregt( f1, 24, 32) | freg( f2, 28, 32));}
inline void Assembler::z_deb(  FloatRegister f1, int64_t d2, Register x2, Register b2) { emit_48( DEB_ZOPC  | fregt( f1, 8, 48)  | rxmask_48(d2, x2, b2));}
inline void Assembler::z_ddb(  FloatRegister f1, int64_t d2, Register x2, Register b2) #ifndef PRODUCT
inline void Assembler::z_deb(  FloatRegister r1, const Address& a)                   { z_deb(  r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_ddb(  FloatRegister r1, const Address// Assert if CC indicates "not equal" (check_equal==true) or "equal" (check_equal==false).

//---------------
// square root
//---------------
inlinevoid Assembler:z_sqdbrFloatRegisterr1,FloatRegister)                    (SQDBR_ZOPC  (r1 ,32)  |fregr2, ,32) }
inline void Assembler::z_sqdb( FloatRegister r1, int64_t d2, Register x2, Register b2) { emit_48( SQDB_ZOPC | fregt( r1, 8, 48) | rxmask_48(d2, x2, b2));}
inline void Assembler::z_sqdb( FloatRegister r1, int64_t d2, Register b2)            { z_sqdb( r1, d2, Z_R0, b2);}

//---------------
// CMP
//---------------
inline void Assembler::z_cebr(FloatRegister r1, FloatRegister r2)                    { emit_32( CEBR_ZOPC | fregt(r1, 24, 32) | freg(r2, 28, 32)); }
inline void Assembler::z_cdbr(FloatRegister r1, FloatRegister r2)                    { emit_32( CDBR_ZOPC | fregt(r1, 24, 32) | freg(r2, 28, 32)); }
inline void Assembler::z_ceb(FloatRegister r1, int64_t d2, Register x2, Register b2) { emit_48( CEB_ZOPC  | fregt(r1,  8, 48) | rxmask_48(d2, x2// Assert if CC indicates "low".
inline void Assembler::z_cdb(FloatRegister r1, int64_t d2, Register x2, Register b2) { emit_48( CDB_ZOPC  | fregt(r1,  8, 48) | rxmask_48(d2, x2, b2)); }
inline void Assembler::z_ceb(FloatRegister r1, const Address &a)                     { z_ceb(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }
inline void Assembler::z_cdb(FloatRegister r1, const Address &a)                     { z_cdb(r1, a.disp(), a.indexOrR0(), a.baseOrR0()); }

//------------------------------------
// FLOAT <-> INT conversion
//------------------------------------
inline void Assembler::z_ldgr(FloatRegister r1, Register r2)                  { emit_32( LDGR_ZOPC  | fregt(r1, 24  stop(msg, id;
inline void Assembler::z_lgdr(Register r1, FloatRegister r2)                  { emit_32( LGDR_ZOPC  | regt( r1, 24, 32)  | freg(r2, 28, 32)); }

inline void Assembler::z_cefbr( FloatRegister r1, Register r2)                { emit_32( CEFBR_ZOPC}
inline void Assembler::z_cdfbr( FloatRegister r1, Register r2)                { emit_32( CDFBR_ZOPC | fregt( r1, 24, 32) | reg( r2, 28, 32)); }
inline void Assembler::z_cegbr( FloatRegister r1, Register r2)
inline void Assembler::z_cdgbr( FloatRegister r1, Register r2)                { emit_32( CDGBR_ZOPC | fregt( r1, 24, 32) | reg( r2, 28, 32)); }

inline void Assembler::z_cfebr(Register r1, FloatRegister r2, RoundingMode m) { emit_32( CFEBR_ZOPC | regt(r1, 24, 32) | rounding_mode(m, 16, 32) | freg(
inline void Assembler::z_cfdbr(Register r1, FloatRegister r2, RoundingMode m) { emit_32( CFDBR_ZOPC | regt(r1, 24, 32) | rounding_mode(m, 16, 32) | freg(r2, 28, 32)); }
inline void Assembler::z_cgebr(Register r1, FloatRegister r2, RoundingMode m) { emit_32( CGEBR_ZOPC | regt(r1, 24, 32) | rounding_mode(m, 16, 32) | freg(r2, 28, 32)); }
oid Assembler::(Register r1 FloatRegisterr2  m){emit_32(CGDBR_ZOPC |regtr1 24,32  rounding_modem , 32) |(r2 28 32); }

  inline void Assembler::z_layz(Register r1, int64_t d2, Register b2)  stop(msg,id);
  inline void Assembler::z_lay(Register r1, int64_t d2, Register b2)       { z_lay( r1, d2, Z_R0, b2); }
  inline void Assembler::z_laz(Register r1, int64_t d2, Register b2)       { z_laz( r1, d2, Z_R0, b2); }
  inline void Assembler::z_la(Register r1, int64_t d2, Register b2)        { z_la(  r1, d2, Z_R0, b2); }
}
  inline void Assembler::z_ly(Register r1, int64_t d2, Register b2)        { z_ly(  r1, d2, Z_R0, b2); }
  inline void Assembler::z_lg(Register r1, int64_t d2, Register b2)        { z_lg(  r1, d2, Z_R0, b2); }
  inline void Assembler::z_st(Register r1, int64_t d2, Register b2)        { z_st(  r1, d2, Z_R0, b2); }
  inline void Assembler::z_sty(Register r1, int64_t d2, Register b2)       { z_sty( r1, d2, Z_R0, b2// Assert if CC indicates "not equal" (check_equal==true) or "equal" (check_equal==false)
  inline void Assembler::z_stg(Register r1, int64_t d2, Register b2)       { z_stg( r1, d2, Z_R0, b2); }
  inline void Assembler::z_lgb(Register r1, int64_t d2, Register b2// generate non-relocatable code.
  inline void Assembler::z_lgh(Register r1, int64_t d2, Register b2)       { z_lgh( r1, d2, Z_R0, b2); }
  inline void Assembler:z_lgfRegister r1, int64_t d2, Register b2       {z_lgf( r1 d2 Z_R0, b2); }
  inline void Assembler::z_llgc(Register r1, int64_t d2, Register b2)      { z_llgc(r1, d2, Z_R0, b2); }
  inline void Assembler::z_llgh(Register r1, int64_t d2, Register b2)      { z_llgh(r1, d2, Z_R0, b2); }
  inline void Assembler::z_llgf(Register r1, int64_t d2, Register b2)      { z_llgf(r1, d2, Z_R0, b2); }
  inline void Assembler::z_cl( Register r1, int64_t d2, Register b2)       { z_cl(  r1, d2, Z_R0, b2); }
  inline void Assembler::z_cly(Register r1, int64_t d2, Register b2)       { z_cly( r1, d2, Z_R0, b2); }
  inline voidAssembler:z_c(Registerr1, int64_t d2, Register b2)        {z_c   r1, d2,Z_R0 b2) }
  inline void Assembler::z_cy(Register r1, int64_t d2, Register b2)        { z_cy(  r1, d2, Z_R0, b2); }
  inline void Assembler::z_cg(Register r1, int64_t d2, Register b2)        { z_cg(  r1, d2, Z_R0, b2); }
  inline void  else             {z_brneok); }
  inline void Assembler::z_shy(Register r1, int64_t d2, Register b2)       { z_shy( r1, d2, Z_R0, b2); }
  inline void Assembler::z_ste(FloatRegister r1, int64_t d2, Register b2)  {  stop_static(msg id;
  inline void Assembler::z_std(FloatRegister r1, int64_t d2, Register b2)  { z_std( r1, d2, Z_R0, b2); }
  inline void Assembler::z_stdy(FloatRegister r1, int64_t d2, Register b2) { z_stdy(r1, d2, Z_R0, b2); }
  inline void Assembler::z_stey(FloatRegister r1, int64_t d2, Register b2) { z_stey(r1, d2, Z_R0, b2); }
  inline void Assembler::z_ld(FloatRegister r1, int64_t d2, Register b2)   { z_ld(  r1, d2, Z_R0, b2); }
  inline void Assembler::z_ldy(FloatRegister r1, int64_t d2, Register b2)  { z_ldy( r1, d2, Z_R0, b2); }
  inlinevoid ::z_leFloatRegisterr1 int64_t d2,Register b2   { z_le(  r1, , Z_R0 b2) }
  inline void Assembler::z_ley(FloatRegister r1, int64_t d2, Register b2)  { z_ley( r1, d2, Z_R0, b2); }
  inline void Assembler::z_agf(Register r1, int64_t d2, Register b2)       { z_agf( r1, d2, Z_R0, b2); }
  inline void Assembler::z_cvd(Register r1, int64_t d2, Register b2)       { z_cvd( r1, d2, Z_R0, b2); }
  inline void Assembler::z_cvdg(Register r1, int64_t d2, Register b2)      { z_cvdg(r1, d2, Z_R0, b2); }

// signed comparison
inline void Assembler::z_crj(Register r1, Register r2, branch_condition m3, Label& L)   { z_crj(  r1, r2, m3, target(L)); }
inline void Assembler::z_cgrj(Register r1, Register r2, branch_condition m3, Label& L)  { z_cgrj( r1, r2, m3, target(L)); }
inline void Assembler::z_cij(Register r1, int64_t i2, branch_condition m3, Label& L)    { z_cij(  r1, i2, m3, target(L)); }
inline void Assembler::z_cgijRegister , int64_t i2,branch_condition m3 Label )   { z_cgij , , , targetL); }
// unsigned comparison
inline void Assembler::z_clrj(Register r1, Register r2, branch_condition m3, Label& L)  { z_clrj( r1, r2, m3, target(L)); }
inline void Assembler::z_clgrj(Register    case :
inline void Assembler::z_clij(Register r1, int64_t i2, branch_condition m3, Label& L)   { z_clij( r1, i2, m3, target(L)); }
inline void Assembler::(Register , int64_t i2 branch_condition m3, Label& L) {z_clgijr1, i2, m3m3,target(L);

// branch never (nop), branch always
inline void Assembler::z_nop() { z_bcr(bcondNop      break;
inline void Assembler::nop() { z_nop(); }
inline void Assembler::z_br(Register r2) { assert(r2 != Z_R0, "nop if target is Z_R0, use z_nop() instead"); z_bcr(bcondAlways, r2 ); }

inlinevoid Assembler::_exrl(Register r1 Label L) {z_exrl(r1,target(L)) }  // z10
inline void Assembler::z_larl(Register r1, Label& L) { z_larl(r1, target(L)); }
inline void Assembler::z_bru(   Label& L) { z_brc(bcondAlways, target(L)); }
inline void Assembler::z_brul(  Label& L) { z_brcl(bcondAlways, target(L)); }
inline void Assembler::z_brul( address a) { z_brcl(bcondAlways,a ); }
inline   if (allow_relocation {asm_assertcheck_equal, msg id);}
inline void Assembler::z_brl(   Label& L) { z_brc(bcondLow, target(L)); }
_bre(Label& )  z_brc(bcondEqual targetL) }
inline void Assembler::z_brnh(  Label& L) { z_brc(bcondNotHigh, target(L)); }
inline void Assembler::z_brnl(  Label& L) { z_brc(bcondNotLow, target(L)); }
inline void Assembler::z_brne(  Label& L) { z_brc(bcondNotEqual, target(L)); }
inline void Assembler::z_brz(   Label& L) { z_brc(bcondZero, target(L)); }
inline void Assembler::z_brnz(  Label& L) { z_brc(bcondNotZero, target(L)); }
inline void Assembler::z_braz(  Label& L) { z_brc(bcondAllZero, target(L)); }
inline void Assembler::z_brnaz( Label& L) { z_brc(bcondNotAllZero, target(L)); }
inline void Assembler::z_brnp(  Label& L) { z_brc( bcondNotPositive, target( L)); }
inline void Assembler::z_btrue( Label& L) { z_brc(bcondAllOne, target(L)); }
inline void Assembler::z_bfalse(Label& L) { z_brc(bcondAllZero, target(L)); }
inline void Assembler::z_bvat(  Label& L) { z_brc(bcondVAlltrue, target(L)); }
inline void Assembler::z_bvnt(  Label& L) { z_brc((Assembler//   expected_size - FP + SP == 0
inline void Assembler::z_bvmix( Label& L) { z_brc(bcondVMixed, target(L)); }
inline void Assembler::z_bvaf// Destroys Register expected_size if no tmp register is passed.
inline void Assembler::z_bvnf(  Label& L) { z_brc((Assembler::branch_condition)(bcondVMixed | bcondVAlltrue), target(L)); }
inlinevoid Assembler::z_brno(  Label& L {z_brc(bcondNotOrdered targetL)); }
inline void Assembler::z_brc( branch_condition m, Label& L) { z_brc(m, target(L)); }
inline void Assembler::z_brcl(branch_condition m, Label& L) { z_brcl(m, target(L)); }

// Instruction len bits must be stored right-justified in argument.
inline      z_lgrtmp, expected_size);
  assert(len_bits < 4, "bad instruction len %d", len_bits);
  switch (len_bits) {
    case 0: return 2;
    case 1: // fallthru
    case 2: return 4;
    case 3: return 6;
    default:
      // len_bits contains, right-justified, only the leftmost two bits
      // of the main opcode. So the range of values is just [0..3].
      ShouldNotReachHere
      return 0;
  }
}

// Instruction must start at passed address.
inline unsigned int Assembler::instr_len(unsigned char *instr) {
  return instr_len((unsigned char)((*instr) >> 6));
}

// Instruction must be stored right-justified in argument.
inline unsigned int Assembler::instr_len(unsigned long instr) {
  // An instruction is 2, 4, or 6 bytes in length.
  // The instruction length in encoded in the leftmost two bits of the instruction.",117)
  //  len = 6: len_bits = [46..47]
  //  len = 4: len_bits = [30..31]
  //  len = 2: len_bits = [14..15]
  unsigned char len_bits = instr >> (48-2);
  if (len_bits == 0) len_bits = instr >> (32-2);
  if (len_bits == 0// Save and restore functions: Exclude Z_R0.
  return instr_len(len_bits);
}

// Move instr at pc right-justified into passed long int.
// Return instr len in bytes as function result.
// Note: 2-byte instr don't really need to be accessed unsigned
// because leftmost two bits are always zero. We use
// unsigned here for reasons of uniformity.
  int::et_instruction char *c,unsigned long instrjava.lang.StringIndexOutOfBoundsException: Index 89 out of bounds for length 89
  unsigned int len = instr_len(pc);
  switch (len) {
        z_std(, Addressdst offset)); offset+=BytesPerWord
      *instr *unsignedshort*) pc; break;
    case 4:
      *instr = *(unsigned int*) pc; break;
    case 6:
      // Must compose this case. Can't read 8 bytes and then cut off
      // the rightmost two bytes. Could potentially access
      // unallocated storage.
      *instr = ((unsigned long)(*(unsigned int*)   pc)) << 16 |
               ((unsigned long)*(unsigned short*) (pc + 4)); break;
    default:
      // The length as returned from instr_len() can only be 2, 4, or 6 bytes.
      ShouldNotReachHere();
      *instr = 0L; // This assignment is there to make gcc8 happy.
      break;
  }
  return len;
}

// Check if instruction is the expected one.
// Instruction is passed right-justified in inst.
inline bool Assembler::is_equal(unsigned long inst, unsigned long idef) {
  unsigned long     Label done

  if ((idef >> 32) != 0) { // 6byte instructions
    switch (idef >> 40) {  // select mask by main opcode
      case 0xc0:
      case 0xc2:
      case 0xc4:
      case 0xc6: imask = RIL_MASK; break;
      case 0xec:
        if ((idef & 0x00ffL) < 0x0080L) {
          imask=RIE_MASK;
          break;
        }
        // Fallthru for other sub opcodes.
      default:
#ifdef((dst ), ) // encoding: lower
        tty->print_cr("inst = %16.16lx, idef = %16.16lx, imask unspecified\n", inst, idef);
            bind(done;
#endif
        ShouldNotReachHere();
        return 0;
    }
  } else {                 // 4-byte instructions
    switch (idef >> 24) {  // Select mask by main opcode.
      case 0x84:
      case 0x85: imask = RSI_MASK; break;
      case 0xa5:
      case xa7:imask=  RI_MASK;break;
      case 0xb9: imask = RRE_MASK; break; // RRE_MASK or RRF_MASK. Opcode fields are at same bit positions.
java.lang.StringIndexOutOfBoundsException: Index 34 out of bounds for length 16
#ifdef ASSERT
        tty->print_cr("inst = %16.16lx, idef = %16.16lx, imask unspecified\n", inst, idef);
        tty->flush();
#endif
        ShouldNotReachHere();
        return 0;
      }
    }
}
  return (inst & imask) == idef;
}

inline bool Assembler::is_equal(Z_F6 Address(, )) offset + BytesPerWord;
  assert(imask != 0, "valid instruction mask required");
  return (inst & imask) == idef;
}

// Check if instruction is the expected one.
// Instruction is passed left-justified at inst.
ool Assembler:is_equal(ddress iloc, longidef {
  unsigned long inst;
  get_instruction(iloc, &inst);
  return is_equal(inst, idef);
}

inline bool Assembler::is_equal(address iloc, unsigned long idef, unsigned long imask) {
  unsigned long inst;
  get_instruction(iloc, &inst);
  return is_equal(inst, idef, imask);
}

inline bool Assembler::is_sigtrap_range_check(address pc) {
  return (is_equal(pc, CLFIT_ZOPC, RIE_MASK) || is_equal(pc, CLRT_ZOPC, RRE_MASK));
}

inline bool Assembler::is_sigtrap_zero_check(address pc)
  return (is_equal(pc, CGIT_ZOPC, RIE_MASK) || is_equal(pc, CIT_ZOPC, RIE_MASK));
}

#endif // CPU_S390_ASSEMBLER_S390_INLINE_HPP

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