/*
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* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER .
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* under the terms of the GNU General Public License version 2 only , as
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*
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* FITNESS FOR A PARTICULAR PURPOSE . See the GNU General Public License
* version 2 for more details ( a copy is included in the LICENSE file that
* accompanied this code ) .
*
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* 2 along with this work ; if not , write to the Free Software Foundation ,
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*/
#ifdef COMPILE_CRYPTO
// The Rijndael S-box and inverted S-box are embedded here for a faster access.
//
// Note about lookup tables (T1...T4 and T5..T8):
// The tables (boxes) combine ahead-of-time precalculated transposition and mixing steps as
// an alternative to a runtime calculation.
// The tables are statically generated in com/sun/crypto/provider/AESCrypt class.
// Only the first table reference is passed to AES methods below. The other 3 tables
// in ecryption and decryption are calculated in runtime by rotating the T1 result accordingly.
// It is a free operation on ARM with embedded register-shifted-register EOR capability.
// The table reference is passed in a form of a last argument on the parameters list.
// The tables lookup method proves to perform better than a runtime Galois Field calculation,
// due to a lack of HW acceleration for the later.
unsigned char * SBox;
unsigned char * SInvBox;
void aes_init() {
const static unsigned char Si[256 ] =
{
0 x52, 0 x09, 0 x6A, 0 xD5, 0 x30, 0 x36, 0 xA5, 0 x38,
0 xBF, 0 x40, 0 xA3, 0 x9E, 0 x81, 0 xF3, 0 xD7, 0 xFB,
0 x7C, 0 xE3, 0 x39, 0 x82, 0 x9B, 0 x2F, 0 xFF, 0 x87,
0 x34, 0 x8E, 0 x43, 0 x44, 0 xC4, 0 xDE, 0 xE9, 0 xCB,
0 x54, 0 x7B, 0 x94, 0 x32, 0 xA6, 0 xC2, 0 x23, 0 x3D,
0 xEE, 0 x4C, 0 x95, 0 x0B, 0 x42, 0 xFA, 0 xC3, 0 x4E,
0 x08, 0 x2E, 0 xA1, 0 x66, 0 x28, 0 xD9, 0 x24, 0 xB2,
0 x76, 0 x5B, 0 xA2, 0 x49, 0 x6D, 0 x8B, 0 xD1, 0 x25,
0 x72, 0 xF8, 0 xF6, 0 x64, 0 x86, 0 x68, 0 x98, 0 x16,
0 xD4, 0 xA4, 0 x5C, 0 xCC, 0 x5D, 0 x65, 0 xB6, 0 x92,
0 x6C, 0 x70, 0 x48, 0 x50, 0 xFD, 0 xED, 0 xB9, 0 xDA,
0 x5E, 0 x15, 0 x46, 0 x57, 0 xA7, 0 x8D, 0 x9D, 0 x84,
0 x90, 0 xD8, 0 xAB, 0 x00, 0 x8C, 0 xBC, 0 xD3, 0 x0A,
0 xF7, 0 xE4, 0 x58, 0 x05, 0 xB8, 0 xB3, 0 x45, 0 x06,
0 xD0, 0 x2C, 0 x1E, 0 x8F, 0 xCA, 0 x3F, 0 x0F, 0 x02,
0 xC1, 0 xAF, 0 xBD, 0 x03, 0 x01, 0 x13, 0 x8A, 0 x6B,
0 x3A, 0 x91, 0 x11, 0 x41, 0 x4F, 0 x67, 0 xDC, 0 xEA,
0 x97, 0 xF2, 0 xCF, 0 xCE, 0 xF0, 0 xB4, 0 xE6, 0 x73,
0 x96, 0 xAC, 0 x74, 0 x22, 0 xE7, 0 xAD, 0 x35, 0 x85,
0 xE2, 0 xF9, 0 x37, 0 xE8, 0 x1C, 0 x75, 0 xDF, 0 x6E,
0 x47, 0 xF1, 0 x1A, 0 x71, 0 x1D, 0 x29, 0 xC5, 0 x89,
0 x6F, 0 xB7, 0 x62, 0 x0E, 0 xAA, 0 x18, 0 xBE, 0 x1B,
0 xFC, 0 x56, 0 x3E, 0 x4B, 0 xC6, 0 xD2, 0 x79, 0 x20,
0 x9A, 0 xDB, 0 xC0, 0 xFE, 0 x78, 0 xCD, 0 x5A, 0 xF4,
0 x1F, 0 xDD, 0 xA8, 0 x33, 0 x88, 0 x07, 0 xC7, 0 x31,
0 xB1, 0 x12, 0 x10, 0 x59, 0 x27, 0 x80, 0 xEC, 0 x5F,
0 x60, 0 x51, 0 x7F, 0 xA9, 0 x19, 0 xB5, 0 x4A, 0 x0D,
0 x2D, 0 xE5, 0 x7A, 0 x9F, 0 x93, 0 xC9, 0 x9C, 0 xEF,
0 xA0, 0 xE0, 0 x3B, 0 x4D, 0 xAE, 0 x2A, 0 xF5, 0 xB0,
0 xC8, 0 xEB, 0 xBB, 0 x3C, 0 x83, 0 x53, 0 x99, 0 x61,
0 x17, 0 x2B, 0 x04, 0 x7E, 0 xBA, 0 x77, 0 xD6, 0 x26,
0 xE1, 0 x69, 0 x14, 0 x63, 0 x55, 0 x21, 0 x0C, 0 x7D
};
static const unsigned char S[256 ]={
0 x63, 0 x7C, 0 x77, 0 x7B, 0 xF2, 0 x6B, 0 x6F, 0 xC5,
0 x30, 0 x01, 0 x67, 0 x2B, 0 xFE, 0 xD7, 0 xAB, 0 x76,
0 xCA, 0 x82, 0 xC9, 0 x7D, 0 xFA, 0 x59, 0 x47, 0 xF0,
0 xAD, 0 xD4, 0 xA2, 0 xAF, 0 x9C, 0 xA4, 0 x72, 0 xC0,
0 xB7, 0 xFD, 0 x93, 0 x26, 0 x36, 0 x3F, 0 xF7, 0 xCC,
0 x34, 0 xA5, 0 xE5, 0 xF1, 0 x71, 0 xD8, 0 x31, 0 x15,
0 x04, 0 xC7, 0 x23, 0 xC3, 0 x18, 0 x96, 0 x05, 0 x9A,
0 x07, 0 x12, 0 x80, 0 xE2, 0 xEB, 0 x27, 0 xB2, 0 x75,
0 x09, 0 x83, 0 x2C, 0 x1A, 0 x1B, 0 x6E, 0 x5A, 0 xA0,
0 x52, 0 x3B, 0 xD6, 0 xB3, 0 x29, 0 xE3, 0 x2F, 0 x84,
0 x53, 0 xD1, 0 x00, 0 xED, 0 x20, 0 xFC, 0 xB1, 0 x5B,
0 x6A, 0 xCB, 0 xBE, 0 x39, 0 x4A, 0 x4C, 0 x58, 0 xCF,
0 xD0, 0 xEF, 0 xAA, 0 xFB, 0 x43, 0 x4D, 0 x33, 0 x85,
0 x45, 0 xF9, 0 x02, 0 x7F, 0 x50, 0 x3C, 0 x9F, 0 xA8,
0 x51, 0 xA3, 0 x40, 0 x8F, 0 x92, 0 x9D, 0 x38, 0 xF5,
0 xBC, 0 xB6, 0 xDA, 0 x21, 0 x10, 0 xFF, 0 xF3, 0 xD2,
0 xCD, 0 x0C, 0 x13, 0 xEC, 0 x5F, 0 x97, 0 x44, 0 x17,
0 xC4, 0 xA7, 0 x7E, 0 x3D, 0 x64, 0 x5D, 0 x19, 0 x73,
0 x60, 0 x81, 0 x4F, 0 xDC, 0 x22, 0 x2A, 0 x90, 0 x88,
0 x46, 0 xEE, 0 xB8, 0 x14, 0 xDE, 0 x5E, 0 x0B, 0 xDB,
0 xE0, 0 x32, 0 x3A, 0 x0A, 0 x49, 0 x06, 0 x24, 0 x5C,
0 xC2, 0 xD3, 0 xAC, 0 x62, 0 x91, 0 x95, 0 xE4, 0 x79,
0 xE7, 0 xC8, 0 x37, 0 x6D, 0 x8D, 0 xD5, 0 x4E, 0 xA9,
0 x6C, 0 x56, 0 xF4, 0 xEA, 0 x65, 0 x7A, 0 xAE, 0 x08,
0 xBA, 0 x78, 0 x25, 0 x2E, 0 x1C, 0 xA6, 0 xB4, 0 xC6,
0 xE8, 0 xDD, 0 x74, 0 x1F, 0 x4B, 0 xBD, 0 x8B, 0 x8A,
0 x70, 0 x3E, 0 xB5, 0 x66, 0 x48, 0 x03, 0 xF6, 0 x0E,
0 x61, 0 x35, 0 x57, 0 xB9, 0 x86, 0 xC1, 0 x1D, 0 x9E,
0 xE1, 0 xF8, 0 x98, 0 x11, 0 x69, 0 xD9, 0 x8E, 0 x94,
0 x9B, 0 x1E, 0 x87, 0 xE9, 0 xCE, 0 x55, 0 x28, 0 xDF,
0 x8C, 0 xA1, 0 x89, 0 x0D, 0 xBF, 0 xE6, 0 x42, 0 x68,
0 x41, 0 x99, 0 x2D, 0 x0F, 0 xB0, 0 x54, 0 xBB, 0 x16
};
SBox = (unsigned char *)S;
SInvBox = (unsigned char *)Si;
}
address generate_aescrypt_encryptBlock() {
__ align(CodeEntryAlignment);
StubCodeMark mark(this , "StubRoutines" , "aesencryptBlock" );
address start = __ pc();
// Register from = R0; // source byte array
// Register to = R1; // destination byte array
// Register key = R2; // expanded key array
// Register tbox = R3; // transposition box reference
__ push (RegisterSet(R4, R12) | LR);
__ fpush(FloatRegisterSet(D0, 4 ));
__ sub(SP, SP, 32 );
// preserve TBox references
__ add(R3, R3, arrayOopDesc::base_offset_in_bytes(T_INT));
__ str(R3, Address(SP, 16 ));
// retrieve key length. The length is used to determine the number of subsequent rounds (10, 12 or 14)
__ ldr(R9, Address(R2, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
__ ldr(R5, Address(R0));
__ ldr(R10, Address(R2, 4 , post_indexed));
__ rev(R5, R5);
__ eor(R5, R5, R10);
__ ldr(R6, Address(R0, 4 ));
__ ldr(R10, Address(R2, 4 , post_indexed));
__ rev(R6, R6);
__ eor(R6, R6, R10);
__ ldr(R7, Address(R0, 8 ));
__ ldr(R10, Address(R2, 4 , post_indexed));
__ rev(R7, R7);
__ eor(R7, R7, R10);
__ ldr(R8, Address(R0, 12 ));
__ ldr(R10, Address(R2, 4 , post_indexed));
__ rev(R8, R8);
__ eor(R8, R8, R10);
// Store the key size; However before doing that adjust the key to compensate for the Initial and Last rounds
__ sub(R9, R9, 8 );
__ fmsr(S7, R1);
// load first transporistion box (T1)
__ ldr(R0, Address(SP, 16 ));
__ mov(LR, R2);
Label round;
__ bind(round);
// Utilize a Transposition Box lookup along with subsequent shift and EOR with a round key.
// instructions ordering is rearranged to minimize ReadAferWrite dependency. Not that important on A15 target
// with register renaming but performs ~10% better on A9.
__ mov(R12, AsmOperand(R5, lsr, 24 ));
__ ubfx(R4, R6, 16 , 8 );
__ ldr (R1, Address(R0, R12, lsl, 2 ));
__ ldr(R2, Address(R0, R4, lsl, 2 ));
__ ubfx(R3, R7, 8 , 8 );
__ eor(R1, R1, AsmOperand(R2, ror, 8 ));
__ uxtb(R4, R8);
__ ldr(R3, Address(R0, R3, lsl, 2 ));
__ ldr(R4, Address(R0, R4, lsl, 2 ));
__ ldr(R12, Address(LR, 4 , post_indexed));
__ eor(R1, R1, AsmOperand(R3, ror, 16 ));
__ eor(R12, R12, AsmOperand(R4, ror, 24 ));
__ eor(R10, R1, R12);
__ mov(R12, AsmOperand(R6, lsr, 24 ));
__ ubfx(R4, R7, 16 , 8 );
__ ldr (R1, Address(R0, R12, lsl, 2 ));
__ ldr(R2, Address(R0, R4, lsl, 2 ));
__ ubfx(R3, R8, 8 , 8 );
__ eor(R1, R1, AsmOperand(R2, ror, 8 ));
__ uxtb(R4, R5);
__ ldr(R3, Address(R0, R3, lsl, 2 ));
__ ldr(R4, Address(R0, R4, lsl, 2 ));
__ ldr(R12, Address(LR, 4 , post_indexed));
__ eor(R1, R1, AsmOperand(R3, ror, 16 ));
__ eor(R12, R12, AsmOperand(R4, ror, 24 ));
__ eor(R11, R1, R12);
__ mov(R12, AsmOperand(R7, lsr, 24 ));
__ ubfx(R4, R8, 16 , 8 );
__ ldr (R1, Address(R0, R12, lsl, 2 ));
__ ldr(R2, Address(R0, R4, lsl, 2 ));
__ ubfx(R3, R5, 8 , 8 );
__ eor(R1, R1, AsmOperand(R2, ror, 8 ));
__ uxtb(R4, R6);
__ ldr(R3, Address(R0, R3, lsl, 2 ));
__ ldr(R4, Address(R0, R4, lsl, 2 ));
__ ldr(R12, Address(LR, 4 , post_indexed));
__ eor(R1, R1, AsmOperand(R3, ror, 16 ));
__ eor(R12, R12, AsmOperand(R4, ror, 24 ));
__ eor(R3, R1, R12);
__ str(R3, Address(SP, 0 ));
__ mov(R12, AsmOperand(R8, lsr, 24 ));
__ ubfx(R4, R5, 16 , 8 );
__ ldr (R1, Address(R0, R12, lsl, 2 ));
__ ldr(R2, Address(R0, R4, lsl, 2 ));
__ ubfx(R3, R6, 8 , 8 );
__ eor(R1, R1, AsmOperand(R2, ror, 8 ));
__ uxtb(R4, R7);
__ ldr(R3, Address(R0, R3, lsl, 2 ));
__ ldr(R4, Address(R0, R4, lsl, 2 ));
__ ldr(R12, Address(LR, 4 , post_indexed));
__ eor(R1, R1, AsmOperand(R3, ror, 16 ));
__ eor(R12, R12, AsmOperand(R4, ror, 24 ));
__ eor(R8, R1, R12);
// update round count
__ subs(R9, R9, 4 );
__ mov(R5, R10);
__ mov(R6, R11);
__ ldr(R7, Address(SP, 0 ));
__ b(round, gt);
// last round - a special case, no MixColumn
__ mov_slow(R10, (int )SBox);
// output buffer pointer
__ fmrs(R9, S7);
__ ldr(R11, Address(LR, 4 , post_indexed));
__ ldrb(R0, Address(R10, R5, lsr, 24 ));
__ ubfx(R12, R6, 16 , 8 );
__ ldrb(R1, Address(R10, R12));
__ orr(R0, R1, AsmOperand(R0, lsl, 8 ));
__ ubfx(R12, R7, 8 , 8 );
__ ldrb(R2, Address(R10, R12));
__ orr(R0, R2, AsmOperand(R0, lsl, 8 ));
__ uxtb (R12, R8);
__ ldrb(R3, Address(R10, R12));
__ orr(R0, R3, AsmOperand(R0, lsl, 8 ));
__ eor(R0, R0, R11);
__ rev(R0, R0);
__ str(R0, Address(R9, 4 , post_indexed));
__ ldr(R11, Address(LR, 4 , post_indexed));
__ ldrb(R0, Address(R10, R6, lsr, 24 ));
__ ubfx(R12, R7, 16 , 8 );
__ ldrb(R1, Address(R10, R12));
__ orr(R0, R1, AsmOperand(R0, lsl, 8 ));
__ ubfx(R12, R8, 8 , 8 );
__ ldrb(R2, Address(R10, R12));
__ orr(R0, R2, AsmOperand(R0, lsl, 8 ));
__ uxtb (R12, R5);
__ ldrb(R3, Address(R10, R12));
__ orr(R0, R3, AsmOperand(R0, lsl, 8 ));
__ eor(R0, R0, R11);
__ rev(R0, R0);
__ str(R0, Address(R9, 4 , post_indexed));
__ ldr(R11, Address(LR, 4 , post_indexed));
__ ldrb(R0, Address(R10, R7, lsr, 24 ));
__ ubfx(R12, R8, 16 , 8 );
__ ldrb(R1, Address(R10, R12));
__ orr(R0, R1, AsmOperand(R0, lsl, 8 ));
__ ubfx(R12, R5, 8 , 8 );
__ ldrb(R2, Address(R10, R12));
__ orr(R0, R2, AsmOperand(R0, lsl, 8 ));
__ uxtb (R12, R6);
__ ldrb(R3, Address(R10, R12));
__ orr(R0, R3, AsmOperand(R0, lsl, 8 ));
__ eor(R0, R0, R11);
__ rev(R0, R0);
__ str(R0, Address(R9, 4 , post_indexed));
__ ldr(R11, Address(LR));
__ ldrb(R0, Address(R10, R8, lsr, 24 ));
__ ubfx(R12, R5, 16 , 8 );
__ ldrb(R1, Address(R10, R12));
__ orr(R0, R1, AsmOperand(R0, lsl, 8 ));
__ ubfx(R12, R6, 8 , 8 );
__ ldrb(R2, Address(R10, R12));
__ orr(R0, R2, AsmOperand(R0, lsl, 8 ));
__ uxtb (R12, R7);
__ ldrb(R3, Address(R10, R12));
__ orr(R0, R3, AsmOperand(R0, lsl, 8 ));
__ eor(R0, R0, R11);
__ rev(R0, R0);
__ str(R0, Address(R9));
__ add(SP, SP, 32 );
__ fpop(FloatRegisterSet(D0, 4 ));
__ pop(RegisterSet(R4, R12) | PC);
return start;
}
address generate_aescrypt_decryptBlock() {
__ align(CodeEntryAlignment);
StubCodeMark mark(this , "StubRoutines" , "aesdecryptBlock" );
address start = __ pc();
// Register from = R0; // source byte array
// Register to = R1; // destination byte array
// Register key = R2; // expanded key array
// Register tbox = R3; // transposition box reference
__ push (RegisterSet(R4, R12) | LR);
__ fpush(FloatRegisterSet(D0, 4 ));
__ sub(SP, SP, 32 );
// retrieve key length
__ ldr(R9, Address(R2, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
// preserve TBox references
__ add(R3, R3, arrayOopDesc::base_offset_in_bytes(T_INT));
__ str(R3, Address(SP, 16 ));
// Preserve the expanded key pointer
__ fmsr(S8, R2);
// The first key round is applied to the last round
__ add(LR, R2, 16 );
__ ldr(R5, Address(R0));
__ ldr(R10, Address(LR, 4 , post_indexed));
__ rev(R5, R5);
__ eor(R5, R5, R10);
__ ldr(R6, Address(R0, 4 ));
__ ldr(R10, Address(LR, 4 , post_indexed));
__ rev(R6, R6);
__ eor(R6, R6, R10);
__ ldr(R7, Address(R0, 8 ));
__ ldr(R10, Address(LR, 4 , post_indexed));
__ rev(R7, R7);
__ eor(R7, R7, R10);
__ ldr(R8, Address(R0, 12 ));
__ ldr(R10, Address(LR, 4 , post_indexed));
__ rev(R8, R8);
__ eor(R8, R8, R10);
// Store the key size; However before doing that adjust the key to compensate for the Initial and Last rounds
__ sub(R9, R9, 8 );
__ fmsr(S7, R1);
// load transporistion box (T5)
__ ldr(R0, Address(SP, 16 ));
Label round;
__ bind(round);
// each sub-block is treated similarly:
// combine SubBytes|ShiftRows|MixColumn through a precalculated set of tables
// Utilize a Transposition Box lookup along with subsequent shift and EOR with a round key.
// instructions ordering is rearranged to minimize ReadAferWrite dependency. Not that important on A15 target
// with register renaming but performs ~10% better on A9.
__ mov(R12, AsmOperand(R5, lsr, 24 ));
__ ubfx(R4, R8, 16 , 8 );
__ ldr (R1, Address(R0, R12, lsl, 2 ));
__ ldr(R2, Address(R0, R4, lsl, 2 ));
__ ubfx(R3, R7, 8 , 8 );
__ eor(R1, R1, AsmOperand(R2, ror, 8 ));
__ uxtb(R4, R6);
__ ldr(R3, Address(R0, R3, lsl, 2 ));
__ ldr(R4, Address(R0, R4, lsl, 2 ));
__ ldr(R12, Address(LR, 4 , post_indexed));
__ eor(R1, R1, AsmOperand(R3, ror, 16 ));
__ eor(R12, R12, AsmOperand(R4, ror, 24 ));
__ eor(R10, R1, R12);
__ mov(R12, AsmOperand(R6, lsr, 24 ));
__ ubfx(R4, R5, 16 , 8 );
__ ldr (R1, Address(R0, R12, lsl, 2 ));
__ ldr(R2, Address(R0, R4, lsl, 2 ));
__ ubfx(R3, R8, 8 , 8 );
__ eor(R1, R1, AsmOperand(R2, ror, 8 ));
__ uxtb(R4, R7);
__ ldr(R3, Address(R0, R3, lsl, 2 ));
__ ldr(R4, Address(R0, R4, lsl, 2 ));
__ ldr(R12, Address(LR, 4 , post_indexed));
__ eor(R1, R1, AsmOperand(R3, ror, 16 ));
__ eor(R12, R12, AsmOperand(R4, ror, 24 ));
__ eor(R11, R1, R12);
__ mov(R12, AsmOperand(R7, lsr, 24 ));
__ ubfx(R4, R6, 16 , 8 );
__ ldr (R1, Address(R0, R12, lsl, 2 ));
__ ldr(R2, Address(R0, R4, lsl, 2 ));
__ ubfx(R3, R5, 8 , 8 );
__ eor(R1, R1, AsmOperand(R2, ror, 8 ));
__ uxtb(R4, R8);
__ ldr(R3, Address(R0, R3, lsl, 2 ));
__ ldr(R4, Address(R0, R4, lsl, 2 ));
__ ldr(R12, Address(LR, 4 , post_indexed));
__ eor(R1, R1, AsmOperand(R3, ror, 16 ));
__ eor(R12, R12, AsmOperand(R4, ror, 24 ));
__ eor(R3, R1, R12);
__ str(R3, Address(SP, 0 ));
__ mov(R12, AsmOperand(R8, lsr, 24 ));
__ ubfx(R4, R7, 16 , 8 );
__ ldr (R1, Address(R0, R12, lsl, 2 ));
__ ldr(R2, Address(R0, R4, lsl, 2 ));
__ ubfx(R3, R6, 8 , 8 );
__ eor(R1, R1, AsmOperand(R2, ror, 8 ));
__ uxtb(R4, R5);
__ ldr(R3, Address(R0, R3, lsl, 2 ));
__ ldr(R4, Address(R0, R4, lsl, 2 ));
__ ldr(R12, Address(LR, 4 , post_indexed));
__ eor(R1, R1, AsmOperand(R3, ror, 16 ));
__ eor(R12, R12, AsmOperand(R4, ror, 24 ));
__ eor(R8, R1, R12);
// update round count
__ subs(R9, R9, 4 );
__ mov(R5, R10);
__ mov(R6, R11);
__ ldr(R7, Address(SP, 0 ));
__ b(round, gt);
// last round - a special case, no MixColumn:
// Retrieve expanded key pointer
__ fmrs(LR, S8);
__ mov_slow(R10, (int )SInvBox);
// output buffer pointer
__ fmrs(R9, S7);
// process each sub-block in a similar manner:
// 1. load a corresponding round key
__ ldr(R11, Address(LR, 4 , post_indexed));
// 2. combine SubBytes and ShiftRows stages
__ ldrb(R0, Address(R10, R5, lsr, 24 ));
__ ubfx(R12, R8, 16 , 8 );
__ ldrb(R1, Address(R10, R12));
__ orr(R0, R1, AsmOperand(R0, lsl, 8 ));
__ ubfx(R12, R7, 8 , 8 );
__ ldrb(R2, Address(R10, R12));
__ orr(R0, R2, AsmOperand(R0, lsl, 8 ));
__ uxtb (R12, R6);
__ ldrb(R3, Address(R10, R12));
__ orr(R3, R3, AsmOperand(R0, lsl, 8 ));
// 3. AddRoundKey stage
__ eor(R0, R3, R11);
// 4. convert the result to LE representation
__ rev(R0, R0);
// 5. store in the output buffer
__ str(R0, Address(R9, 4 , post_indexed));
__ ldr(R11, Address(LR, 4 , post_indexed));
__ ldrb(R0, Address(R10, R6, lsr, 24 ));
__ ubfx(R12, R5, 16 , 8 );
__ ldrb(R1, Address(R10, R12));
__ orr(R0, R1, AsmOperand(R0, lsl, 8 ));
__ ubfx(R12, R8, 8 , 8 );
__ ldrb(R2, Address(R10, R12));
__ orr(R0, R2, AsmOperand(R0, lsl, 8 ));
__ uxtb (R12, R7);
__ ldrb(R3, Address(R10, R12));
__ orr(R0, R3, AsmOperand(R0, lsl, 8 ));
__ eor(R0, R0, R11);
__ rev(R0, R0);
__ str(R0, Address(R9, 4 , post_indexed));
__ ldr(R11, Address(LR, 4 , post_indexed));
__ ldrb(R0, Address(R10, R7, lsr, 24 ));
__ ubfx(R12, R6, 16 , 8 );
__ ldrb(R1, Address(R10, R12));
__ orr(R0, R1, AsmOperand(R0, lsl, 8 ));
__ ubfx(R12, R5, 8 , 8 );
__ ldrb(R2, Address(R10, R12));
__ orr(R0, R2, AsmOperand(R0, lsl, 8 ));
__ uxtb (R12, R8);
__ ldrb(R3, Address(R10, R12));
__ orr(R0, R3, AsmOperand(R0, lsl, 8 ));
__ eor(R0, R0, R11);
__ rev(R0, R0);
__ str(R0, Address(R9, 4 , post_indexed));
__ ldr(R11, Address(LR));
__ ldrb(R0, Address(R10, R8, lsr, 24 ));
__ ubfx(R12, R7, 16 , 8 );
__ ldrb(R1, Address(R10, R12));
__ orr(R0, R1, AsmOperand(R0, lsl, 8 ));
__ ubfx(R12, R6, 8 , 8 );
__ ldrb(R2, Address(R10, R12));
__ orr(R0, R2, AsmOperand(R0, lsl, 8 ));
__ uxtb (R12, R5);
__ ldrb(R3, Address(R10, R12));
__ orr(R0, R3, AsmOperand(R0, lsl, 8 ));
__ eor(R0, R0, R11);
__ rev(R0, R0);
__ str(R0, Address(R9));
__ add(SP, SP, 32 );
__ fpop(FloatRegisterSet(D0, 4 ));
__ pop(RegisterSet(R4, R12) | PC);
return start;
}
address generate_cipherBlockChaining_encryptAESCrypt() {
// R0 - plain
// R1 - cipher
// R2 - expanded key
// R3 - Initialization Vector (IV)
// [sp+0] - cipher len
// [sp+4] Transposition Box reference
__ align(CodeEntryAlignment);
StubCodeMark mark(this , "StubRoutines" , "cipherBlockChaining_encryptAESCrypt" );
address start = __ pc();
__ push(RegisterSet(R4, R12) | LR);
// load cipher length (which is first element on the original calling stack)
__ ldr(R4, Address(SP, 40 ));
__ sub(SP, SP, 32 );
// preserve some arguments
__ mov(R5, R1);
__ mov(R6, R2);
// load IV
__ ldmia(R3, RegisterSet(R9, R12), writeback);
// preserve original source buffer on stack
__ str(R0, Address(SP, 16 ));
Label loop;
__ bind(loop);
__ ldmia(R0, RegisterSet(R0, R1) | RegisterSet(R7, R8));
__ eor(R0, R0, R9);
__ eor(R1, R1, R10);
__ eor(R7, R7, R11);
__ eor(R8, R8, R12);
__ stmia(SP, RegisterSet(R0, R1) | RegisterSet(R7, R8));
__ mov(R0, SP);
__ mov(R1, R5);
__ mov(R2, R6);
__ ldr(R3, Address(SP, 40 +32 +4 ));
// near call is sufficient since the target is also in the stubs
__ bl(StubRoutines::_aescrypt_encryptBlock);
__ subs(R4, R4, 16 );
__ ldr(R0, Address(SP, 16 ), gt);
__ ldmia(R5, RegisterSet(R9, R12), writeback);
__ add(R0, R0, 16 , gt);
__ str(R0, Address(SP, 16 ), gt);
__ b(loop, gt);
__ add(SP, SP, 32 );
__ pop(RegisterSet(R4, R12) | LR);
// return cipher len (copied from the original argument)
__ ldr(R0, Address(SP));
__ bx(LR);
return start;
}
// The CBC decryption could benefit from parallel processing as the blocks could be
// decrypted separately from each other.
// NEON is utilized (if available) to perform parallel execution on 8 blocks at a time.
// Since Transposition Box (tbox) is used the parallel execution will only apply to an
// Initial Round and the last round. It's not practical to use NEON for a table lookup
// larger than 128 bytes. It also appears to be faster performing tbox lookup
// sequentially then execute Galois Field calculation in parallel.
address generate_cipherBlockChaining_decryptAESCrypt() {
__ align(CodeEntryAlignment);
StubCodeMark mark(this , "StubRoutines" , "cipherBlockChaining_decryptAESCrypt" );
address start = __ pc();
Label single_block_done, single_block, cbc_done;
// R0 - cipher
// R1 - plain
// R2 - expanded key
// R3 - Initialization Vector (iv)
// [sp+0] - cipher len
// [sp+4] - Transpotition Box reference
__ push(RegisterSet(R4, R12) | LR);
// load cipher len: must be modulo 16
__ ldr(R4, Address(SP, 40 ));
if (VM_Version::has_simd()) {
__ andrs(R4, R4, 0 x7f);
}
// preserve registers based arguments
__ mov(R7, R2);
__ mov(R8, R3);
if (VM_Version::has_simd()) {
__ b(single_block_done, eq);
}
__ bind(single_block);
// preserve args
__ mov(R5, R0);
__ mov(R6, R1);
// reload arguments
__ mov(R2, R7);
__ ldr(R3, Address(SP, 40 +4 ));
// near call is sufficient as the method is part of the StubGenerator
__ bl((address)StubRoutines::_aescrypt_decryptBlock);
// check remaining cipher size (for individual block processing)
__ subs(R4, R4, 16 );
if (VM_Version::has_simd()) {
__ tst(R4, 0 x7f);
}
// load IV (changes based on a CBC schedule)
__ ldmia(R8, RegisterSet(R9, R12));
// load plaintext from the previous block processing
__ ldmia(R6, RegisterSet(R0, R3));
// perform IV addition and save the plaintext for good now
__ eor(R0, R0, R9);
__ eor(R1, R1, R10);
__ eor(R2, R2, R11);
__ eor(R3, R3, R12);
__ stmia(R6, RegisterSet(R0, R3));
// adjust pointers for next block processing
__ mov(R8, R5);
__ add(R0, R5, 16 );
__ add(R1, R6, 16 );
__ b(single_block, ne);
__ bind(single_block_done);
if (!VM_Version::has_simd()) {
__ b(cbc_done);
} else {
// done with single blocks.
// check if any 8 block chunks are available for parallel processing
__ ldr(R4, Address(SP, 40 ));
__ bics(R4, R4, 0 x7f);
__ b(cbc_done, eq);
Label decrypt_8_blocks;
int quad = 1 ;
// Process 8 blocks in parallel
__ fpush(FloatRegisterSet(D8, 8 ));
__ sub(SP, SP, 40 );
// record output buffer end address (used as a block counter)
Address output_buffer_end(SP, 16 );
__ add(R5, R1, R4);
__ str(R5, output_buffer_end);
// preserve key pointer
Address rounds_key(SP, 28 );
__ str(R7, rounds_key);
// in decryption the first 16 bytes of expanded key are used in the last round
__ add(LR, R7, 16 );
// Record the end of the key which is used to indicate a last round
__ ldr(R3, Address(R7, arrayOopDesc::length_offset_in_bytes() - arrayOopDesc::base_offset_in_bytes(T_INT)));
__ add(R9, R7, AsmOperand(R3, lsl, 2 ));
// preserve IV
Address iv(SP, 36 );
__ str(R8, iv);
__ bind(decrypt_8_blocks);
__ mov(R5, R1);
// preserve original source pointer
Address original_src(SP, 32 );
__ str(R0, original_src);
// Apply ShiftRow for 8 block at once:
// use output buffer for a temp storage to preload it into cache
__ vld1(D18, LR, MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vld1(D0, Address(R0, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vrev(D0, D0, quad, 32 , MacroAssembler::VELEM_SIZE_8);
__ veor(D20, D0, D18, quad);
__ vst1(D20, Address(R5, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vld1(D2, Address(R0, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vrev(D2, D2, quad, 32 , MacroAssembler::VELEM_SIZE_8);
__ veor(D20, D2, D18, quad);
__ vst1(D20, Address(R5, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vld1(D4, Address(R0, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vrev(D4, D4, quad, 32 , MacroAssembler::VELEM_SIZE_8);
__ veor(D20, D4, D18, quad);
__ vst1(D20, Address(R5, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vld1(D6, Address(R0, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vrev(D6, D6, quad, 32 , MacroAssembler::VELEM_SIZE_8);
__ veor(D20, D6, D18, quad);
__ vst1(D20, Address(R5, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vld1(D8, Address(R0, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vrev(D8, D8, quad, 32 , MacroAssembler::VELEM_SIZE_8);
__ veor(D20, D8, D18, quad);
__ vst1(D20, Address(R5, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vld1(D10, Address(R0, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vrev(D10, D10, quad, 32 , MacroAssembler::VELEM_SIZE_8);
__ veor(D20, D10, D18, quad);
__ vst1(D20, Address(R5, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vld1(D12, Address(R0, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vrev(D12, D12, quad, 32 , MacroAssembler::VELEM_SIZE_8);
__ veor(D20, D12, D18, quad);
__ vst1(D20, Address(R5, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vld1(D14, Address(R0, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vrev(D14, D14, quad, 32 , MacroAssembler::VELEM_SIZE_8);
__ veor(D20, D14, D18, quad);
__ vst1(D20, Address(R5, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
// Local frame map:
// sp+20 - output buffer pointer
// sp+28 - key pointer
// sp+32 - original source
// sp+36 - block counter
// preserve output buffer pointer
Address block_current_output_buffer(SP, 20 );
__ str(R1, block_current_output_buffer);
// individual rounds in block processing are executed sequentially .
Label block_start;
// record end of the output buffer
__ add(R0, R1, 128 );
__ str(R0, Address(SP, 12 ));
__ bind(block_start);
// load transporistion box reference (T5)
// location of the reference (6th incoming argument, second slot on the stack):
// 10 scalar registers on stack
// 8 double-precision FP registers
// 40 bytes frame size for local storage
// 4 bytes offset to the original arguments list
__ ldr(R0, Address(SP, 40 +64 +40 +4 ));
__ add(R0, R0, arrayOopDesc::base_offset_in_bytes(T_INT));
// load rounds key and compensate for the first and last rounds
__ ldr(LR, rounds_key);
__ add(LR, LR, 32 );
// load block data out buffer
__ ldr(R2, block_current_output_buffer);
__ ldmia(R2, RegisterSet(R5, R8));
Label round;
__ bind(round);
// Utilize a Transposition Box lookup along with subsequent shift and EOR with a round key.
// instructions ordering is rearranged to minimize ReadAferWrite dependency. Not that important on A15 target
// with register renaming but performs ~10% better on A9.
__ mov(R12, AsmOperand(R5, lsr, 24 ));
__ ubfx(R4, R8, 16 , 8 );
__ ldr (R1, Address(R0, R12, lsl, 2 ));
__ ldr(R2, Address(R0, R4, lsl, 2 ));
__ ubfx(R3, R7, 8 , 8 );
__ eor(R1, R1, AsmOperand(R2, ror, 8 ));
__ uxtb(R4, R6);
__ ldr(R3, Address(R0, R3, lsl, 2 ));
__ ldr(R4, Address(R0, R4, lsl, 2 ));
__ ldr(R12, Address(LR, 4 , post_indexed));
__ eor(R1, R1, AsmOperand(R3, ror, 16 ));
__ eor(R12, R12, AsmOperand(R4, ror, 24 ));
__ eor(R10, R1, R12);
__ mov(R12, AsmOperand(R6, lsr, 24 ));
__ ubfx(R4, R5, 16 , 8 );
__ ldr (R1, Address(R0, R12, lsl, 2 ));
__ ldr(R2, Address(R0, R4, lsl, 2 ));
__ ubfx(R3, R8, 8 , 8 );
__ eor(R1, R1, AsmOperand(R2, ror, 8 ));
__ uxtb(R4, R7);
__ ldr(R3, Address(R0, R3, lsl, 2 ));
__ ldr(R4, Address(R0, R4, lsl, 2 ));
__ ldr(R12, Address(LR, 4 , post_indexed));
__ eor(R1, R1, AsmOperand(R3, ror, 16 ));
__ eor(R12, R12, AsmOperand(R4, ror, 24 ));
__ eor(R11, R1, R12);
__ mov(R12, AsmOperand(R7, lsr, 24 ));
__ ubfx(R4, R6, 16 , 8 );
__ ldr (R1, Address(R0, R12, lsl, 2 ));
__ ldr(R2, Address(R0, R4, lsl, 2 ));
__ ubfx(R3, R5, 8 , 8 );
__ eor(R1, R1, AsmOperand(R2, ror, 8 ));
__ uxtb(R4, R8);
__ ldr(R3, Address(R0, R3, lsl, 2 ));
__ ldr(R4, Address(R0, R4, lsl, 2 ));
__ ldr(R12, Address(LR, 4 , post_indexed));
__ eor(R1, R1, AsmOperand(R3, ror, 16 ));
__ eor(R12, R12, AsmOperand(R4, ror, 24 ));
__ eor(R3, R1, R12);
__ str(R3, Address(SP, 0 ));
__ mov(R12, AsmOperand(R8, lsr, 24 ));
__ ubfx(R4, R7, 16 , 8 );
__ ldr (R1, Address(R0, R12, lsl, 2 ));
__ ldr(R2, Address(R0, R4, lsl, 2 ));
__ ubfx(R3, R6, 8 , 8 );
__ eor(R1, R1, AsmOperand(R2, ror, 8 ));
__ uxtb(R4, R5);
__ ldr(R3, Address(R0, R3, lsl, 2 ));
__ ldr(R4, Address(R0, R4, lsl, 2 ));
__ ldr(R12, Address(LR, 4 , post_indexed));
__ eor(R1, R1, AsmOperand(R3, ror, 16 ));
__ eor(R12, R12, AsmOperand(R4, ror, 24 ));
__ eor(R8, R1, R12);
// see if we reached the key array end
__ cmp(R9, LR);
// load processed data
__ mov(R5, R10);
__ mov(R6, R11);
__ ldr(R7, Address(SP, 0 ));
__ b(round, gt);
// last round is special
// this round could be implemented through vtbl instruction in NEON. However vtbl is limited to a 32-byte wide table (4 vectors),
// thus it requires 8 lookup rounds to cover 256-byte wide Si table. On the other hand scalar lookup is independent of the
// lookup table size and thus proves to be faster.
__ ldr(LR, block_current_output_buffer);
// cipher counter
__ ldr(R11, Address(SP, 12 ));
__ mov_slow(R10, (int )SInvBox);
__ ldrb(R0, Address(R10, R5, lsr, 24 ));
__ ubfx(R12, R8, 16 , 8 );
__ ldrb (R1, Address(R10, R12));
__ orr(R0, R1, AsmOperand(R0, lsl, 8 ));
__ ubfx(R12, R7, 8 , 8 );
__ ldrb(R2, Address(R10, R12));
__ orr(R0, R2, AsmOperand(R0, lsl, 8 ));
__ uxtb(R12, R6);
__ ldrb(R3, Address(R10, R12));
__ orr(R0, R3, AsmOperand(R0, lsl, 8 ));
__ str(R0, Address(LR, 4 , post_indexed));
__ ldrb(R0, Address(R10, R6, lsr, 24 ));
__ ubfx(R12, R5, 16 , 8 );
__ ldrb (R1, Address(R10, R12));
__ orr(R0, R1, AsmOperand(R0, lsl, 8 ));
__ ubfx(R12, R8, 8 , 8 );
__ ldrb(R2, Address(R10, R12));
__ orr(R0, R2, AsmOperand(R0, lsl, 8 ));
__ uxtb(R12, R7);
__ ldrb(R3, Address(R10, R12));
__ orr(R0, R3, AsmOperand(R0, lsl, 8 ));
__ str(R0, Address(LR, 4 , post_indexed));
__ ldrb(R0, Address(R10, R7, lsr, 24 ));
__ ubfx(R12, R6, 16 , 8 );
__ ldrb (R1, Address(R10, R12));
__ orr(R0, R1, AsmOperand(R0, lsl, 8 ));
__ ubfx(R12, R5, 8 , 8 );
__ ldrb(R2, Address(R10, R12));
__ orr(R0, R2, AsmOperand(R0, lsl, 8 ));
__ uxtb(R12, R8);
__ ldrb(R3, Address(R10, R12));
__ orr(R0, R3, AsmOperand(R0, lsl, 8 ));
__ str(R0, Address(LR, 4 , post_indexed));
__ ldrb(R0, Address(R10, R8, lsr, 24 ));
__ ubfx(R12, R7, 16 , 8 );
__ ldrb (R1, Address(R10, R12));
__ orr(R0, R1, AsmOperand(R0, lsl, 8 ));
__ ubfx(R12, R6, 8 , 8 );
__ ldrb(R2, Address(R10, R12));
__ orr(R0, R2, AsmOperand(R0, lsl, 8 ));
__ uxtb(R12, R5);
__ ldrb(R3, Address(R10, R12));
__ orr(R0, R3, AsmOperand(R0, lsl, 8 ));
__ str(R0, Address(LR, 4 , post_indexed));
// preserve current scratch buffer pointer
__ cmp(R11, LR);
__ str(LR, block_current_output_buffer);
// go to the next block processing
__ b(block_start, ne);
// Perform last round AddRoundKey state on all 8 blocks
// load key pointer (remember that [sp+24] points to a byte #32 at the key array)
// last round is processed with the key[0 ..3]
__ ldr(LR, rounds_key);
// retireve original output buffer pointer
__ ldr(R1, block_current_output_buffer);
__ sub(R1, R1, 128 );
__ mov(R5, R1);
// retrieve original cipher (source) pointer
__ ldr(R0, original_src);
// retrieve IV (second argument on stack)
__ ldr(R6, iv);
__ vld1(D20, R6, MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vrev(D20, D20, quad, 32 , MacroAssembler::VELEM_SIZE_8);
// perform last AddRoundKey and IV addition
__ vld1(D18, Address(LR, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vld1(D22, Address(R1, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ veor(D22, D22, D18, quad);
__ veor(D22, D22, D20, quad);
__ vrev(D22, D22, quad, 32 , MacroAssembler::VELEM_SIZE_8);
__ vst1(D22, Address(R5, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vld1(D22, Address(R1, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ veor(D22, D22, D18, quad);
__ veor(D22, D22, D0, quad);
__ vrev(D22, D22, quad, 32 , MacroAssembler::VELEM_SIZE_8);
__ vst1(D22, Address(R5, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vld1(D22, Address(R1, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ veor(D22, D22, D18, quad);
__ veor(D22, D22, D2, quad);
__ vrev(D22, D22, quad, 32 , MacroAssembler::VELEM_SIZE_8);
__ vst1(D22, Address(R5, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vld1(D22, Address(R1, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ veor(D22, D22, D18, quad);
__ veor(D22, D22, D4, quad);
__ vrev(D22, D22, quad, 32 , MacroAssembler::VELEM_SIZE_8);
__ vst1(D22, Address(R5, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vld1(D22, Address(R1, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ veor(D22, D22, D18, quad);
__ veor(D22, D22, D6, quad);
__ vrev(D22, D22, quad, 32 , MacroAssembler::VELEM_SIZE_8);
__ vst1(D22, Address(R5, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vld1(D22, Address(R1, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ veor(D22, D22, D18, quad);
__ veor(D22, D22, D8, quad);
__ vrev(D22, D22, quad, 32 , MacroAssembler::VELEM_SIZE_8);
__ vst1(D22, Address(R5, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vld1(D22, Address(R1, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ veor(D22, D22, D18, quad);
__ veor(D22, D22, D10, quad);
__ vrev(D22, D22, quad, 32 , MacroAssembler::VELEM_SIZE_8);
__ vst1(D22, Address(R5, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ vld1(D22, Address(R1, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
__ veor(D22, D22, D18, quad);
__ veor(D22, D22, D12, quad);
__ vrev(D22, D22, quad, 32 , MacroAssembler::VELEM_SIZE_8);
__ vst1(D22, Address(R5, 0 , post_indexed), MacroAssembler::VELEM_SIZE_8, MacroAssembler::VLD1_TYPE_2_REGS);
// check if we're done
__ ldr(R4, output_buffer_end);
__ cmp(R4, R1);
__ add(R0, R0, 128 -16 );
__ str(R0, iv);
__ add(R0, R0, 16 );
__ b(decrypt_8_blocks, ne);
__ add(SP, SP, 40 );
__ fpop(FloatRegisterSet(D8, 8 ));
}
__ bind(cbc_done);
__ pop(RegisterSet(R4, R12) | LR);
__ ldr(R0, Address(SP));
__ bx(LR);
return start;
}
#endif // USE_CRYPTO
Messung V0.5 in Prozent C=97 H=99 G=97
¤ Dauer der Verarbeitung: 0.14 Sekunden
(vorverarbeitet am 2026-06-10)
¤
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