// SPDX-License-Identifier: GPL-2.0 /* * Mediatek ALSA SoC AFE platform driver for 8195 * * Copyright (c) 2021 MediaTek Inc. * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> * Trevor Wu <trevor.wu@mediatek.com> #include <linux/delay.h>#include <linux/dma-mapping.h>#include <linux/module.h>#include <linux/mfd/syscon.h>#include <linux/of.h>#include <linux/of_address.h>#include <linux/of_platform.h>#include <linux/of_reserved_mem.h>#include <linux/pm_runtime.h>#include <linux/reset.h>#include "mt8195-afe-common.h" #include "mt8195-afe-clk.h" #include "mt8195-reg.h" #include "../common/mtk-afe-platform-driver.h" #include "../common/mtk-afe-fe-dai.h" #define MT8195_MEMIF_BUFFER_BYTES_ALIGN (0 x40)#define MT8195_MEMIF_DL7_MAX_PERIOD_SIZE (0 x3fff)struct mtk_dai_memif_priv {unsigned int asys_timing_sel;static const struct snd_pcm_hardware mt8195_afe_hardware = {64 ,256 * 1024 ,2 ,256 ,256 * 2 * 1024 ,struct mt8195_afe_rate {unsigned int rate;unsigned int reg_value;static const struct mt8195_afe_rate mt8195_afe_rates[] = {8000 , .reg_value = 0 , },12000 , .reg_value = 1 , },16000 , .reg_value = 2 , },24000 , .reg_value = 3 , },32000 , .reg_value = 4 , },48000 , .reg_value = 5 , },96000 , .reg_value = 6 , },192000 , .reg_value = 7 , },384000 , .reg_value = 8 , },7350 , .reg_value = 16 , },11025 , .reg_value = 17 , },14700 , .reg_value = 18 , },22050 , .reg_value = 19 , },29400 , .reg_value = 20 , },44100 , .reg_value = 21 , },88200 , .reg_value = 22 , },176400 , .reg_value = 23 , },352800 , .reg_value = 24 , },int mt8195_afe_fs_timing(unsigned int rate)int i;for (i = 0 ; i < ARRAY_SIZE(mt8195_afe_rates); i++)if (mt8195_afe_rates[i].rate == rate)return mt8195_afe_rates[i].reg_value;return -EINVAL;static int mt8195_memif_fs(struct snd_pcm_substream *substream,unsigned int rate)struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);struct snd_soc_component *component =struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);int id = snd_soc_rtd_to_cpu(rtd, 0 )->id;struct mtk_base_afe_memif *memif = &afe->memif[id];int fs = mt8195_afe_fs_timing(rate);switch (memif->data->id) {case MT8195_AFE_MEMIF_DL10:break ;case MT8195_AFE_MEMIF_UL8:break ;case MT8195_AFE_MEMIF_UL3:break ;default :break ;return fs;static int mt8195_irq_fs(struct snd_pcm_substream *substream,unsigned int rate)int fs = mt8195_memif_fs(substream, rate);switch (fs) {case MT8195_ETDM_IN1_NX_EN:break ;case MT8195_ETDM_IN2_NX_EN:break ;default :break ;return fs;enum {struct mt8195_afe_channel_merge {int id;int reg;unsigned int sel_shift;unsigned int sel_maskbit;unsigned int sel_default;unsigned int ch_num_shift;unsigned int ch_num_maskbit;unsigned int en_shift;unsigned int en_maskbit;unsigned int update_cnt_shift;unsigned int update_cnt_maskbit;unsigned int update_cnt_default;static const struct mt8195_afe_channel_merge30 ,0 x1,1 ,2 ,0 x3f,0 ,0 x1,16 ,0 x1fff,0 x3,30 ,0 x1,1 ,2 ,0 x1f,0 ,0 x1,16 ,0 x1fff,0 x3,30 ,0 x1,1 ,2 ,0 x1f,0 ,0 x1,16 ,0 x1fff,0 x3,static int mt8195_afe_memif_is_ul(int id)if (id >= MT8195_AFE_MEMIF_UL_START && id < MT8195_AFE_MEMIF_END)return 1 ;else return 0 ;static const struct mt8195_afe_channel_merge*struct snd_soc_dai *dai)struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);int id = -EINVAL;if (mt8195_afe_memif_is_ul(dai->id) == 0 )return NULL;switch (dai->id) {case MT8195_AFE_MEMIF_UL9:break ;case MT8195_AFE_MEMIF_UL2:break ;case MT8195_AFE_MEMIF_UL10:break ;default :break ;if (id < 0 ) {"%s, memif %d cannot find CM!\n" ,return NULL;return &mt8195_afe_cm[id];static int mt8195_afe_config_cm(struct mtk_base_afe *afe,const struct mt8195_afe_channel_merge *cm,unsigned int channels)if (!cm)return -EINVAL;1 ) << cm->ch_num_shift);return 0 ;static int mt8195_afe_enable_cm(struct mtk_base_afe *afe,const struct mt8195_afe_channel_merge *cm,bool enable)if (!cm)return -EINVAL;return 0 ;static int struct snd_pcm_substream *substream,struct snd_soc_dai *dai,int enable)struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);struct mt8195_afe_private *afe_priv = afe->platform_priv;int id = snd_soc_rtd_to_cpu(rtd, 0 )->id;int clk_id;if (id != MT8195_AFE_MEMIF_DL8 && id != MT8195_AFE_MEMIF_DL10)return 0 ;if (enable) {else {return 0 ;static int struct snd_pcm_substream *substream,struct snd_soc_dai *dai,int enable)struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);struct mt8195_afe_private *afe_priv = afe->platform_priv;int id = snd_soc_rtd_to_cpu(rtd, 0 )->id;int clk_id;if (id != MT8195_AFE_MEMIF_DL8 && id != MT8195_AFE_MEMIF_DL10)return 0 ;if (enable) {/* DL8_DL10_MEM */ 1 );/* DL8_DL10_AGENT */ else {/* DL8_DL10_AGENT */ /* DL8_DL10_MEM */ return 0 ;static int mt8195_afe_fe_startup(struct snd_pcm_substream *substream,struct snd_soc_dai *dai)struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);struct snd_pcm_runtime *runtime = substream->runtime;struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);int id = snd_soc_rtd_to_cpu(rtd, 0 )->id;int ret = 0 ;1 );0 ,if (id != MT8195_AFE_MEMIF_DL7)goto out;1 ,if (ret < 0 )"hw_constraint_minmax failed\n" );return ret;static void mt8195_afe_fe_shutdown(struct snd_pcm_substream *substream,struct snd_soc_dai *dai)0 );static int mt8195_afe_fe_hw_params(struct snd_pcm_substream *substream,struct snd_pcm_hw_params *params,struct snd_soc_dai *dai)struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);int id = snd_soc_rtd_to_cpu(rtd, 0 )->id;struct mtk_base_afe_memif *memif = &afe->memif[id];const struct mtk_base_memif_data *data = memif->data;const struct mt8195_afe_channel_merge *cm = mt8195_afe_found_cm(dai);unsigned int ch_num = params_channels(params);if (data->ch_num_reg >= 0 ) {return mtk_afe_fe_hw_params(substream, params, dai);static int mt8195_afe_fe_hw_free(struct snd_pcm_substream *substream,struct snd_soc_dai *dai)return mtk_afe_fe_hw_free(substream, dai);static int mt8195_afe_fe_prepare(struct snd_pcm_substream *substream,struct snd_soc_dai *dai)return mtk_afe_fe_prepare(substream, dai);static int mt8195_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd,struct snd_soc_dai *dai)int ret = 0 ;struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);const struct mt8195_afe_channel_merge *cm = mt8195_afe_found_cm(dai);switch (cmd) {case SNDRV_PCM_TRIGGER_START:case SNDRV_PCM_TRIGGER_RESUME:true );break ;case SNDRV_PCM_TRIGGER_STOP:case SNDRV_PCM_TRIGGER_SUSPEND:false );break ;default :break ;switch (cmd) {case SNDRV_PCM_TRIGGER_START:case SNDRV_PCM_TRIGGER_RESUME:1 );break ;case SNDRV_PCM_TRIGGER_STOP:case SNDRV_PCM_TRIGGER_SUSPEND:0 );break ;default :break ;return ret;static int mt8195_afe_fe_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)return 0 ;static const struct snd_soc_dai_ops mt8195_afe_fe_dai_ops = {#define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\#define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\static struct snd_soc_dai_driver mt8195_memif_dai_driver[] = {/* FE DAIs: memory intefaces to CPU */ "DL2" ,"DL2" ,1 ,2 ,"DL3" ,"DL3" ,1 ,2 ,"DL6" ,"DL6" ,1 ,2 ,"DL7" ,"DL7" ,1 ,2 ,"DL8" ,"DL8" ,1 ,24 ,"DL10" ,"DL10" ,1 ,8 ,"DL11" ,"DL11" ,1 ,48 ,"UL1" ,"UL1" ,1 ,8 ,"UL2" ,"UL2" ,1 ,8 ,"UL3" ,"UL3" ,1 ,16 ,"UL4" ,"UL4" ,1 ,2 ,"UL5" ,"UL5" ,1 ,2 ,"UL6" ,"UL6" ,1 ,8 ,"UL8" ,"UL8" ,1 ,24 ,"UL9" ,"UL9" ,1 ,32 ,"UL10" ,"UL10" ,1 ,4 ,static const struct snd_kcontrol_new o002_mix[] = {"I000 Switch" , AFE_CONN2, 0 , 1 , 0 ),"I012 Switch" , AFE_CONN2, 12 , 1 , 0 ),"I020 Switch" , AFE_CONN2, 20 , 1 , 0 ),"I022 Switch" , AFE_CONN2, 22 , 1 , 0 ),"I070 Switch" , AFE_CONN2_2, 6 , 1 , 0 ),"I072 Switch" , AFE_CONN2_2, 8 , 1 , 0 ),"I168 Switch" , AFE_CONN2_5, 8 , 1 , 0 ),static const struct snd_kcontrol_new o003_mix[] = {"I001 Switch" , AFE_CONN3, 1 , 1 , 0 ),"I013 Switch" , AFE_CONN3, 13 , 1 , 0 ),"I021 Switch" , AFE_CONN3, 21 , 1 , 0 ),"I023 Switch" , AFE_CONN3, 23 , 1 , 0 ),"I071 Switch" , AFE_CONN3_2, 7 , 1 , 0 ),"I073 Switch" , AFE_CONN3_2, 9 , 1 , 0 ),"I169 Switch" , AFE_CONN3_5, 9 , 1 , 0 ),static const struct snd_kcontrol_new o004_mix[] = {"I000 Switch" , AFE_CONN4, 0 , 1 , 0 ),"I014 Switch" , AFE_CONN4, 14 , 1 , 0 ),"I024 Switch" , AFE_CONN4, 24 , 1 , 0 ),"I074 Switch" , AFE_CONN4_2, 10 , 1 , 0 ),"I170 Switch" , AFE_CONN4_5, 10 , 1 , 0 ),static const struct snd_kcontrol_new o005_mix[] = {"I001 Switch" , AFE_CONN5, 1 , 1 , 0 ),"I015 Switch" , AFE_CONN5, 15 , 1 , 0 ),"I025 Switch" , AFE_CONN5, 25 , 1 , 0 ),"I075 Switch" , AFE_CONN5_2, 11 , 1 , 0 ),"I171 Switch" , AFE_CONN5_5, 11 , 1 , 0 ),static const struct snd_kcontrol_new o006_mix[] = {"I000 Switch" , AFE_CONN6, 0 , 1 , 0 ),"I016 Switch" , AFE_CONN6, 16 , 1 , 0 ),"I026 Switch" , AFE_CONN6, 26 , 1 , 0 ),"I076 Switch" , AFE_CONN6_2, 12 , 1 , 0 ),static const struct snd_kcontrol_new o007_mix[] = {"I001 Switch" , AFE_CONN7, 1 , 1 , 0 ),"I017 Switch" , AFE_CONN7, 17 , 1 , 0 ),"I027 Switch" , AFE_CONN7, 27 , 1 , 0 ),"I077 Switch" , AFE_CONN7_2, 13 , 1 , 0 ),static const struct snd_kcontrol_new o008_mix[] = {"I018 Switch" , AFE_CONN8, 18 , 1 , 0 ),"I028 Switch" , AFE_CONN8, 28 , 1 , 0 ),"I078 Switch" , AFE_CONN8_2, 14 , 1 , 0 ),static const struct snd_kcontrol_new o009_mix[] = {"I019 Switch" , AFE_CONN9, 19 , 1 , 0 ),"I029 Switch" , AFE_CONN9, 29 , 1 , 0 ),"I079 Switch" , AFE_CONN9_2, 15 , 1 , 0 ),static const struct snd_kcontrol_new o010_mix[] = {"I022 Switch" , AFE_CONN10, 22 , 1 , 0 ),"I030 Switch" , AFE_CONN10, 30 , 1 , 0 ),"I046 Switch" , AFE_CONN10_1, 14 , 1 , 0 ),"I072 Switch" , AFE_CONN10_2, 8 , 1 , 0 ),static const struct snd_kcontrol_new o011_mix[] = {"I023 Switch" , AFE_CONN11, 23 , 1 , 0 ),"I031 Switch" , AFE_CONN11, 31 , 1 , 0 ),"I047 Switch" , AFE_CONN11_1, 15 , 1 , 0 ),"I073 Switch" , AFE_CONN11_2, 9 , 1 , 0 ),static const struct snd_kcontrol_new o012_mix[] = {"I024 Switch" , AFE_CONN12, 24 , 1 , 0 ),"I032 Switch" , AFE_CONN12_1, 0 , 1 , 0 ),"I048 Switch" , AFE_CONN12_1, 16 , 1 , 0 ),"I074 Switch" , AFE_CONN12_2, 10 , 1 , 0 ),static const struct snd_kcontrol_new o013_mix[] = {"I025 Switch" , AFE_CONN13, 25 , 1 , 0 ),"I033 Switch" , AFE_CONN13_1, 1 , 1 , 0 ),"I049 Switch" , AFE_CONN13_1, 17 , 1 , 0 ),"I075 Switch" , AFE_CONN13_2, 11 , 1 , 0 ),static const struct snd_kcontrol_new o014_mix[] = {"I026 Switch" , AFE_CONN14, 26 , 1 , 0 ),"I034 Switch" , AFE_CONN14_1, 2 , 1 , 0 ),"I050 Switch" , AFE_CONN14_1, 18 , 1 , 0 ),"I076 Switch" , AFE_CONN14_2, 12 , 1 , 0 ),static const struct snd_kcontrol_new o015_mix[] = {"I027 Switch" , AFE_CONN15, 27 , 1 , 0 ),"I035 Switch" , AFE_CONN15_1, 3 , 1 , 0 ),"I051 Switch" , AFE_CONN15_1, 19 , 1 , 0 ),"I077 Switch" , AFE_CONN15_2, 13 , 1 , 0 ),static const struct snd_kcontrol_new o016_mix[] = {"I028 Switch" , AFE_CONN16, 28 , 1 , 0 ),"I036 Switch" , AFE_CONN16_1, 4 , 1 , 0 ),"I052 Switch" , AFE_CONN16_1, 20 , 1 , 0 ),"I078 Switch" , AFE_CONN16_2, 14 , 1 , 0 ),static const struct snd_kcontrol_new o017_mix[] = {"I029 Switch" , AFE_CONN17, 29 , 1 , 0 ),"I037 Switch" , AFE_CONN17_1, 5 , 1 , 0 ),"I053 Switch" , AFE_CONN17_1, 21 , 1 , 0 ),"I079 Switch" , AFE_CONN17_2, 15 , 1 , 0 ),static const struct snd_kcontrol_new o018_mix[] = {"I038 Switch" , AFE_CONN18_1, 6 , 1 , 0 ),"I080 Switch" , AFE_CONN18_2, 16 , 1 , 0 ),static const struct snd_kcontrol_new o019_mix[] = {"I039 Switch" , AFE_CONN19_1, 7 , 1 , 0 ),"I081 Switch" , AFE_CONN19_2, 17 , 1 , 0 ),static const struct snd_kcontrol_new o020_mix[] = {"I040 Switch" , AFE_CONN20_1, 8 , 1 , 0 ),"I082 Switch" , AFE_CONN20_2, 18 , 1 , 0 ),static const struct snd_kcontrol_new o021_mix[] = {"I041 Switch" , AFE_CONN21_1, 9 , 1 , 0 ),"I083 Switch" , AFE_CONN21_2, 19 , 1 , 0 ),static const struct snd_kcontrol_new o022_mix[] = {"I042 Switch" , AFE_CONN22_1, 10 , 1 , 0 ),"I084 Switch" , AFE_CONN22_2, 20 , 1 , 0 ),static const struct snd_kcontrol_new o023_mix[] = {"I043 Switch" , AFE_CONN23_1, 11 , 1 , 0 ),"I085 Switch" , AFE_CONN23_2, 21 , 1 , 0 ),static const struct snd_kcontrol_new o024_mix[] = {"I044 Switch" , AFE_CONN24_1, 12 , 1 , 0 ),"I086 Switch" , AFE_CONN24_2, 22 , 1 , 0 ),static const struct snd_kcontrol_new o025_mix[] = {"I045 Switch" , AFE_CONN25_1, 13 , 1 , 0 ),"I087 Switch" , AFE_CONN25_2, 23 , 1 , 0 ),static const struct snd_kcontrol_new o026_mix[] = {"I046 Switch" , AFE_CONN26_1, 14 , 1 , 0 ),"I088 Switch" , AFE_CONN26_2, 24 , 1 , 0 ),static const struct snd_kcontrol_new o027_mix[] = {"I047 Switch" , AFE_CONN27_1, 15 , 1 , 0 ),"I089 Switch" , AFE_CONN27_2, 25 , 1 , 0 ),static const struct snd_kcontrol_new o028_mix[] = {"I048 Switch" , AFE_CONN28_1, 16 , 1 , 0 ),"I090 Switch" , AFE_CONN28_2, 26 , 1 , 0 ),static const struct snd_kcontrol_new o029_mix[] = {"I049 Switch" , AFE_CONN29_1, 17 , 1 , 0 ),"I091 Switch" , AFE_CONN29_2, 27 , 1 , 0 ),static const struct snd_kcontrol_new o030_mix[] = {"I050 Switch" , AFE_CONN30_1, 18 , 1 , 0 ),"I092 Switch" , AFE_CONN30_2, 28 , 1 , 0 ),static const struct snd_kcontrol_new o031_mix[] = {"I051 Switch" , AFE_CONN31_1, 19 , 1 , 0 ),"I093 Switch" , AFE_CONN31_2, 29 , 1 , 0 ),static const struct snd_kcontrol_new o032_mix[] = {"I052 Switch" , AFE_CONN32_1, 20 , 1 , 0 ),"I094 Switch" , AFE_CONN32_2, 30 , 1 , 0 ),static const struct snd_kcontrol_new o033_mix[] = {"I053 Switch" , AFE_CONN33_1, 21 , 1 , 0 ),"I095 Switch" , AFE_CONN33_2, 31 , 1 , 0 ),static const struct snd_kcontrol_new o034_mix[] = {"I000 Switch" , AFE_CONN34, 0 , 1 , 0 ),"I002 Switch" , AFE_CONN34, 2 , 1 , 0 ),"I012 Switch" , AFE_CONN34, 12 , 1 , 0 ),"I020 Switch" , AFE_CONN34, 20 , 1 , 0 ),"I070 Switch" , AFE_CONN34_2, 6 , 1 , 0 ),"I072 Switch" , AFE_CONN34_2, 8 , 1 , 0 ),"I168 Switch" , AFE_CONN34_5, 8 , 1 , 0 ),"I170 Switch" , AFE_CONN34_5, 10 , 1 , 0 ),static const struct snd_kcontrol_new o035_mix[] = {"I001 Switch" , AFE_CONN35, 1 , 1 , 0 ),"I003 Switch" , AFE_CONN35, 3 , 1 , 0 ),"I013 Switch" , AFE_CONN35, 13 , 1 , 0 ),"I021 Switch" , AFE_CONN35, 21 , 1 , 0 ),"I071 Switch" , AFE_CONN35_2, 7 , 1 , 0 ),"I073 Switch" , AFE_CONN35_2, 9 , 1 , 0 ),"I137 Switch" , AFE_CONN35_4, 9 , 1 , 0 ),"I139 Switch" , AFE_CONN35_4, 11 , 1 , 0 ),"I168 Switch" , AFE_CONN35_5, 8 , 1 , 0 ),"I169 Switch" , AFE_CONN35_5, 9 , 1 , 0 ),"I170 Switch" , AFE_CONN35_5, 10 , 1 , 0 ),"I171 Switch" , AFE_CONN35_5, 11 , 1 , 0 ),static const struct snd_kcontrol_new o036_mix[] = {"I000 Switch" , AFE_CONN36, 0 , 1 , 0 ),"I012 Switch" , AFE_CONN36, 12 , 1 , 0 ),"I020 Switch" , AFE_CONN36, 20 , 1 , 0 ),"I070 Switch" , AFE_CONN36_2, 6 , 1 , 0 ),"I168 Switch" , AFE_CONN36_5, 8 , 1 , 0 ),static const struct snd_kcontrol_new o037_mix[] = {"I001 Switch" , AFE_CONN37, 1 , 1 , 0 ),"I013 Switch" , AFE_CONN37, 13 , 1 , 0 ),"I021 Switch" , AFE_CONN37, 21 , 1 , 0 ),"I071 Switch" , AFE_CONN37_2, 7 , 1 , 0 ),"I169 Switch" , AFE_CONN37_5, 9 , 1 , 0 ),static const struct snd_kcontrol_new o038_mix[] = {"I022 Switch" , AFE_CONN38, 22 , 1 , 0 ),static const struct snd_kcontrol_new o039_mix[] = {"I023 Switch" , AFE_CONN39, 23 , 1 , 0 ),static const struct snd_kcontrol_new o040_mix[] = {"I002 Switch" , AFE_CONN40, 2 , 1 , 0 ),"I012 Switch" , AFE_CONN40, 12 , 1 , 0 ),"I022 Switch" , AFE_CONN40, 22 , 1 , 0 ),"I168 Switch" , AFE_CONN40_5, 8 , 1 , 0 ),static const struct snd_kcontrol_new o041_mix[] = {"I003 Switch" , AFE_CONN41, 3 , 1 , 0 ),"I013 Switch" , AFE_CONN41, 13 , 1 , 0 ),"I023 Switch" , AFE_CONN41, 23 , 1 , 0 ),"I169 Switch" , AFE_CONN41_5, 9 , 1 , 0 ),static const struct snd_kcontrol_new o042_mix[] = {"I014 Switch" , AFE_CONN42, 14 , 1 , 0 ),"I024 Switch" , AFE_CONN42, 24 , 1 , 0 ),"I170 Switch" , AFE_CONN42_5, 10 , 1 , 0 ),static const struct snd_kcontrol_new o043_mix[] = {"I015 Switch" , AFE_CONN43, 15 , 1 , 0 ),"I025 Switch" , AFE_CONN43, 25 , 1 , 0 ),"I171 Switch" , AFE_CONN43_5, 11 , 1 , 0 ),static const struct snd_kcontrol_new o044_mix[] = {"I016 Switch" , AFE_CONN44, 16 , 1 , 0 ),"I026 Switch" , AFE_CONN44, 26 , 1 , 0 ),static const struct snd_kcontrol_new o045_mix[] = {"I017 Switch" , AFE_CONN45, 17 , 1 , 0 ),"I027 Switch" , AFE_CONN45, 27 , 1 , 0 ),static const struct snd_kcontrol_new o046_mix[] = {"I018 Switch" , AFE_CONN46, 18 , 1 , 0 ),"I028 Switch" , AFE_CONN46, 28 , 1 , 0 ),static const struct snd_kcontrol_new o047_mix[] = {"I019 Switch" , AFE_CONN47, 19 , 1 , 0 ),"I029 Switch" , AFE_CONN47, 29 , 1 , 0 ),static const struct snd_kcontrol_new o182_mix[] = {"I024 Switch" , AFE_CONN182, 24 , 1 , 0 ),static const struct snd_kcontrol_new o183_mix[] = {"I025 Switch" , AFE_CONN183, 25 , 1 , 0 ),static const char * const dl8_dl11_data_sel_mux_text[] = {"dl8" , "dl11" ,static SOC_ENUM_SINGLE_DECL(dl8_dl11_data_sel_mux_enum,0 , dl8_dl11_data_sel_mux_text);static const struct snd_kcontrol_new dl8_dl11_data_sel_mux ="DL8_DL11 Sink" , dl8_dl11_data_sel_mux_enum);static const struct snd_soc_dapm_widget mt8195_memif_widgets[] = {/* DL6 */ "I000" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I001" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),/* DL3 */ "I020" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I021" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),/* DL11 */ "I022" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I023" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I024" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I025" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I026" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I027" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I028" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I029" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I030" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I031" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I032" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I033" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I034" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I035" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I036" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I037" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I038" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I039" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I040" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I041" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I042" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I043" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I044" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I045" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),/* DL11/DL8 */ "I046" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I047" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I048" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I049" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I050" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I051" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I052" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I053" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I054" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I055" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I056" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I057" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I058" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I059" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I060" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I061" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I062" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I063" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I064" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I065" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I066" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I067" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I068" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I069" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),/* DL2 */ "I070" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"I071" , SND_SOC_NOPM, 0 , 0 , NULL, 0 ),"DL8_DL11 Mux" ,0 , 0 , &dl8_dl11_data_sel_mux),/* UL9 */ "O002" , SND_SOC_NOPM, 0 , 0 ,"O003" , SND_SOC_NOPM, 0 , 0 ,"O004" , SND_SOC_NOPM, 0 , 0 ,"O005" , SND_SOC_NOPM, 0 , 0 ,"O006" , SND_SOC_NOPM, 0 , 0 ,"O007" , SND_SOC_NOPM, 0 , 0 ,"O008" , SND_SOC_NOPM, 0 , 0 ,"O009" , SND_SOC_NOPM, 0 , 0 ,"O010" , SND_SOC_NOPM, 0 , 0 ,"O011" , SND_SOC_NOPM, 0 , 0 ,"O012" , SND_SOC_NOPM, 0 , 0 ,"O013" , SND_SOC_NOPM, 0 , 0 ,"O014" , SND_SOC_NOPM, 0 , 0 ,"O015" , SND_SOC_NOPM, 0 , 0 ,"O016" , SND_SOC_NOPM, 0 , 0 ,"O017" , SND_SOC_NOPM, 0 , 0 ,"O018" , SND_SOC_NOPM, 0 , 0 ,"O019" , SND_SOC_NOPM, 0 , 0 ,"O020" , SND_SOC_NOPM, 0 , 0 ,"O021" , SND_SOC_NOPM, 0 , 0 ,"O022" , SND_SOC_NOPM, 0 , 0 ,"O023" , SND_SOC_NOPM, 0 , 0 ,"O024" , SND_SOC_NOPM, 0 , 0 ,"O025" , SND_SOC_NOPM, 0 , 0 ,"O026" , SND_SOC_NOPM, 0 , 0 ,"O027" , SND_SOC_NOPM, 0 , 0 ,"O028" , SND_SOC_NOPM, 0 , 0 ,"O029" , SND_SOC_NOPM, 0 , 0 ,"O030" , SND_SOC_NOPM, 0 , 0 ,"O031" , SND_SOC_NOPM, 0 , 0 ,"O032" , SND_SOC_NOPM, 0 , 0 ,"O033" , SND_SOC_NOPM, 0 , 0 ,/* UL4 */ "O034" , SND_SOC_NOPM, 0 , 0 ,"O035" , SND_SOC_NOPM, 0 , 0 ,/* UL5 */ "O036" , SND_SOC_NOPM, 0 , 0 ,"O037" , SND_SOC_NOPM, 0 , 0 ,/* UL10 */ "O038" , SND_SOC_NOPM, 0 , 0 ,"O039" , SND_SOC_NOPM, 0 , 0 ,"O182" , SND_SOC_NOPM, 0 , 0 ,"O183" , SND_SOC_NOPM, 0 , 0 ,/* UL2 */ "O040" , SND_SOC_NOPM, 0 , 0 ,"O041" , SND_SOC_NOPM, 0 , 0 ,"O042" , SND_SOC_NOPM, 0 , 0 ,"O043" , SND_SOC_NOPM, 0 , 0 ,"O044" , SND_SOC_NOPM, 0 , 0 ,"O045" , SND_SOC_NOPM, 0 , 0 ,"O046" , SND_SOC_NOPM, 0 , 0 ,"O047" , SND_SOC_NOPM, 0 , 0 ,static const struct snd_soc_dapm_route mt8195_memif_routes[] = {"I000" , NULL, "DL6" },"I001" , NULL, "DL6" },"I020" , NULL, "DL3" },"I021" , NULL, "DL3" },"I022" , NULL, "DL11" },"I023" , NULL, "DL11" },"I024" , NULL, "DL11" },"I025" , NULL, "DL11" },"I026" , NULL, "DL11" },"I027" , NULL, "DL11" },"I028" , NULL, "DL11" },"I029" , NULL, "DL11" },"I030" , NULL, "DL11" },"I031" , NULL, "DL11" },"I032" , NULL, "DL11" },"I033" , NULL, "DL11" },"I034" , NULL, "DL11" },"I035" , NULL, "DL11" },"I036" , NULL, "DL11" },"I037" , NULL, "DL11" },"I038" , NULL, "DL11" },"I039" , NULL, "DL11" },"I040" , NULL, "DL11" },"I041" , NULL, "DL11" },"I042" , NULL, "DL11" },"I043" , NULL, "DL11" },"I044" , NULL, "DL11" },"I045" , NULL, "DL11" },"DL8_DL11 Mux" , "dl8" , "DL8" },"DL8_DL11 Mux" , "dl11" , "DL11" },"I046" , NULL, "DL8_DL11 Mux" },"I047" , NULL, "DL8_DL11 Mux" },"I048" , NULL, "DL8_DL11 Mux" },"I049" , NULL, "DL8_DL11 Mux" },"I050" , NULL, "DL8_DL11 Mux" },"I051" , NULL, "DL8_DL11 Mux" },"I052" , NULL, "DL8_DL11 Mux" },"I053" , NULL, "DL8_DL11 Mux" },"I054" , NULL, "DL8_DL11 Mux" },"I055" , NULL, "DL8_DL11 Mux" },"I056" , NULL, "DL8_DL11 Mux" },"I057" , NULL, "DL8_DL11 Mux" },"I058" , NULL, "DL8_DL11 Mux" },"I059" , NULL, "DL8_DL11 Mux" },"I060" , NULL, "DL8_DL11 Mux" },"I061" , NULL, "DL8_DL11 Mux" },"I062" , NULL, "DL8_DL11 Mux" },"I063" , NULL, "DL8_DL11 Mux" },"I064" , NULL, "DL8_DL11 Mux" },"I065" , NULL, "DL8_DL11 Mux" },"I066" , NULL, "DL8_DL11 Mux" },"I067" , NULL, "DL8_DL11 Mux" },"I068" , NULL, "DL8_DL11 Mux" },"I069" , NULL, "DL8_DL11 Mux" },"I070" , NULL, "DL2" },"I071" , NULL, "DL2" },"UL9" , NULL, "O002" },"UL9" , NULL, "O003" },"UL9" , NULL, "O004" },"UL9" , NULL, "O005" },"UL9" , NULL, "O006" },"UL9" , NULL, "O007" },"UL9" , NULL, "O008" },"UL9" , NULL, "O009" },"UL9" , NULL, "O010" },"UL9" , NULL, "O011" },"UL9" , NULL, "O012" },"UL9" , NULL, "O013" },"UL9" , NULL, "O014" },"UL9" , NULL, "O015" },"UL9" , NULL, "O016" },"UL9" , NULL, "O017" },"UL9" , NULL, "O018" },"UL9" , NULL, "O019" },"UL9" , NULL, "O020" },"UL9" , NULL, "O021" },"UL9" , NULL, "O022" },"UL9" , NULL, "O023" },"UL9" , NULL, "O024" },"UL9" , NULL, "O025" },"UL9" , NULL, "O026" },"UL9" , NULL, "O027" },"UL9" , NULL, "O028" },"UL9" , NULL, "O029" },"UL9" , NULL, "O030" },"UL9" , NULL, "O031" },"UL9" , NULL, "O032" },"UL9" , NULL, "O033" },"UL4" , NULL, "O034" },"UL4" , NULL, "O035" },"UL5" , NULL, "O036" },"UL5" , NULL, "O037" },"UL10" , NULL, "O038" },"UL10" , NULL, "O039" },"UL10" , NULL, "O182" },"UL10" , NULL, "O183" },"UL2" , NULL, "O040" },"UL2" , NULL, "O041" },"UL2" , NULL, "O042" },"UL2" , NULL, "O043" },"UL2" , NULL, "O044" },"UL2" , NULL, "O045" },"UL2" , NULL, "O046" },"UL2" , NULL, "O047" },"O004" , "I000 Switch" , "I000" },"O005" , "I001 Switch" , "I001" },"O006" , "I000 Switch" , "I000" },"O007" , "I001 Switch" , "I001" },"O010" , "I022 Switch" , "I022" },"O011" , "I023 Switch" , "I023" },"O012" , "I024 Switch" , "I024" },"O013" , "I025 Switch" , "I025" },"O014" , "I026 Switch" , "I026" },"O015" , "I027 Switch" , "I027" },"O016" , "I028 Switch" , "I028" },"O017" , "I029 Switch" , "I029" },"O010" , "I046 Switch" , "I046" },"O011" , "I047 Switch" , "I047" },"O012" , "I048 Switch" , "I048" },"O013" , "I049 Switch" , "I049" },"O014" , "I050 Switch" , "I050" },"O015" , "I051 Switch" , "I051" },"O016" , "I052 Switch" , "I052" },"O017" , "I053 Switch" , "I053" },"O002" , "I022 Switch" , "I022" },"O003" , "I023 Switch" , "I023" },"O004" , "I024 Switch" , "I024" },"O005" , "I025 Switch" , "I025" },"O006" , "I026 Switch" , "I026" },"O007" , "I027 Switch" , "I027" },"O008" , "I028 Switch" , "I028" },"O009" , "I029 Switch" , "I029" },"O010" , "I030 Switch" , "I030" },"O011" , "I031 Switch" , "I031" },"O012" , "I032 Switch" , "I032" },"O013" , "I033 Switch" , "I033" },"O014" , "I034 Switch" , "I034" },"O015" , "I035 Switch" , "I035" },"O016" , "I036 Switch" , "I036" },"O017" , "I037 Switch" , "I037" },"O018" , "I038 Switch" , "I038" },"O019" , "I039 Switch" , "I039" },"O020" , "I040 Switch" , "I040" },"O021" , "I041 Switch" , "I041" },"O022" , "I042 Switch" , "I042" },"O023" , "I043 Switch" , "I043" },"O024" , "I044 Switch" , "I044" },"O025" , "I045 Switch" , "I045" },"O026" , "I046 Switch" , "I046" },"O027" , "I047 Switch" , "I047" },"O028" , "I048 Switch" , "I048" },"O029" , "I049 Switch" , "I049" },"O030" , "I050 Switch" , "I050" },"O031" , "I051 Switch" , "I051" },"O032" , "I052 Switch" , "I052" },"O033" , "I053 Switch" , "I053" },"O002" , "I000 Switch" , "I000" },"O003" , "I001 Switch" , "I001" },"O002" , "I020 Switch" , "I020" },"O003" , "I021 Switch" , "I021" },"O002" , "I070 Switch" , "I070" },"O003" , "I071 Switch" , "I071" },"O034" , "I000 Switch" , "I000" },"O035" , "I001 Switch" , "I001" },"O034" , "I002 Switch" , "I002" },"O035" , "I003 Switch" , "I003" },"O034" , "I012 Switch" , "I012" },"O035" , "I013 Switch" , "I013" },"O034" , "I020 Switch" , "I020" },"O035" , "I021 Switch" , "I021" },"O034" , "I070 Switch" , "I070" },"O035" , "I071 Switch" , "I071" },"O034" , "I072 Switch" , "I072" },"O035" , "I073 Switch" , "I073" },"O036" , "I000 Switch" , "I000" },"O037" , "I001 Switch" , "I001" },"O036" , "I012 Switch" , "I012" },"O037" , "I013 Switch" , "I013" },"O036" , "I020 Switch" , "I020" },"O037" , "I021 Switch" , "I021" },"O036" , "I070 Switch" , "I070" },"O037" , "I071 Switch" , "I071" },"O036" , "I168 Switch" , "I168" },"O037" , "I169 Switch" , "I169" },"O038" , "I022 Switch" , "I022" },"O039" , "I023 Switch" , "I023" },"O182" , "I024 Switch" , "I024" },"O183" , "I025 Switch" , "I025" },"O040" , "I022 Switch" , "I022" },"O041" , "I023 Switch" , "I023" },"O042" , "I024 Switch" , "I024" },"O043" , "I025 Switch" , "I025" },"O044" , "I026 Switch" , "I026" },"O045" , "I027 Switch" , "I027" },"O046" , "I028 Switch" , "I028" },"O047" , "I029 Switch" , "I029" },"O040" , "I002 Switch" , "I002" },"O041" , "I003 Switch" , "I003" },"O002" , "I012 Switch" , "I012" },"O003" , "I013 Switch" , "I013" },"O004" , "I014 Switch" , "I014" },"O005" , "I015 Switch" , "I015" },"O006" , "I016 Switch" , "I016" },"O007" , "I017 Switch" , "I017" },"O008" , "I018 Switch" , "I018" },"O009" , "I019 Switch" , "I019" },"O040" , "I012 Switch" , "I012" },"O041" , "I013 Switch" , "I013" },"O042" , "I014 Switch" , "I014" },"O043" , "I015 Switch" , "I015" },"O044" , "I016 Switch" , "I016" },"O045" , "I017 Switch" , "I017" },"O046" , "I018 Switch" , "I018" },"O047" , "I019 Switch" , "I019" },"O002" , "I072 Switch" , "I072" },"O003" , "I073 Switch" , "I073" },"O004" , "I074 Switch" , "I074" },"O005" , "I075 Switch" , "I075" },"O006" , "I076 Switch" , "I076" },"O007" , "I077 Switch" , "I077" },"O008" , "I078 Switch" , "I078" },"O009" , "I079 Switch" , "I079" },"O010" , "I072 Switch" , "I072" },"O011" , "I073 Switch" , "I073" },"O012" , "I074 Switch" , "I074" },"O013" , "I075 Switch" , "I075" },"O014" , "I076 Switch" , "I076" },"O015" , "I077 Switch" , "I077" },"O016" , "I078 Switch" , "I078" },"O017" , "I079 Switch" , "I079" },"O018" , "I080 Switch" , "I080" },"O019" , "I081 Switch" , "I081" },"O020" , "I082 Switch" , "I082" },"O021" , "I083 Switch" , "I083" },"O022" , "I084 Switch" , "I084" },"O023" , "I085 Switch" , "I085" },"O024" , "I086 Switch" , "I086" },"O025" , "I087 Switch" , "I087" },"O026" , "I088 Switch" , "I088" },"O027" , "I089 Switch" , "I089" },"O028" , "I090 Switch" , "I090" },"O029" , "I091 Switch" , "I091" },"O030" , "I092 Switch" , "I092" },"O031" , "I093 Switch" , "I093" },"O032" , "I094 Switch" , "I094" },"O033" , "I095 Switch" , "I095" },"O002" , "I168 Switch" , "I168" },"O003" , "I169 Switch" , "I169" },"O004" , "I170 Switch" , "I170" },"O005" , "I171 Switch" , "I171" },"O034" , "I168 Switch" , "I168" },"O035" , "I168 Switch" , "I168" },"O035" , "I169 Switch" , "I169" },"O034" , "I170 Switch" , "I170" },"O035" , "I170 Switch" , "I170" },"O035" , "I171 Switch" , "I171" },"O040" , "I168 Switch" , "I168" },"O041" , "I169 Switch" , "I169" },"O042" , "I170 Switch" , "I170" },"O043" , "I171 Switch" , "I171" },static const char * const mt8195_afe_1x_en_sel_text[] = {"a1sys_a2sys" , "a3sys" , "a4sys" ,static const unsigned int mt8195_afe_1x_en_sel_values[] = {0 , 1 , 2 ,static int mt8195_memif_1x_en_sel_put(struct snd_kcontrol *kcontrol,struct snd_ctl_elem_value *ucontrol)struct snd_soc_component *component =struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);struct mt8195_afe_private *afe_priv = afe->platform_priv;struct mtk_dai_memif_priv *memif_priv;unsigned int dai_id = kcontrol->id.device;long val = ucontrol->value.integer.value[0 ];int ret = 0 ;if (val == memif_priv->asys_timing_sel)return 0 ;return ret;static int mt8195_asys_irq_1x_en_sel_put(struct snd_kcontrol *kcontrol,struct snd_ctl_elem_value *ucontrol)struct snd_soc_component *component =struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component);struct mt8195_afe_private *afe_priv = afe->platform_priv;unsigned int id = kcontrol->id.device;long val = ucontrol->value.integer.value[0 ];int ret = 0 ;if (val == afe_priv->irq_priv[id].asys_timing_sel)return 0 ;return ret;static SOC_VALUE_ENUM_SINGLE_DECL(dl2_1x_en_sel_enum,18 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(dl3_1x_en_sel_enum,20 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(dl6_1x_en_sel_enum,22 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(dl7_1x_en_sel_enum,24 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(dl8_1x_en_sel_enum,26 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(dl10_1x_en_sel_enum,28 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(dl11_1x_en_sel_enum,30 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(ul1_1x_en_sel_enum,0 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(ul2_1x_en_sel_enum,2 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(ul3_1x_en_sel_enum,4 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(ul4_1x_en_sel_enum,6 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(ul5_1x_en_sel_enum,8 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(ul6_1x_en_sel_enum,10 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(ul8_1x_en_sel_enum,12 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(ul9_1x_en_sel_enum,14 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(ul10_1x_en_sel_enum,16 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq1_1x_en_sel_enum,0 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq2_1x_en_sel_enum,2 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq3_1x_en_sel_enum,4 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq4_1x_en_sel_enum,6 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq5_1x_en_sel_enum,8 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq6_1x_en_sel_enum,10 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq7_1x_en_sel_enum,12 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq8_1x_en_sel_enum,14 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq9_1x_en_sel_enum,16 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq10_1x_en_sel_enum,18 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq11_1x_en_sel_enum,20 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq12_1x_en_sel_enum,22 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq13_1x_en_sel_enum,24 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq14_1x_en_sel_enum,26 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq15_1x_en_sel_enum,28 , 0 x3,static SOC_VALUE_ENUM_SINGLE_DECL(asys_irq16_1x_en_sel_enum,30 , 0 x3,static const struct snd_kcontrol_new mt8195_memif_controls[] = {"dl2_1x_en_sel" ,"dl3_1x_en_sel" ,"dl6_1x_en_sel" ,"dl7_1x_en_sel" ,"dl8_1x_en_sel" ,"dl10_1x_en_sel" ,"dl11_1x_en_sel" ,"ul1_1x_en_sel" ,"ul2_1x_en_sel" ,"ul3_1x_en_sel" ,"ul4_1x_en_sel" ,"ul5_1x_en_sel" ,"ul6_1x_en_sel" ,"ul8_1x_en_sel" ,"ul9_1x_en_sel" ,"ul10_1x_en_sel" ,"asys_irq1_1x_en_sel" ,"asys_irq2_1x_en_sel" ,"asys_irq3_1x_en_sel" ,"asys_irq4_1x_en_sel" ,"asys_irq5_1x_en_sel" ,"asys_irq6_1x_en_sel" ,"asys_irq7_1x_en_sel" ,"asys_irq8_1x_en_sel" ,"asys_irq9_1x_en_sel" ,"asys_irq10_1x_en_sel" ,"asys_irq11_1x_en_sel" ,"asys_irq12_1x_en_sel" ,"asys_irq13_1x_en_sel" ,"asys_irq14_1x_en_sel" ,"asys_irq15_1x_en_sel" ,"asys_irq16_1x_en_sel" ,static const struct mtk_base_memif_data memif_data[MT8195_AFE_MEMIF_NUM] = {"DL2" ,10 ,0 x1f,1 ,0 ,1 ,0 ,18 ,5 ,18 ,0 ,0 x1f,18 ,18 ,"DL3" ,15 ,0 x1f,1 ,0 ,1 ,0 ,19 ,5 ,19 ,0 ,0 x1f,19 ,19 ,"DL6" ,0 ,0 x1f,1 ,0 ,1 ,0 ,22 ,5 ,22 ,0 ,0 x1f,22 ,22 ,"DL7" ,1 ,0 ,0 ,1 ,0 ,1 ,0 ,23 ,5 ,23 ,0 ,0 x1f,23 ,23 ,"DL8" ,10 ,0 x1f,1 ,0 ,1 ,0 ,24 ,6 ,1 ,0 ,0 ,0 x3f,24 ,24 ,"DL10" ,20 ,0 x1f,1 ,0 ,1 ,0 ,26 ,5 ,1 ,0 ,0 ,0 x1f,26 ,26 ,"DL11" ,25 ,0 x1f,1 ,0 ,1 ,0 ,27 ,7 ,27 ,0 ,0 x7f,27 ,27 ,"UL1" ,1 ,0 ,0 ,1 ,0 ,1 ,5 ,0 ,1 ,0 ,0 ,0 ,0 ,"UL2" ,5 ,0 x1f,1 ,0 ,2 ,5 ,1 ,1 ,0 ,0 ,1 ,1 ,"UL3" ,10 ,0 x1f,1 ,0 ,3 ,5 ,2 ,1 ,0 ,0 ,2 ,2 ,"UL4" ,15 ,0 x1f,1 ,0 ,4 ,5 ,3 ,1 ,0 ,0 ,3 ,3 ,"UL5" ,20 ,0 x1f,1 ,0 ,5 ,5 ,4 ,1 ,0 ,0 ,4 ,4 ,"UL6" ,1 ,0 ,0 ,1 ,0 ,6 ,5 ,5 ,1 ,0 ,0 ,5 ,5 ,"UL8" ,5 ,0 x1f,1 ,0 ,8 ,5 ,7 ,1 ,0 ,0 ,7 ,7 ,"UL9" ,10 ,0 x1f,1 ,0 ,9 ,5 ,8 ,1 ,0 ,0 ,8 ,8 ,"UL10" ,15 ,0 x1f,1 ,0 ,10 ,5 ,9 ,1 ,0 ,0 ,9 ,9 ,static const struct mtk_base_irq_data irq_data_array[MT8195_AFE_IRQ_NUM] = {1 ,0 ,0 ,1 ,0 ,0 ,31 ,0 ,16 ,1 ,0 ,0 ,1 ,0 ,0 ,31 ,1 ,17 ,0 ,0 xffffff,1 ,0 ,0 ,31 ,2 ,18 ,1 ,0 ,0 ,1 ,0 ,0 ,31 ,7 ,23 ,0 ,0 xffffff,1 ,0 ,0 ,31 ,8 ,24 ,1 ,0 ,0 ,1 ,0 ,0 ,31 ,9 ,25 ,0 ,0 xffffff,24 ,0 x1ffff,31 ,0 ,0 ,0 ,0 xffffff,24 ,0 x1ffff,31 ,1 ,1 ,0 ,0 xffffff,24 ,0 x1ffff,31 ,2 ,2 ,0 ,0 xffffff,24 ,0 x1ffff,31 ,3 ,3 ,0 ,0 xffffff,24 ,0 x1ffff,31 ,4 ,4 ,0 ,0 xffffff,24 ,0 x1ffff,31 ,5 ,5 ,0 ,0 xffffff,24 ,0 x1ffff,31 ,6 ,6 ,0 ,0 xffffff,24 ,0 x1ffff,31 ,7 ,7 ,0 ,0 xffffff,24 ,0 x1ffff,31 ,8 ,8 ,0 ,0 xffffff,24 ,0 x1ffff,31 ,9 ,9 ,0 ,0 xffffff,24 ,0 x1ffff,31 ,10 ,10 ,0 ,0 xffffff,24 ,0 x1ffff,31 ,11 ,11 ,0 ,0 xffffff,24 ,0 x1ffff,31 ,12 ,12 ,0 ,0 xffffff,24 ,0 x1ffff,31 ,13 ,13 ,0 ,0 xffffff,24 ,0 x1ffff,31 ,14 ,14 ,0 ,0 xffffff,24 ,0 x1ffff,31 ,15 ,15 ,static const int mt8195_afe_memif_const_irqs[MT8195_AFE_MEMIF_NUM] = {static bool mt8195_is_volatile_reg(struct device *dev, unsigned int reg)/* these auto-gen reg has read-only bit, so put it as volatile */ /* volatile reg cannot be cached, so cannot be set when power off */ switch (reg) {case AUDIO_TOP_CON0:case AUDIO_TOP_CON1:case AUDIO_TOP_CON3:case AUDIO_TOP_CON4:case AUDIO_TOP_CON5:case AUDIO_TOP_CON6:case ASYS_IRQ_CLR:case ASYS_IRQ_STATUS:case ASYS_IRQ_MON1:case ASYS_IRQ_MON2:case AFE_IRQ_MCU_CLR:case AFE_IRQ_STATUS:case AFE_IRQ3_CON_MON:case AFE_IRQ_MCU_MON2:case ADSP_IRQ_STATUS:case AUDIO_TOP_STA0:case AUDIO_TOP_STA1:case AFE_GAIN1_CUR:case AFE_GAIN2_CUR:case AFE_IEC_BURST_INFO:case AFE_IEC_CHL_STAT0:case AFE_IEC_CHL_STAT1:case AFE_IEC_CHR_STAT0:case AFE_IEC_CHR_STAT1:case AFE_SPDIFIN_CHSTS1:case AFE_SPDIFIN_CHSTS2:case AFE_SPDIFIN_CHSTS3:case AFE_SPDIFIN_CHSTS4:case AFE_SPDIFIN_CHSTS5:case AFE_SPDIFIN_CHSTS6:case AFE_SPDIFIN_DEBUG1:case AFE_SPDIFIN_DEBUG2:case AFE_SPDIFIN_DEBUG3:case AFE_SPDIFIN_DEBUG4:case AFE_SPDIFIN_EC:case AFE_SPDIFIN_CKLOCK_CFG:case AFE_SPDIFIN_BR_DBG1:case AFE_SPDIFIN_CKFBDIV:case AFE_SPDIFIN_INT_EXT:case AFE_SPDIFIN_INT_EXT2:case SPDIFIN_FREQ_STATUS:case SPDIFIN_USERCODE1:case SPDIFIN_USERCODE2:case SPDIFIN_USERCODE3:case SPDIFIN_USERCODE4:case SPDIFIN_USERCODE5:case SPDIFIN_USERCODE6:case SPDIFIN_USERCODE7:case SPDIFIN_USERCODE8:case SPDIFIN_USERCODE9:case SPDIFIN_USERCODE10:case SPDIFIN_USERCODE11:case SPDIFIN_USERCODE12:case AFE_LINEIN_APLL_TUNER_MON:case AFE_EARC_APLL_TUNER_MON:case AFE_CM0_MON:case AFE_CM1_MON:case AFE_CM2_MON:case AFE_MPHONE_MULTI_DET_MON0:case AFE_MPHONE_MULTI_DET_MON1:case AFE_MPHONE_MULTI_DET_MON2:case AFE_MPHONE_MULTI2_DET_MON0:case AFE_MPHONE_MULTI2_DET_MON1:case AFE_MPHONE_MULTI2_DET_MON2:case AFE_ADDA_MTKAIF_MON0:case AFE_ADDA_MTKAIF_MON1:case AFE_AUD_PAD_TOP:case AFE_ADDA6_MTKAIF_MON0:case AFE_ADDA6_MTKAIF_MON1:case AFE_ADDA6_SRC_DEBUG_MON0:case AFE_ADDA6_UL_SRC_MON0:case AFE_ADDA6_UL_SRC_MON1:case AFE_ASRC11_NEW_CON8:case AFE_ASRC11_NEW_CON9:case AFE_ASRC12_NEW_CON8:case AFE_ASRC12_NEW_CON9:case AFE_LRCK_CNT:case AFE_DAC_MON0:case AFE_DL2_CUR:case AFE_DL3_CUR:case AFE_DL6_CUR:case AFE_DL7_CUR:case AFE_DL8_CUR:case AFE_DL10_CUR:case AFE_DL11_CUR:case AFE_UL1_CUR:case AFE_UL2_CUR:case AFE_UL3_CUR:case AFE_UL4_CUR:case AFE_UL5_CUR:case AFE_UL6_CUR:case AFE_UL8_CUR:case AFE_UL9_CUR:case AFE_UL10_CUR:case AFE_DL8_CHK_SUM1:case AFE_DL8_CHK_SUM2:case AFE_DL8_CHK_SUM3:case AFE_DL8_CHK_SUM4:case AFE_DL8_CHK_SUM5:case AFE_DL8_CHK_SUM6:case AFE_DL10_CHK_SUM1:case AFE_DL10_CHK_SUM2:case AFE_DL10_CHK_SUM3:case AFE_DL10_CHK_SUM4:case AFE_DL10_CHK_SUM5:case AFE_DL10_CHK_SUM6:case AFE_DL11_CHK_SUM1:case AFE_DL11_CHK_SUM2:case AFE_DL11_CHK_SUM3:case AFE_DL11_CHK_SUM4:case AFE_DL11_CHK_SUM5:case AFE_DL11_CHK_SUM6:case AFE_UL1_CHK_SUM1:case AFE_UL1_CHK_SUM2:case AFE_UL2_CHK_SUM1:case AFE_UL2_CHK_SUM2:case AFE_UL3_CHK_SUM1:case AFE_UL3_CHK_SUM2:case AFE_UL4_CHK_SUM1:case AFE_UL4_CHK_SUM2:case AFE_UL5_CHK_SUM1:case AFE_UL5_CHK_SUM2:case AFE_UL6_CHK_SUM1:case AFE_UL6_CHK_SUM2:case AFE_UL8_CHK_SUM1:case AFE_UL8_CHK_SUM2:case AFE_DL2_CHK_SUM1:case AFE_DL2_CHK_SUM2:case AFE_DL3_CHK_SUM1:case AFE_DL3_CHK_SUM2:case AFE_DL6_CHK_SUM1:case AFE_DL6_CHK_SUM2:case AFE_DL7_CHK_SUM1:case AFE_DL7_CHK_SUM2:case AFE_UL9_CHK_SUM1:case AFE_UL9_CHK_SUM2:case AFE_BUS_MON1:case UL1_MOD2AGT_CNT_LAT:case UL2_MOD2AGT_CNT_LAT:case UL3_MOD2AGT_CNT_LAT:case UL4_MOD2AGT_CNT_LAT:case UL5_MOD2AGT_CNT_LAT:case UL6_MOD2AGT_CNT_LAT:case UL8_MOD2AGT_CNT_LAT:case UL9_MOD2AGT_CNT_LAT:case UL10_MOD2AGT_CNT_LAT:case AFE_MEMIF_BUF_FULL_MON:case AFE_MEMIF_BUF_MON1:case AFE_MEMIF_BUF_MON3:case AFE_MEMIF_BUF_MON4:case AFE_MEMIF_BUF_MON5:case AFE_MEMIF_BUF_MON6:case AFE_MEMIF_BUF_MON7:case AFE_MEMIF_BUF_MON8:case AFE_MEMIF_BUF_MON9:case AFE_MEMIF_BUF_MON10:case DL2_AGENT2MODULE_CNT:case DL3_AGENT2MODULE_CNT:case DL6_AGENT2MODULE_CNT:case DL7_AGENT2MODULE_CNT:case DL8_AGENT2MODULE_CNT:case DL10_AGENT2MODULE_CNT:case DL11_AGENT2MODULE_CNT:case UL1_MODULE2AGENT_CNT:case UL2_MODULE2AGENT_CNT:case UL3_MODULE2AGENT_CNT:case UL4_MODULE2AGENT_CNT:case UL5_MODULE2AGENT_CNT:case UL6_MODULE2AGENT_CNT:case UL8_MODULE2AGENT_CNT:case UL9_MODULE2AGENT_CNT:case UL10_MODULE2AGENT_CNT:case AFE_DMIC0_SRC_DEBUG_MON0:case AFE_DMIC0_UL_SRC_MON0:case AFE_DMIC0_UL_SRC_MON1:case AFE_DMIC1_SRC_DEBUG_MON0:case AFE_DMIC1_UL_SRC_MON0:case AFE_DMIC1_UL_SRC_MON1:case AFE_DMIC2_SRC_DEBUG_MON0:case AFE_DMIC2_UL_SRC_MON0:case AFE_DMIC2_UL_SRC_MON1:case AFE_DMIC3_SRC_DEBUG_MON0:case AFE_DMIC3_UL_SRC_MON0:case AFE_DMIC3_UL_SRC_MON1:case DMIC_GAIN1_CUR:case DMIC_GAIN2_CUR:case DMIC_GAIN3_CUR:case DMIC_GAIN4_CUR:case ETDM_IN1_MONITOR:case ETDM_IN2_MONITOR:case ETDM_OUT1_MONITOR:case ETDM_OUT2_MONITOR:case ETDM_OUT3_MONITOR:case AFE_ADDA_SRC_DEBUG_MON0:case AFE_ADDA_SRC_DEBUG_MON1:case AFE_ADDA_DL_SDM_FIFO_MON:case AFE_ADDA_DL_SRC_LCH_MON:case AFE_ADDA_DL_SRC_RCH_MON:case AFE_ADDA_DL_SDM_OUT_MON:case AFE_GASRC0_NEW_CON8:case AFE_GASRC0_NEW_CON9:case AFE_GASRC0_NEW_CON12:case AFE_GASRC1_NEW_CON8:case AFE_GASRC1_NEW_CON9:case AFE_GASRC1_NEW_CON12:case AFE_GASRC2_NEW_CON8:case AFE_GASRC2_NEW_CON9:case AFE_GASRC2_NEW_CON12:case AFE_GASRC3_NEW_CON8:case AFE_GASRC3_NEW_CON9:case AFE_GASRC3_NEW_CON12:case AFE_GASRC4_NEW_CON8:case AFE_GASRC4_NEW_CON9:case AFE_GASRC4_NEW_CON12:case AFE_GASRC5_NEW_CON8:case AFE_GASRC5_NEW_CON9:case AFE_GASRC5_NEW_CON12:case AFE_GASRC6_NEW_CON8:case AFE_GASRC6_NEW_CON9:case AFE_GASRC6_NEW_CON12:case AFE_GASRC7_NEW_CON8:case AFE_GASRC7_NEW_CON9:case AFE_GASRC7_NEW_CON12:case AFE_GASRC8_NEW_CON8:case AFE_GASRC8_NEW_CON9:case AFE_GASRC8_NEW_CON12:case AFE_GASRC9_NEW_CON8:case AFE_GASRC9_NEW_CON9:case AFE_GASRC9_NEW_CON12:case AFE_GASRC10_NEW_CON8:case AFE_GASRC10_NEW_CON9:case AFE_GASRC10_NEW_CON12:case AFE_GASRC11_NEW_CON8:case AFE_GASRC11_NEW_CON9:case AFE_GASRC11_NEW_CON12:case AFE_GASRC12_NEW_CON8:case AFE_GASRC12_NEW_CON9:case AFE_GASRC12_NEW_CON12:case AFE_GASRC13_NEW_CON8:case AFE_GASRC13_NEW_CON9:case AFE_GASRC13_NEW_CON12:case AFE_GASRC14_NEW_CON8:case AFE_GASRC14_NEW_CON9:case AFE_GASRC14_NEW_CON12:case AFE_GASRC15_NEW_CON8:case AFE_GASRC15_NEW_CON9:case AFE_GASRC15_NEW_CON12:case AFE_GASRC16_NEW_CON8:case AFE_GASRC16_NEW_CON9:case AFE_GASRC16_NEW_CON12:case AFE_GASRC17_NEW_CON8:case AFE_GASRC17_NEW_CON9:case AFE_GASRC17_NEW_CON12:case AFE_GASRC18_NEW_CON8:case AFE_GASRC18_NEW_CON9:case AFE_GASRC18_NEW_CON12:case AFE_GASRC19_NEW_CON8:case AFE_GASRC19_NEW_CON9:case AFE_GASRC19_NEW_CON12:return true ;default :return false ;static const struct regmap_config mt8195_afe_regmap_config = {32 ,4 ,32 ,4 ) + 1 ),#define AFE_IRQ_CLR_BITS (0 x387)#define ASYS_IRQ_CLR_BITS (0 xffff)static irqreturn_t mt8195_afe_irq_handler(int irq_id, void *dev_id)struct mtk_base_afe *afe = dev_id;unsigned int val = 0 ;unsigned int asys_irq_clr_bits = 0 ;unsigned int afe_irq_clr_bits = 0 ;unsigned int irq_status_bits = 0 ;unsigned int irq_clr_bits = 0 ;unsigned int mcu_irq_mask = 0 ;int i = 0 ;int ret = 0 ;if (ret) {"%s irq status err\n" , __func__);goto err_irq;if (ret) {"%s read irq mask err\n" , __func__);goto err_irq;/* only clr cpu irq */ for (i = 0 ; i < MT8195_AFE_MEMIF_NUM; i++) {struct mtk_base_afe_memif *memif = &afe->memif[i];struct mtk_base_irq_data const *irq_data;if (memif->irq_usage < 0 )continue ;if (!(val & irq_status_bits))continue ;if (irq_data->irq_clr_reg == ASYS_IRQ_CLR)else /* clear irq */ if (asys_irq_clr_bits)if (afe_irq_clr_bits)return IRQ_HANDLED;static int mt8195_afe_runtime_suspend(struct device *dev)struct mtk_base_afe *afe = dev_get_drvdata(dev);struct mt8195_afe_private *afe_priv = afe->platform_priv;if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)goto skip_regmap;true );return 0 ;static int mt8195_afe_runtime_resume(struct device *dev)struct mtk_base_afe *afe = dev_get_drvdata(dev);struct mt8195_afe_private *afe_priv = afe->platform_priv;if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl)goto skip_regmap;false );return 0 ;static int init_memif_priv_data(struct mtk_base_afe *afe)struct mt8195_afe_private *afe_priv = afe->platform_priv;struct mtk_dai_memif_priv *memif_priv;int i;for (i = MT8195_AFE_MEMIF_START; i < MT8195_AFE_MEMIF_END; i++) {sizeof (struct mtk_dai_memif_priv),if (!memif_priv)return -ENOMEM;return 0 ;static int mt8195_dai_memif_register(struct mtk_base_afe *afe)struct mtk_base_afe_dai *dai;sizeof (*dai), GFP_KERNEL);if (!dai)return -ENOMEM;return init_memif_priv_data(afe);typedef int (*dai_register_cb)(struct mtk_base_afe *);static const dai_register_cb dai_register_cbs[] = {static const struct reg_sequence mt8195_afe_reg_defaults[] = {0 x387ffff },30 ) },30 ) },0 x12000100 },0 x12000100 },static const struct reg_sequence mt8195_cg_patch[] = {0 xfffffffb },0 xfffffff8 },static int mt8195_afe_pcm_dev_probe(struct platform_device *pdev)struct mtk_base_afe *afe;struct mt8195_afe_private *afe_priv;struct device *dev = &pdev->dev;struct reset_control *rstc;int i, irq_id, ret;if (ret)return dev_err_probe(dev, ret, "failed to assign memory region\n" );33 ));if (ret)return ret;sizeof (*afe), GFP_KERNEL);if (!afe)return -ENOMEM;sizeof (*afe_priv),if (!afe->platform_priv)return -ENOMEM;0 );if (IS_ERR(afe->base_addr))return PTR_ERR(afe->base_addr);/* initial audio related clock */ if (ret)return dev_err_probe(dev, ret, "init clock error\n" );/* reset controller to reset audio regs before regmap cache */ "audiosys" );if (IS_ERR(rstc))return dev_err_probe(dev, PTR_ERR(rstc), "could not get audiosys reset\n" );if (ret)return dev_err_probe(dev, ret, "failed to trigger audio reset\n" );/* irq initialize */ sizeof (*afe->irqs),if (!afe->irqs)return -ENOMEM;for (i = 0 ; i < afe->irqs_size; i++)/* init memif */ sizeof (*afe->memif),if (!afe->memif)return -ENOMEM;for (i = 0 ; i < afe->memif_size; i++) {1 ;true ;/* request irq */ 0 );if (irq_id < 0 )return -ENXIO;"asys-isr" , (void *)afe);if (ret)return dev_err_probe(dev, ret, "could not request_irq for asys-isr\n" );/* init sub_dais */ for (i = 0 ; i < ARRAY_SIZE(dai_register_cbs); i++) {if (ret)return dev_err_probe(dev, ret, "dai cb%i register fail\n" , i);/* init dai_driver and component_driver */ if (ret)return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n" );"mediatek,topckgen" );if (IS_ERR(afe_priv->topckgen))"Cannot find topckgen controller: %ld\n" ,/* enable clock for regcache get default value from hw */ true ;if (ret)return ret;if (ret)return dev_err_probe(dev, ret, "Failed to resume device\n" );if (IS_ERR(afe->regmap)) {goto err_pm_put;if (ret < 0 ) {"Failed to apply cg patch\n" );goto err_pm_put;/* register component */ if (ret) {"err_platform\n" );goto err_pm_put;if (ret)goto err_pm_put;if (ret)return dev_err_probe(dev, ret, "Failed to suspend device\n" );false ;true );return 0 ;return ret;static void mt8195_afe_pcm_dev_remove(struct platform_device *pdev)if (!pm_runtime_status_suspended(&pdev->dev))static const struct of_device_id mt8195_afe_pcm_dt_match[] = {"mediatek,mt8195-audio" , },static const struct dev_pm_ops mt8195_afe_pm_ops = {static struct platform_driver mt8195_afe_pcm_driver = {"mt8195-audio" ,"Mediatek ALSA SoC AFE platform driver for 8195" );"Bicycle Tsai <bicycle.tsai@mediatek.com>" );"GPL v2" );
Messung V0.5 in Prozent C=97 H=96 G=96
