// SPDX-License-Identifier: GPL-2.0-or-later /* * Analog Devices ADAU1373 Audio Codec drive * * Copyright 2011 Analog Devices Inc. * Author: Lars-Peter Clausen <lars@metafoo.de> #include <linux/module.h>#include <linux/init.h>#include <linux/gpio/consumer.h>#include <linux/delay.h>#include <linux/pm.h>#include <linux/property.h>#include <linux/i2c.h>#include <linux/slab.h>#include <sound/core.h>#include <sound/pcm.h>#include <sound/pcm_params.h>#include <sound/tlv.h>#include <sound/soc.h>#include "adau1373.h" #include "adau-utils.h" struct adau1373_dai {unsigned int clk_src;unsigned int sysclk;bool enable_src;bool clock_provider;enum adau1373_micbias_voltage {#define ADAU1373_DRC_SIZE 13 struct adau1373 {struct regmap *regmap;struct adau1373_dai dais[3 ];bool input_differential[4 ];bool lineout_differential;bool lineout_ground_sense;unsigned int num_drc;3 ][ADAU1373_DRC_SIZE];enum adau1373_micbias_voltage micbias1;enum adau1373_micbias_voltage micbias2;#define ADAU1373_INPUT_MODE 0 x00#define ADAU1373_AINL_CTRL(x) (0 x01 + (x) * 2 )#define ADAU1373_AINR_CTRL(x) (0 x02 + (x) * 2 )#define ADAU1373_LLINE_OUT(x) (0 x9 + (x) * 2 )#define ADAU1373_RLINE_OUT(x) (0 xa + (x) * 2 )#define ADAU1373_LSPK_OUT 0 x0d#define ADAU1373_RSPK_OUT 0 x0e#define ADAU1373_LHP_OUT 0 x0f#define ADAU1373_RHP_OUT 0 x10#define ADAU1373_ADC_GAIN 0 x11#define ADAU1373_LADC_MIXER 0 x12#define ADAU1373_RADC_MIXER 0 x13#define ADAU1373_LLINE1_MIX 0 x14#define ADAU1373_RLINE1_MIX 0 x15#define ADAU1373_LLINE2_MIX 0 x16#define ADAU1373_RLINE2_MIX 0 x17#define ADAU1373_LSPK_MIX 0 x18#define ADAU1373_RSPK_MIX 0 x19#define ADAU1373_LHP_MIX 0 x1a#define ADAU1373_RHP_MIX 0 x1b#define ADAU1373_EP_MIX 0 x1c#define ADAU1373_HP_CTRL 0 x1d#define ADAU1373_HP_CTRL2 0 x1e#define ADAU1373_LS_CTRL 0 x1f#define ADAU1373_EP_CTRL 0 x21#define ADAU1373_MICBIAS_CTRL1 0 x22#define ADAU1373_MICBIAS_CTRL2 0 x23#define ADAU1373_OUTPUT_CTRL 0 x24#define ADAU1373_PWDN_CTRL1 0 x25#define ADAU1373_PWDN_CTRL2 0 x26#define ADAU1373_PWDN_CTRL3 0 x27#define ADAU1373_DPLL_CTRL(x) (0 x28 + (x) * 7 )#define ADAU1373_PLL_CTRL1(x) (0 x29 + (x) * 7 )#define ADAU1373_PLL_CTRL2(x) (0 x2a + (x) * 7 )#define ADAU1373_PLL_CTRL3(x) (0 x2b + (x) * 7 )#define ADAU1373_PLL_CTRL4(x) (0 x2c + (x) * 7 )#define ADAU1373_PLL_CTRL5(x) (0 x2d + (x) * 7 )#define ADAU1373_PLL_CTRL6(x) (0 x2e + (x) * 7 )#define ADAU1373_HEADDECT 0 x36#define ADAU1373_ADC_DAC_STATUS 0 x37#define ADAU1373_ADC_CTRL 0 x3c#define ADAU1373_DAI(x) (0 x44 + (x))#define ADAU1373_CLK_SRC_DIV(x) (0 x40 + (x) * 2 )#define ADAU1373_BCLKDIV(x) (0 x47 + (x))#define ADAU1373_SRC_RATIOA(x) (0 x4a + (x) * 2 )#define ADAU1373_SRC_RATIOB(x) (0 x4b + (x) * 2 )#define ADAU1373_DEEMP_CTRL 0 x50#define ADAU1373_SRC_DAI_CTRL(x) (0 x51 + (x))#define ADAU1373_DIN_MIX_CTRL(x) (0 x56 + (x))#define ADAU1373_DOUT_MIX_CTRL(x) (0 x5b + (x))#define ADAU1373_DAI_PBL_VOL(x) (0 x62 + (x) * 2 )#define ADAU1373_DAI_PBR_VOL(x) (0 x63 + (x) * 2 )#define ADAU1373_DAI_RECL_VOL(x) (0 x68 + (x) * 2 )#define ADAU1373_DAI_RECR_VOL(x) (0 x69 + (x) * 2 )#define ADAU1373_DAC1_PBL_VOL 0 x6e#define ADAU1373_DAC1_PBR_VOL 0 x6f#define ADAU1373_DAC2_PBL_VOL 0 x70#define ADAU1373_DAC2_PBR_VOL 0 x71#define ADAU1373_ADC_RECL_VOL 0 x72#define ADAU1373_ADC_RECR_VOL 0 x73#define ADAU1373_DMIC_RECL_VOL 0 x74#define ADAU1373_DMIC_RECR_VOL 0 x75#define ADAU1373_VOL_GAIN1 0 x76#define ADAU1373_VOL_GAIN2 0 x77#define ADAU1373_VOL_GAIN3 0 x78#define ADAU1373_HPF_CTRL 0 x7d#define ADAU1373_BASS1 0 x7e#define ADAU1373_BASS2 0 x7f#define ADAU1373_DRC(x) (0 x80 + (x) * 0 x10)#define ADAU1373_3D_CTRL1 0 xc0#define ADAU1373_3D_CTRL2 0 xc1#define ADAU1373_FDSP_SEL1 0 xdc#define ADAU1373_FDSP_SEL2 0 xdd#define ADAU1373_FDSP_SEL3 0 xde#define ADAU1373_FDSP_SEL4 0 xdf#define ADAU1373_DIGMICCTRL 0 xe2#define ADAU1373_DIGEN 0 xeb#define ADAU1373_SOFT_RESET 0 xff#define ADAU1373_PLL_CTRL6_DPLL_BYPASS BIT(1 )#define ADAU1373_PLL_CTRL6_PLL_EN BIT(0 )#define ADAU1373_DAI_INVERT_BCLK BIT(7 )#define ADAU1373_DAI_MASTER BIT(6 )#define ADAU1373_DAI_INVERT_LRCLK BIT(4 )#define ADAU1373_DAI_WLEN_16 0 x0#define ADAU1373_DAI_WLEN_20 0 x4#define ADAU1373_DAI_WLEN_24 0 x8#define ADAU1373_DAI_WLEN_32 0 xc#define ADAU1373_DAI_WLEN_MASK 0 xc#define ADAU1373_DAI_FORMAT_RIGHT_J 0 x0#define ADAU1373_DAI_FORMAT_LEFT_J 0 x1#define ADAU1373_DAI_FORMAT_I2S 0 x2#define ADAU1373_DAI_FORMAT_DSP 0 x3#define ADAU1373_BCLKDIV_SOURCE BIT(5 )#define ADAU1373_BCLKDIV_SR_MASK (0 x07 << 2 )#define ADAU1373_BCLKDIV_BCLK_MASK 0 x03#define ADAU1373_BCLKDIV_32 0 x03#define ADAU1373_BCLKDIV_64 0 x02#define ADAU1373_BCLKDIV_128 0 x01#define ADAU1373_BCLKDIV_256 0 x00#define ADAU1373_ADC_CTRL_PEAK_DETECT BIT(0 )#define ADAU1373_ADC_CTRL_RESET BIT(1 )#define ADAU1373_ADC_CTRL_RESET_FORCE BIT(2 )#define ADAU1373_OUTPUT_CTRL_LDIFF BIT(3 )#define ADAU1373_OUTPUT_CTRL_LNFBEN BIT(2 )#define ADAU1373_PWDN_CTRL3_PWR_EN BIT(0 )#define ADAU1373_EP_CTRL_MICBIAS1_OFFSET 4 #define ADAU1373_EP_CTRL_MICBIAS2_OFFSET 2 static const struct reg_default adau1373_reg_defaults[] = {0 x00 },0 ), 0 x00 },0 ), 0 x00 },1 ), 0 x00 },1 ), 0 x00 },2 ), 0 x00 },2 ), 0 x00 },3 ), 0 x00 },3 ), 0 x00 },0 ), 0 x00 },0 ), 0 x00 },1 ), 0 x00 },1 ), 0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 ), 0 x00 },0 ), 0 x00 },0 ), 0 x00 },0 ), 0 x00 },0 ), 0 x00 },0 ), 0 x00 },0 ), 0 x02 },1 ), 0 x00 },1 ), 0 x00 },1 ), 0 x00 },1 ), 0 x00 },1 ), 0 x00 },1 ), 0 x00 },1 ), 0 x02 },0 x00 },0 x00 },0 ), 0 x00 },1 ), 0 x00 },0 ), 0 x0a },1 ), 0 x0a },2 ), 0 x0a },0 ), 0 x00 },1 ), 0 x00 },2 ), 0 x00 },0 ), 0 x00 },0 ), 0 x00 },1 ), 0 x00 },1 ), 0 x00 },2 ), 0 x00 },2 ), 0 x00 },0 x00 },0 ), 0 x08 },1 ), 0 x08 },2 ), 0 x08 },0 ), 0 x00 },1 ), 0 x00 },2 ), 0 x00 },3 ), 0 x00 },4 ), 0 x00 },0 ), 0 x00 },1 ), 0 x00 },2 ), 0 x00 },3 ), 0 x00 },4 ), 0 x00 },0 ), 0 x00 },0 ), 0 x00 },1 ), 0 x00 },1 ), 0 x00 },2 ), 0 x00 },2 ), 0 x00 },0 ), 0 x00 },0 ), 0 x00 },1 ), 0 x00 },1 ), 0 x00 },2 ), 0 x00 },2 ), 0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 ) + 0 x0, 0 x78 },0 ) + 0 x1, 0 x18 },0 ) + 0 x2, 0 x00 },0 ) + 0 x3, 0 x00 },0 ) + 0 x4, 0 x00 },0 ) + 0 x5, 0 xc0 },0 ) + 0 x6, 0 x00 },0 ) + 0 x7, 0 x00 },0 ) + 0 x8, 0 x00 },0 ) + 0 x9, 0 xc0 },0 ) + 0 xa, 0 x88 },0 ) + 0 xb, 0 x7a },0 ) + 0 xc, 0 xdf },0 ) + 0 xd, 0 x20 },0 ) + 0 xe, 0 x00 },0 ) + 0 xf, 0 x00 },1 ) + 0 x0, 0 x78 },1 ) + 0 x1, 0 x18 },1 ) + 0 x2, 0 x00 },1 ) + 0 x3, 0 x00 },1 ) + 0 x4, 0 x00 },1 ) + 0 x5, 0 xc0 },1 ) + 0 x6, 0 x00 },1 ) + 0 x7, 0 x00 },1 ) + 0 x8, 0 x00 },1 ) + 0 x9, 0 xc0 },1 ) + 0 xa, 0 x88 },1 ) + 0 xb, 0 x7a },1 ) + 0 xc, 0 xdf },1 ) + 0 xd, 0 x20 },1 ) + 0 xe, 0 x00 },1 ) + 0 xf, 0 x00 },2 ) + 0 x0, 0 x78 },2 ) + 0 x1, 0 x18 },2 ) + 0 x2, 0 x00 },2 ) + 0 x3, 0 x00 },2 ) + 0 x4, 0 x00 },2 ) + 0 x5, 0 xc0 },2 ) + 0 x6, 0 x00 },2 ) + 0 x7, 0 x00 },2 ) + 0 x8, 0 x00 },2 ) + 0 x9, 0 xc0 },2 ) + 0 xa, 0 x88 },2 ) + 0 xb, 0 x7a },2 ) + 0 xc, 0 xdf },2 ) + 0 xd, 0 x20 },2 ) + 0 xe, 0 x00 },2 ) + 0 xf, 0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },static const DECLARE_TLV_DB_RANGE(adau1373_out_tlv,0 , 7 , TLV_DB_SCALE_ITEM(-7900 , 400 , 1 ),8 , 15 , TLV_DB_SCALE_ITEM(-4700 , 300 , 0 ),16 , 23 , TLV_DB_SCALE_ITEM(-2300 , 200 , 0 ),24 , 31 , TLV_DB_SCALE_ITEM(-700 , 100 , 0 )static const DECLARE_TLV_DB_MINMAX(adau1373_digital_tlv, -9563 , 0 );static const DECLARE_TLV_DB_SCALE(adau1373_in_pga_tlv, -1300 , 100 , 1 );static const DECLARE_TLV_DB_SCALE(adau1373_ep_tlv, -600 , 600 , 1 );static const DECLARE_TLV_DB_SCALE(adau1373_input_boost_tlv, 0 , 2000 , 0 );static const DECLARE_TLV_DB_SCALE(adau1373_gain_boost_tlv, 0 , 600 , 0 );static const DECLARE_TLV_DB_SCALE(adau1373_speaker_boost_tlv, 1200 , 600 , 0 );static const char *adau1373_fdsp_sel_text[] = {"None" ,"Channel 1" ,"Channel 2" ,"Channel 3" ,"Channel 4" ,"Channel 5" ,static SOC_ENUM_SINGLE_DECL(adau1373_drc1_channel_enum,4 , adau1373_fdsp_sel_text);static SOC_ENUM_SINGLE_DECL(adau1373_drc2_channel_enum,0 , adau1373_fdsp_sel_text);static SOC_ENUM_SINGLE_DECL(adau1373_drc3_channel_enum,0 , adau1373_fdsp_sel_text);static SOC_ENUM_SINGLE_DECL(adau1373_hpf_channel_enum,0 , adau1373_fdsp_sel_text);static SOC_ENUM_SINGLE_DECL(adau1373_bass_channel_enum,4 , adau1373_fdsp_sel_text);static const char *adau1373_hpf_cutoff_text[] = {"3.7Hz" , "50Hz" , "100Hz" , "150Hz" , "200Hz" , "250Hz" , "300Hz" , "350Hz" ,"400Hz" , "450Hz" , "500Hz" , "550Hz" , "600Hz" , "650Hz" , "700Hz" , "750Hz" ,"800Hz" ,static SOC_ENUM_SINGLE_DECL(adau1373_hpf_cutoff_enum,3 , adau1373_hpf_cutoff_text);static const char *adau1373_bass_lpf_cutoff_text[] = {"801Hz" , "1001Hz" ,static const char *adau1373_bass_clip_level_text[] = {"0.125" , "0.250" , "0.370" , "0.500" , "0.625" , "0.750" , "0.875" ,static const unsigned int adau1373_bass_clip_level_values[] = {1 , 2 , 3 , 4 , 5 , 6 , 7 ,static const char *adau1373_bass_hpf_cutoff_text[] = {"158Hz" , "232Hz" , "347Hz" , "520Hz" ,static const DECLARE_TLV_DB_RANGE(adau1373_bass_tlv,0 , 2 , TLV_DB_SCALE_ITEM(-600 , 600 , 1 ),3 , 4 , TLV_DB_SCALE_ITEM(950 , 250 , 0 ),5 , 7 , TLV_DB_SCALE_ITEM(1400 , 150 , 0 )static SOC_ENUM_SINGLE_DECL(adau1373_bass_lpf_cutoff_enum,5 , adau1373_bass_lpf_cutoff_text);static SOC_VALUE_ENUM_SINGLE_DECL(adau1373_bass_clip_level_enum,2 , 7 , adau1373_bass_clip_level_text,static SOC_ENUM_SINGLE_DECL(adau1373_bass_hpf_cutoff_enum,0 , adau1373_bass_hpf_cutoff_text);static const char *adau1373_3d_level_text[] = {"0%" , "6.67%" , "13.33%" , "20%" , "26.67%" , "33.33%" ,"40%" , "46.67%" , "53.33%" , "60%" , "66.67%" , "73.33%" ,"80%" , "86.67" , "99.33%" , "100%" static const char *adau1373_3d_cutoff_text[] = {"No 3D" , "0.03125 fs" , "0.04583 fs" , "0.075 fs" , "0.11458 fs" ,"0.16875 fs" , "0.27083 fs" static SOC_ENUM_SINGLE_DECL(adau1373_3d_level_enum,4 , adau1373_3d_level_text);static SOC_ENUM_SINGLE_DECL(adau1373_3d_cutoff_enum,0 , adau1373_3d_cutoff_text);static const DECLARE_TLV_DB_RANGE(adau1373_3d_tlv,0 , 0 , TLV_DB_SCALE_ITEM(0 , 0 , 0 ),1 , 7 , TLV_DB_LINEAR_ITEM(-1800 , -120 )static const char *adau1373_lr_mux_text[] = {"Mute" ,"Right Channel (L+R)" ,"Left Channel (L+R)" ,"Stereo" ,static SOC_ENUM_SINGLE_DECL(adau1373_lineout1_lr_mux_enum,4 , adau1373_lr_mux_text);static SOC_ENUM_SINGLE_DECL(adau1373_lineout2_lr_mux_enum,6 , adau1373_lr_mux_text);static SOC_ENUM_SINGLE_DECL(adau1373_speaker_lr_mux_enum,4 , adau1373_lr_mux_text);static const struct snd_kcontrol_new adau1373_controls[] = {"AIF1 Capture Volume" , ADAU1373_DAI_RECL_VOL(0 ),0 ), 0 , 0 xff, 1 , adau1373_digital_tlv),"AIF2 Capture Volume" , ADAU1373_DAI_RECL_VOL(1 ),1 ), 0 , 0 xff, 1 , adau1373_digital_tlv),"AIF3 Capture Volume" , ADAU1373_DAI_RECL_VOL(2 ),2 ), 0 , 0 xff, 1 , adau1373_digital_tlv),"ADC Capture Volume" , ADAU1373_ADC_RECL_VOL,0 , 0 xff, 1 , adau1373_digital_tlv),"DMIC Capture Volume" , ADAU1373_DMIC_RECL_VOL,0 , 0 xff, 1 , adau1373_digital_tlv),"AIF1 Playback Volume" , ADAU1373_DAI_PBL_VOL(0 ),0 ), 0 , 0 xff, 1 , adau1373_digital_tlv),"AIF2 Playback Volume" , ADAU1373_DAI_PBL_VOL(1 ),1 ), 0 , 0 xff, 1 , adau1373_digital_tlv),"AIF3 Playback Volume" , ADAU1373_DAI_PBL_VOL(2 ),2 ), 0 , 0 xff, 1 , adau1373_digital_tlv),"DAC1 Playback Volume" , ADAU1373_DAC1_PBL_VOL,0 , 0 xff, 1 , adau1373_digital_tlv),"DAC2 Playback Volume" , ADAU1373_DAC2_PBL_VOL,0 , 0 xff, 1 , adau1373_digital_tlv),"Lineout1 Playback Volume" , ADAU1373_LLINE_OUT(0 ),0 ), 0 , 0 x1f, 0 , adau1373_out_tlv),"Speaker Playback Volume" , ADAU1373_LSPK_OUT,0 , 0 x1f, 0 , adau1373_out_tlv),"Headphone Playback Volume" , ADAU1373_LHP_OUT,0 , 0 x1f, 0 , adau1373_out_tlv),"Input 1 Capture Volume" , ADAU1373_AINL_CTRL(0 ),0 ), 0 , 0 x1f, 0 , adau1373_in_pga_tlv),"Input 2 Capture Volume" , ADAU1373_AINL_CTRL(1 ),1 ), 0 , 0 x1f, 0 , adau1373_in_pga_tlv),"Input 3 Capture Volume" , ADAU1373_AINL_CTRL(2 ),2 ), 0 , 0 x1f, 0 , adau1373_in_pga_tlv),"Input 4 Capture Volume" , ADAU1373_AINL_CTRL(3 ),3 ), 0 , 0 x1f, 0 , adau1373_in_pga_tlv),"Earpiece Playback Volume" , ADAU1373_EP_CTRL, 0 , 3 , 0 ,"AIF3 Boost Playback Volume" , ADAU1373_VOL_GAIN1, 4 , 5 ,1 , 0 , adau1373_gain_boost_tlv),"AIF2 Boost Playback Volume" , ADAU1373_VOL_GAIN1, 2 , 3 ,1 , 0 , adau1373_gain_boost_tlv),"AIF1 Boost Playback Volume" , ADAU1373_VOL_GAIN1, 0 , 1 ,1 , 0 , adau1373_gain_boost_tlv),"AIF3 Boost Capture Volume" , ADAU1373_VOL_GAIN2, 4 , 5 ,1 , 0 , adau1373_gain_boost_tlv),"AIF2 Boost Capture Volume" , ADAU1373_VOL_GAIN2, 2 , 3 ,1 , 0 , adau1373_gain_boost_tlv),"AIF1 Boost Capture Volume" , ADAU1373_VOL_GAIN2, 0 , 1 ,1 , 0 , adau1373_gain_boost_tlv),"DMIC Boost Capture Volume" , ADAU1373_VOL_GAIN3, 6 , 7 ,1 , 0 , adau1373_gain_boost_tlv),"ADC Boost Capture Volume" , ADAU1373_VOL_GAIN3, 4 , 5 ,1 , 0 , adau1373_gain_boost_tlv),"DAC2 Boost Playback Volume" , ADAU1373_VOL_GAIN3, 2 , 3 ,1 , 0 , adau1373_gain_boost_tlv),"DAC1 Boost Playback Volume" , ADAU1373_VOL_GAIN3, 0 , 1 ,1 , 0 , adau1373_gain_boost_tlv),"Input 1 Boost Capture Volume" , ADAU1373_ADC_GAIN, 0 , 4 ,1 , 0 , adau1373_input_boost_tlv),"Input 2 Boost Capture Volume" , ADAU1373_ADC_GAIN, 1 , 5 ,1 , 0 , adau1373_input_boost_tlv),"Input 3 Boost Capture Volume" , ADAU1373_ADC_GAIN, 2 , 6 ,1 , 0 , adau1373_input_boost_tlv),"Input 4 Boost Capture Volume" , ADAU1373_ADC_GAIN, 3 , 7 ,1 , 0 , adau1373_input_boost_tlv),"Speaker Boost Playback Volume" , ADAU1373_LS_CTRL, 2 , 3 ,1 , 0 , adau1373_speaker_boost_tlv),"Lineout1 LR Mux" , adau1373_lineout1_lr_mux_enum),"Speaker LR Mux" , adau1373_speaker_lr_mux_enum),"HPF Cutoff" , adau1373_hpf_cutoff_enum),"HPF Switch" , ADAU1373_HPF_CTRL, 1 , 0 , 1 , 0 ),"HPF Channel" , adau1373_hpf_channel_enum),"Bass HPF Cutoff" , adau1373_bass_hpf_cutoff_enum),"Bass Clip Level Threshold" , adau1373_bass_clip_level_enum),"Bass LPF Cutoff" , adau1373_bass_lpf_cutoff_enum),"Bass Playback Switch" , ADAU1373_BASS2, 0 , 1 , 1 , 0 ),"Bass Playback Volume" , ADAU1373_BASS2, 2 , 7 , 0 ,"Bass Channel" , adau1373_bass_channel_enum),"3D Freq" , adau1373_3d_cutoff_enum),"3D Level" , adau1373_3d_level_enum),"3D Playback Switch" , ADAU1373_3D_CTRL2, 0 , 1 , 0 ),"3D Playback Volume" , ADAU1373_3D_CTRL2, 2 , 7 , 0 ,"3D Channel" , adau1373_bass_channel_enum),"Zero Cross Switch" , ADAU1373_PWDN_CTRL3, 7 , 1 , 0 ),static const struct snd_kcontrol_new adau1373_lineout2_controls[] = {"Lineout2 Playback Volume" , ADAU1373_LLINE_OUT(1 ),1 ), 0 , 0 x1f, 0 , adau1373_out_tlv),"Lineout2 LR Mux" , adau1373_lineout2_lr_mux_enum),static const struct snd_kcontrol_new adau1373_drc_controls[] = {"DRC1 Channel" , adau1373_drc1_channel_enum),"DRC2 Channel" , adau1373_drc2_channel_enum),"DRC3 Channel" , adau1373_drc3_channel_enum),static int adau1373_pll_event(struct snd_soc_dapm_widget *w,struct snd_kcontrol *kcontrol, int event)struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);unsigned int pll_id = w->name[3 ] - '1' ;unsigned int val;if (SND_SOC_DAPM_EVENT_ON(event))else 0 ;if (SND_SOC_DAPM_EVENT_ON(event))5 );return 0 ;static const char *adau1373_decimator_text[] = {"ADC" ,"DMIC1" ,static SOC_ENUM_SINGLE_VIRT_DECL(adau1373_decimator_enum,static const struct snd_kcontrol_new adau1373_decimator_mux ="Decimator Mux" , adau1373_decimator_enum);static const struct snd_kcontrol_new adau1373_left_adc_mixer_controls[] = {"DAC1 Switch" , ADAU1373_LADC_MIXER, 4 , 1 , 0 ),"Input 4 Switch" , ADAU1373_LADC_MIXER, 3 , 1 , 0 ),"Input 3 Switch" , ADAU1373_LADC_MIXER, 2 , 1 , 0 ),"Input 2 Switch" , ADAU1373_LADC_MIXER, 1 , 1 , 0 ),"Input 1 Switch" , ADAU1373_LADC_MIXER, 0 , 1 , 0 ),static const struct snd_kcontrol_new adau1373_right_adc_mixer_controls[] = {"DAC1 Switch" , ADAU1373_RADC_MIXER, 4 , 1 , 0 ),"Input 4 Switch" , ADAU1373_RADC_MIXER, 3 , 1 , 0 ),"Input 3 Switch" , ADAU1373_RADC_MIXER, 2 , 1 , 0 ),"Input 2 Switch" , ADAU1373_RADC_MIXER, 1 , 1 , 0 ),"Input 1 Switch" , ADAU1373_RADC_MIXER, 0 , 1 , 0 ),#define DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(_name, _reg) \const struct snd_kcontrol_new _name[] = { \"Left DAC2 Switch" , _reg, 7 , 1 , 0 ), \"Right DAC2 Switch" , _reg, 6 , 1 , 0 ), \"Left DAC1 Switch" , _reg, 5 , 1 , 0 ), \"Right DAC1 Switch" , _reg, 4 , 1 , 0 ), \"Input 4 Bypass Switch" , _reg, 3 , 1 , 0 ), \"Input 3 Bypass Switch" , _reg, 2 , 1 , 0 ), \"Input 2 Bypass Switch" , _reg, 1 , 1 , 0 ), \"Input 1 Bypass Switch" , _reg, 0 , 1 , 0 ), \static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line1_mixer_controls,static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line1_mixer_controls,static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line2_mixer_controls,static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line2_mixer_controls,static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_spk_mixer_controls,static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_spk_mixer_controls,static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_ep_mixer_controls,static const struct snd_kcontrol_new adau1373_left_hp_mixer_controls[] = {"Left DAC1 Switch" , ADAU1373_LHP_MIX, 5 , 1 , 0 ),"Left DAC2 Switch" , ADAU1373_LHP_MIX, 4 , 1 , 0 ),"Input 4 Bypass Switch" , ADAU1373_LHP_MIX, 3 , 1 , 0 ),"Input 3 Bypass Switch" , ADAU1373_LHP_MIX, 2 , 1 , 0 ),"Input 2 Bypass Switch" , ADAU1373_LHP_MIX, 1 , 1 , 0 ),"Input 1 Bypass Switch" , ADAU1373_LHP_MIX, 0 , 1 , 0 ),static const struct snd_kcontrol_new adau1373_right_hp_mixer_controls[] = {"Right DAC1 Switch" , ADAU1373_RHP_MIX, 5 , 1 , 0 ),"Right DAC2 Switch" , ADAU1373_RHP_MIX, 4 , 1 , 0 ),"Input 4 Bypass Switch" , ADAU1373_RHP_MIX, 3 , 1 , 0 ),"Input 3 Bypass Switch" , ADAU1373_RHP_MIX, 2 , 1 , 0 ),"Input 2 Bypass Switch" , ADAU1373_RHP_MIX, 1 , 1 , 0 ),"Input 1 Bypass Switch" , ADAU1373_RHP_MIX, 0 , 1 , 0 ),#define DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(_name, _reg) \const struct snd_kcontrol_new _name[] = { \"DMIC2 Swapped Switch" , _reg, 6 , 1 , 0 ), \"DMIC2 Switch" , _reg, 5 , 1 , 0 ), \"ADC/DMIC1 Swapped Switch" , _reg, 4 , 1 , 0 ), \"ADC/DMIC1 Switch" , _reg, 3 , 1 , 0 ), \"AIF3 Switch" , _reg, 2 , 1 , 0 ), \"AIF2 Switch" , _reg, 1 , 1 , 0 ), \"AIF1 Switch" , _reg, 0 , 1 , 0 ), \static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel1_mixer_controls,0 ));static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel2_mixer_controls,1 ));static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel3_mixer_controls,2 ));static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel4_mixer_controls,3 ));static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel5_mixer_controls,4 ));#define DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(_name, _reg) \const struct snd_kcontrol_new _name[] = { \"DSP Channel5 Switch" , _reg, 4 , 1 , 0 ), \"DSP Channel4 Switch" , _reg, 3 , 1 , 0 ), \"DSP Channel3 Switch" , _reg, 2 , 1 , 0 ), \"DSP Channel2 Switch" , _reg, 1 , 1 , 0 ), \"DSP Channel1 Switch" , _reg, 0 , 1 , 0 ), \static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif1_mixer_controls,0 ));static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif2_mixer_controls,1 ));static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif3_mixer_controls,2 ));static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac1_mixer_controls,3 ));static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac2_mixer_controls,4 ));static const struct snd_soc_dapm_widget adau1373_dapm_widgets[] = {/* Datasheet claims Left ADC is bit 6 and Right ADC is bit 7, but that "Left ADC" , NULL, ADAU1373_PWDN_CTRL1, 7 , 0 ),"Right ADC" , NULL, ADAU1373_PWDN_CTRL1, 6 , 0 ),"DMIC1" , NULL, ADAU1373_DIGMICCTRL, 0 , 0 ),"DMIC2" , NULL, ADAU1373_DIGMICCTRL, 2 , 0 ),"Decimator Mux" , SND_SOC_NOPM, 0 , 0 ,"MICBIAS2" , ADAU1373_PWDN_CTRL1, 5 , 0 , NULL, 0 ),"MICBIAS1" , ADAU1373_PWDN_CTRL1, 4 , 0 , NULL, 0 ),"IN4PGA" , ADAU1373_PWDN_CTRL1, 3 , 0 , NULL, 0 ),"IN3PGA" , ADAU1373_PWDN_CTRL1, 2 , 0 , NULL, 0 ),"IN2PGA" , ADAU1373_PWDN_CTRL1, 1 , 0 , NULL, 0 ),"IN1PGA" , ADAU1373_PWDN_CTRL1, 0 , 0 , NULL, 0 ),"Left DAC2" , NULL, ADAU1373_PWDN_CTRL2, 7 , 0 ),"Right DAC2" , NULL, ADAU1373_PWDN_CTRL2, 6 , 0 ),"Left DAC1" , NULL, ADAU1373_PWDN_CTRL2, 5 , 0 ),"Right DAC1" , NULL, ADAU1373_PWDN_CTRL2, 4 , 0 ),"Left ADC Mixer" , SND_SOC_NOPM, 0 , 0 ,"Right ADC Mixer" , SND_SOC_NOPM, 0 , 0 ,"Left Lineout2 Mixer" , ADAU1373_PWDN_CTRL2, 3 , 0 ,"Right Lineout2 Mixer" , ADAU1373_PWDN_CTRL2, 2 , 0 ,"Left Lineout1 Mixer" , ADAU1373_PWDN_CTRL2, 1 , 0 ,"Right Lineout1 Mixer" , ADAU1373_PWDN_CTRL2, 0 , 0 ,"Earpiece Mixer" , ADAU1373_PWDN_CTRL3, 4 , 0 ,"Left Speaker Mixer" , ADAU1373_PWDN_CTRL3, 3 , 0 ,"Right Speaker Mixer" , ADAU1373_PWDN_CTRL3, 2 , 0 ,"Left Headphone Mixer" , SND_SOC_NOPM, 0 , 0 ,"Right Headphone Mixer" , SND_SOC_NOPM, 0 , 0 ,"Headphone Enable" , ADAU1373_PWDN_CTRL3, 1 , 0 ,0 ),"AIF1 CLK" , ADAU1373_SRC_DAI_CTRL(0 ), 0 , 0 ,0 ),"AIF2 CLK" , ADAU1373_SRC_DAI_CTRL(1 ), 0 , 0 ,0 ),"AIF3 CLK" , ADAU1373_SRC_DAI_CTRL(2 ), 0 , 0 ,0 ),"AIF1 IN SRC" , ADAU1373_SRC_DAI_CTRL(0 ), 2 , 0 ,0 ),"AIF1 OUT SRC" , ADAU1373_SRC_DAI_CTRL(0 ), 1 , 0 ,0 ),"AIF2 IN SRC" , ADAU1373_SRC_DAI_CTRL(1 ), 2 , 0 ,0 ),"AIF2 OUT SRC" , ADAU1373_SRC_DAI_CTRL(1 ), 1 , 0 ,0 ),"AIF3 IN SRC" , ADAU1373_SRC_DAI_CTRL(2 ), 2 , 0 ,0 ),"AIF3 OUT SRC" , ADAU1373_SRC_DAI_CTRL(2 ), 1 , 0 ,0 ),"AIF1 IN" , "AIF1 Playback" , 0 , SND_SOC_NOPM, 0 , 0 ),"AIF1 OUT" , "AIF1 Capture" , 0 , SND_SOC_NOPM, 0 , 0 ),"AIF2 IN" , "AIF2 Playback" , 0 , SND_SOC_NOPM, 0 , 0 ),"AIF2 OUT" , "AIF2 Capture" , 0 , SND_SOC_NOPM, 0 , 0 ),"AIF3 IN" , "AIF3 Playback" , 0 , SND_SOC_NOPM, 0 , 0 ),"AIF3 OUT" , "AIF3 Capture" , 0 , SND_SOC_NOPM, 0 , 0 ),"DSP Channel1 Mixer" , SND_SOC_NOPM, 0 , 0 ,"DSP Channel2 Mixer" , SND_SOC_NOPM, 0 , 0 ,"DSP Channel3 Mixer" , SND_SOC_NOPM, 0 , 0 ,"DSP Channel4 Mixer" , SND_SOC_NOPM, 0 , 0 ,"DSP Channel5 Mixer" , SND_SOC_NOPM, 0 , 0 ,"AIF1 Mixer" , SND_SOC_NOPM, 0 , 0 ,"AIF2 Mixer" , SND_SOC_NOPM, 0 , 0 ,"AIF3 Mixer" , SND_SOC_NOPM, 0 , 0 ,"DAC1 Mixer" , SND_SOC_NOPM, 0 , 0 ,"DAC2 Mixer" , SND_SOC_NOPM, 0 , 0 ,"DSP" , ADAU1373_DIGEN, 4 , 0 , NULL, 0 ),"Recording Engine B" , ADAU1373_DIGEN, 3 , 0 , NULL, 0 ),"Recording Engine A" , ADAU1373_DIGEN, 2 , 0 , NULL, 0 ),"Playback Engine B" , ADAU1373_DIGEN, 1 , 0 , NULL, 0 ),"Playback Engine A" , ADAU1373_DIGEN, 0 , 0 , NULL, 0 ),"PLL1" , SND_SOC_NOPM, 0 , 0 , adau1373_pll_event,"PLL2" , SND_SOC_NOPM, 0 , 0 , adau1373_pll_event,"SYSCLK1" , ADAU1373_CLK_SRC_DIV(0 ), 7 , 0 , NULL, 0 ),"SYSCLK2" , ADAU1373_CLK_SRC_DIV(1 ), 7 , 0 , NULL, 0 ),"AIN1L" ),"AIN1R" ),"AIN2L" ),"AIN2R" ),"AIN3L" ),"AIN3R" ),"AIN4L" ),"AIN4R" ),"DMIC1DAT" ),"DMIC2DAT" ),"LOUT1L" ),"LOUT1R" ),"LOUT2L" ),"LOUT2R" ),"HPL" ),"HPR" ),"SPKL" ),"SPKR" ),"EP" ),static int adau1373_check_aif_clk(struct snd_soc_dapm_widget *source,struct snd_soc_dapm_widget *sink)struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);unsigned int dai;const char *clk;3 ] - '1' ;if (!adau1373->dais[dai].clock_provider)return 0 ;if (adau1373->dais[dai].clk_src == ADAU1373_CLK_SRC_PLL1)"SYSCLK1" ;else "SYSCLK2" ;return snd_soc_dapm_widget_name_cmp(source, clk) == 0 ;static int adau1373_check_src(struct snd_soc_dapm_widget *source,struct snd_soc_dapm_widget *sink)struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);unsigned int dai;3 ] - '1' ;return adau1373->dais[dai].enable_src;#define DSP_CHANNEL_MIXER_ROUTES(_sink) \"DMIC2 Swapped Switch" , "DMIC2" }, \"DMIC2 Switch" , "DMIC2" }, \"ADC/DMIC1 Swapped Switch" , "Decimator Mux" }, \"ADC/DMIC1 Switch" , "Decimator Mux" }, \"AIF1 Switch" , "AIF1 IN" }, \"AIF2 Switch" , "AIF2 IN" }, \"AIF3 Switch" , "AIF3 IN" }#define DSP_OUTPUT_MIXER_ROUTES(_sink) \"DSP Channel1 Switch" , "DSP Channel1 Mixer" }, \"DSP Channel2 Switch" , "DSP Channel2 Mixer" }, \"DSP Channel3 Switch" , "DSP Channel3 Mixer" }, \"DSP Channel4 Switch" , "DSP Channel4 Mixer" }, \"DSP Channel5 Switch" , "DSP Channel5 Mixer" }#define LEFT_OUTPUT_MIXER_ROUTES(_sink) \"Right DAC2 Switch" , "Right DAC2" }, \"Left DAC2 Switch" , "Left DAC2" }, \"Right DAC1 Switch" , "Right DAC1" }, \"Left DAC1 Switch" , "Left DAC1" }, \"Input 1 Bypass Switch" , "IN1PGA" }, \"Input 2 Bypass Switch" , "IN2PGA" }, \"Input 3 Bypass Switch" , "IN3PGA" }, \"Input 4 Bypass Switch" , "IN4PGA" }#define RIGHT_OUTPUT_MIXER_ROUTES(_sink) \"Right DAC2 Switch" , "Right DAC2" }, \"Left DAC2 Switch" , "Left DAC2" }, \"Right DAC1 Switch" , "Right DAC1" }, \"Left DAC1 Switch" , "Left DAC1" }, \"Input 1 Bypass Switch" , "IN1PGA" }, \"Input 2 Bypass Switch" , "IN2PGA" }, \"Input 3 Bypass Switch" , "IN3PGA" }, \"Input 4 Bypass Switch" , "IN4PGA" }static const struct snd_soc_dapm_route adau1373_dapm_routes[] = {"Left ADC Mixer" , "DAC1 Switch" , "Left DAC1" },"Left ADC Mixer" , "Input 1 Switch" , "IN1PGA" },"Left ADC Mixer" , "Input 2 Switch" , "IN2PGA" },"Left ADC Mixer" , "Input 3 Switch" , "IN3PGA" },"Left ADC Mixer" , "Input 4 Switch" , "IN4PGA" },"Right ADC Mixer" , "DAC1 Switch" , "Right DAC1" },"Right ADC Mixer" , "Input 1 Switch" , "IN1PGA" },"Right ADC Mixer" , "Input 2 Switch" , "IN2PGA" },"Right ADC Mixer" , "Input 3 Switch" , "IN3PGA" },"Right ADC Mixer" , "Input 4 Switch" , "IN4PGA" },"Left ADC" , NULL, "Left ADC Mixer" },"Right ADC" , NULL, "Right ADC Mixer" },"Decimator Mux" , "ADC" , "Left ADC" },"Decimator Mux" , "ADC" , "Right ADC" },"Decimator Mux" , "DMIC1" , "DMIC1" },"DSP Channel1 Mixer" ),"DSP Channel2 Mixer" ),"DSP Channel3 Mixer" ),"DSP Channel4 Mixer" ),"DSP Channel5 Mixer" ),"AIF1 Mixer" ),"AIF2 Mixer" ),"AIF3 Mixer" ),"DAC1 Mixer" ),"DAC2 Mixer" ),"AIF1 OUT" , NULL, "AIF1 Mixer" },"AIF2 OUT" , NULL, "AIF2 Mixer" },"AIF3 OUT" , NULL, "AIF3 Mixer" },"Left DAC1" , NULL, "DAC1 Mixer" },"Right DAC1" , NULL, "DAC1 Mixer" },"Left DAC2" , NULL, "DAC2 Mixer" },"Right DAC2" , NULL, "DAC2 Mixer" },"Left Lineout1 Mixer" ),"Right Lineout1 Mixer" ),"Left Lineout2 Mixer" ),"Right Lineout2 Mixer" ),"Left Speaker Mixer" ),"Right Speaker Mixer" ),"Left Headphone Mixer" , "Left DAC2 Switch" , "Left DAC2" },"Left Headphone Mixer" , "Left DAC1 Switch" , "Left DAC1" },"Left Headphone Mixer" , "Input 1 Bypass Switch" , "IN1PGA" },"Left Headphone Mixer" , "Input 2 Bypass Switch" , "IN2PGA" },"Left Headphone Mixer" , "Input 3 Bypass Switch" , "IN3PGA" },"Left Headphone Mixer" , "Input 4 Bypass Switch" , "IN4PGA" },"Right Headphone Mixer" , "Right DAC2 Switch" , "Right DAC2" },"Right Headphone Mixer" , "Right DAC1 Switch" , "Right DAC1" },"Right Headphone Mixer" , "Input 1 Bypass Switch" , "IN1PGA" },"Right Headphone Mixer" , "Input 2 Bypass Switch" , "IN2PGA" },"Right Headphone Mixer" , "Input 3 Bypass Switch" , "IN3PGA" },"Right Headphone Mixer" , "Input 4 Bypass Switch" , "IN4PGA" },"Left Headphone Mixer" , NULL, "Headphone Enable" },"Right Headphone Mixer" , NULL, "Headphone Enable" },"Earpiece Mixer" , "Right DAC2 Switch" , "Right DAC2" },"Earpiece Mixer" , "Left DAC2 Switch" , "Left DAC2" },"Earpiece Mixer" , "Right DAC1 Switch" , "Right DAC1" },"Earpiece Mixer" , "Left DAC1 Switch" , "Left DAC1" },"Earpiece Mixer" , "Input 1 Bypass Switch" , "IN1PGA" },"Earpiece Mixer" , "Input 2 Bypass Switch" , "IN2PGA" },"Earpiece Mixer" , "Input 3 Bypass Switch" , "IN3PGA" },"Earpiece Mixer" , "Input 4 Bypass Switch" , "IN4PGA" },"LOUT1L" , NULL, "Left Lineout1 Mixer" },"LOUT1R" , NULL, "Right Lineout1 Mixer" },"LOUT2L" , NULL, "Left Lineout2 Mixer" },"LOUT2R" , NULL, "Right Lineout2 Mixer" },"SPKL" , NULL, "Left Speaker Mixer" },"SPKR" , NULL, "Right Speaker Mixer" },"HPL" , NULL, "Left Headphone Mixer" },"HPR" , NULL, "Right Headphone Mixer" },"EP" , NULL, "Earpiece Mixer" },"IN1PGA" , NULL, "AIN1L" },"IN2PGA" , NULL, "AIN2L" },"IN3PGA" , NULL, "AIN3L" },"IN4PGA" , NULL, "AIN4L" },"IN1PGA" , NULL, "AIN1R" },"IN2PGA" , NULL, "AIN2R" },"IN3PGA" , NULL, "AIN3R" },"IN4PGA" , NULL, "AIN4R" },"SYSCLK1" , NULL, "PLL1" },"SYSCLK2" , NULL, "PLL2" },"Left DAC1" , NULL, "SYSCLK1" },"Right DAC1" , NULL, "SYSCLK1" },"Left DAC2" , NULL, "SYSCLK1" },"Right DAC2" , NULL, "SYSCLK1" },"Left ADC" , NULL, "SYSCLK1" },"Right ADC" , NULL, "SYSCLK1" },"DSP" , NULL, "SYSCLK1" },"AIF1 Mixer" , NULL, "DSP" },"AIF2 Mixer" , NULL, "DSP" },"AIF3 Mixer" , NULL, "DSP" },"DAC1 Mixer" , NULL, "DSP" },"DAC2 Mixer" , NULL, "DSP" },"DAC1 Mixer" , NULL, "Playback Engine A" },"DAC2 Mixer" , NULL, "Playback Engine B" },"Left ADC Mixer" , NULL, "Recording Engine A" },"Right ADC Mixer" , NULL, "Recording Engine A" },"AIF1 CLK" , NULL, "SYSCLK1" , adau1373_check_aif_clk },"AIF2 CLK" , NULL, "SYSCLK1" , adau1373_check_aif_clk },"AIF3 CLK" , NULL, "SYSCLK1" , adau1373_check_aif_clk },"AIF1 CLK" , NULL, "SYSCLK2" , adau1373_check_aif_clk },"AIF2 CLK" , NULL, "SYSCLK2" , adau1373_check_aif_clk },"AIF3 CLK" , NULL, "SYSCLK2" , adau1373_check_aif_clk },"AIF1 IN" , NULL, "AIF1 CLK" },"AIF1 OUT" , NULL, "AIF1 CLK" },"AIF2 IN" , NULL, "AIF2 CLK" },"AIF2 OUT" , NULL, "AIF2 CLK" },"AIF3 IN" , NULL, "AIF3 CLK" },"AIF3 OUT" , NULL, "AIF3 CLK" },"AIF1 IN" , NULL, "AIF1 IN SRC" , adau1373_check_src },"AIF1 OUT" , NULL, "AIF1 OUT SRC" , adau1373_check_src },"AIF2 IN" , NULL, "AIF2 IN SRC" , adau1373_check_src },"AIF2 OUT" , NULL, "AIF2 OUT SRC" , adau1373_check_src },"AIF3 IN" , NULL, "AIF3 IN SRC" , adau1373_check_src },"AIF3 OUT" , NULL, "AIF3 OUT SRC" , adau1373_check_src },"DMIC1" , NULL, "DMIC1DAT" },"DMIC1" , NULL, "SYSCLK1" },"DMIC1" , NULL, "Recording Engine A" },"DMIC2" , NULL, "DMIC2DAT" },"DMIC2" , NULL, "SYSCLK1" },"DMIC2" , NULL, "Recording Engine B" },static int adau1373_hw_params(struct snd_pcm_substream *substream,struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)struct snd_soc_component *component = dai->component;struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];unsigned int div;unsigned int freq;unsigned int ctrl;if (freq % params_rate(params) != 0 )return -EINVAL;switch (freq / params_rate(params)) {case 1024 : /* sysclk / 256 */ 0 ;break ;case 1536 : /* 2/3 sysclk / 256 */ 1 ;break ;case 2048 : /* 1/2 sysclk / 256 */ 2 ;break ;case 3072 : /* 1/3 sysclk / 256 */ 3 ;break ;case 4096 : /* 1/4 sysclk / 256 */ 4 ;break ;case 6144 : /* 1/6 sysclk / 256 */ 5 ;break ;case 5632 : /* 2/11 sysclk / 256 */ 6 ;break ;default :return -EINVAL;0 );2 ) | ADAU1373_BCLKDIV_64);switch (params_width(params)) {case 16 :break ;case 20 :break ;case 24 :break ;case 32 :break ;default :return -EINVAL;return regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id),static int adau1373_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)struct snd_soc_component *component = dai->component;struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];unsigned int ctrl;switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {case SND_SOC_DAIFMT_CBP_CFP:true ;break ;case SND_SOC_DAIFMT_CBC_CFC:0 ;false ;break ;default :return -EINVAL;switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {case SND_SOC_DAIFMT_I2S:break ;case SND_SOC_DAIFMT_LEFT_J:break ;case SND_SOC_DAIFMT_RIGHT_J:break ;case SND_SOC_DAIFMT_DSP_B:break ;default :return -EINVAL;switch (fmt & SND_SOC_DAIFMT_INV_MASK) {case SND_SOC_DAIFMT_NB_NF:break ;case SND_SOC_DAIFMT_IB_NF:break ;case SND_SOC_DAIFMT_NB_IF:break ;case SND_SOC_DAIFMT_IB_IF:break ;default :return -EINVAL;return 0 ;static int adau1373_set_dai_sysclk(struct snd_soc_dai *dai,int clk_id, unsigned int freq, int dir)struct adau1373 *adau1373 = snd_soc_component_get_drvdata(dai->component);struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];switch (clk_id) {case ADAU1373_CLK_SRC_PLL1:case ADAU1373_CLK_SRC_PLL2:break ;default :return -EINVAL;5 );return 0 ;static const struct snd_soc_dai_ops adau1373_dai_ops = {#define ADAU1373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \static struct snd_soc_dai_driver adau1373_dai_driver[] = {0 ,"adau1373-aif1" ,"AIF1 Playback" ,2 ,2 ,"AIF1 Capture" ,2 ,2 ,1 ,1 ,"adau1373-aif2" ,"AIF2 Playback" ,2 ,2 ,"AIF2 Capture" ,2 ,2 ,1 ,2 ,"adau1373-aif3" ,"AIF3 Playback" ,2 ,2 ,"AIF3 Capture" ,2 ,2 ,1 ,static int adau1373_set_pll(struct snd_soc_component *component, int pll_id,int source, unsigned int freq_in, unsigned int freq_out)struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);unsigned int dpll_div = 0 ;5 ];int ret;switch (pll_id) {case ADAU1373_PLL1:case ADAU1373_PLL2:break ;default :return -EINVAL;switch (source) {case ADAU1373_PLL_SRC_BCLK1:case ADAU1373_PLL_SRC_BCLK2:case ADAU1373_PLL_SRC_BCLK3:case ADAU1373_PLL_SRC_LRCLK1:case ADAU1373_PLL_SRC_LRCLK2:case ADAU1373_PLL_SRC_LRCLK3:case ADAU1373_PLL_SRC_MCLK1:case ADAU1373_PLL_SRC_MCLK2:case ADAU1373_PLL_SRC_GPIO1:case ADAU1373_PLL_SRC_GPIO2:case ADAU1373_PLL_SRC_GPIO3:case ADAU1373_PLL_SRC_GPIO4:break ;default :return -EINVAL;if (freq_in < 7813 || freq_in > 27000000 )return -EINVAL;if (freq_out < 45158000 || freq_out > 49152000 )return -EINVAL;/* APLL input needs to be >= 8Mhz, so in case freq_in is less we use the while (freq_in < 8000000 ) {2 ;if (ret)return -EINVAL;if (dpll_div) {11 - dpll_div;0 );else {4 ) | dpll_div);0 ]);1 ]);2 ]);3 ]);4 ]);/* Set sysclk to pll_rate / 4 */ 0 x3f, 0 x09);return 0 ;static void adau1373_load_drc_settings(struct adau1373 *adau1373,unsigned int nr, uint8_t *drc)unsigned int i;for (i = 0 ; i < ADAU1373_DRC_SIZE; ++i)static int adau1373_get_micbias(unsigned int val,enum adau1373_micbias_voltage *micbias)switch (val) {case 2900000 :return 0 ;case 2200000 :return 0 ;case 2600000 :return 0 ;case 1800000 :return 0 ;default :return -EINVAL;static int adau1373_probe(struct snd_soc_component *component)struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);unsigned int val;int i;for (i = 0 ; i < adau1373->num_drc; ++i) {0 ;for (i = 0 ; i < ARRAY_SIZE(adau1373->input_differential); ++i) {if (adau1373->input_differential[i])0 ;if (adau1373->lineout_differential)if (adau1373->lineout_ground_sense)if (!adau1373->lineout_differential) {return 0 ;static int adau1373_set_bias_level(struct snd_soc_component *component,enum snd_soc_bias_level level)struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);switch (level) {case SND_SOC_BIAS_ON:break ;case SND_SOC_BIAS_PREPARE:break ;case SND_SOC_BIAS_STANDBY:break ;case SND_SOC_BIAS_OFF:0 );break ;return 0 ;static int adau1373_resume(struct snd_soc_component *component)struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);return 0 ;static bool adau1373_register_volatile(struct device *dev, unsigned int reg)switch (reg) {case ADAU1373_SOFT_RESET:case ADAU1373_ADC_DAC_STATUS:return true ;default :return false ;static const struct regmap_config adau1373_regmap_config = {8 ,8 ,static const struct snd_soc_component_driver adau1373_component_driver = {1 ,1 ,static void adau1373_reset(void *reset_gpio)1 );static int adau1373_parse_fw(struct device *dev, struct adau1373 *adau1373)int ret, drc_count;unsigned int val;if (device_property_present(dev, "adi,input1-differential" ))0 ] = true ;if (device_property_present(dev, "adi,input2-differential" ))1 ] = true ;if (device_property_present(dev, "adi,input3-differential" ))2 ] = true ;if (device_property_present(dev, "adi,input4-differential" ))3 ] = true ;if (device_property_present(dev, "adi,lineout-differential" ))true ;if (device_property_present(dev, "adi,lineout-gnd-sense" ))true ;"adi,micbias1-microvolt" , &val);if (!ret) {if (ret)return dev_err_probe(dev, ret,"Failed to get micbias1(%u)\n" , val);"adi,micbias2-microvolt" , &val);if (!ret) {if (ret)return dev_err_probe(dev, ret,"Failed to get micbias2(%u)\n" , val);"adi,drc-settings" );if (drc_count < 0 )return 0 ;if (drc_count % ADAU1373_DRC_SIZE != 0 )return dev_err_probe(dev, -EINVAL,"DRC count(%u) not multiple of %u\n" ,if (adau1373->num_drc > ARRAY_SIZE(adau1373->drc_setting))return dev_err_probe(dev, -EINVAL,"Too many DRC settings(%u)\n" ,"adi,drc-settings" ,0 ],if (ret)return dev_err_probe(dev, ret,"Failed to read DRC settings\n" );return 0 ;static int adau1373_i2c_probe(struct i2c_client *client)struct adau1373 *adau1373;struct gpio_desc *gpiod;int ret;sizeof (*adau1373), GFP_KERNEL);if (!adau1373)return -ENOMEM;if (IS_ERR(adau1373->regmap))return PTR_ERR(adau1373->regmap);/* * If the powerdown GPIO is specified, we use it for reset. Otherwise * a software reset is done. "powerdown" ,if (IS_ERR(gpiod))return PTR_ERR(gpiod);if (gpiod) {0 );10 );if (ret)return ret;else {0 x00);if (ret)return ret;return ret;static const struct i2c_device_id adau1373_i2c_id[] = {"adau1373" },static const struct of_device_id adau1373_of_match[] = {"adi,adau1373" , },static struct i2c_driver adau1373_i2c_driver = {"adau1373" ,"ASoC ADAU1373 driver" );"Lars-Peter Clausen <lars@metafoo.de>" );"GPL" );
Messung V0.5 in Prozent C=96 H=91 G=93
¤ Dauer der Verarbeitung: 0.20 Sekunden
(vorverarbeitet am 2026-06-08)
¤ *© Formatika GbR, Deutschland
