AudioScience HPI driver Copyright (C) 1997-2014 AudioScience Inc. <support@audioscience.com>
Hardware Programming Interface (HPI) for AudioScience ASI50xx, AS51xx, ASI6xxx, ASI87xx ASI89xx series adapters. These PCI and PCIe bus adapters are based on a TMS320C6205 PCI bus mastering DSP, and (except ASI50xx) TI TMS320C6xxx floating point DSP
/* BAR0 maps to prefetchable 4 Mbyte memory block set by DSPP. * BAR1 maps to non-prefetchable 8 Mbyte memory block * of DSP memory mapped registers (starting at 0x01800000). * 0x01800000 is hardcoded in the PCI i/f, so that only the offset from this * needs to be added to the BAR1 base address set in the PCI config reg
*/ #define C6205_BAR1_PCI_IO_OFFSET (0x027FFF0L) #define C6205_BAR1_HSR (C6205_BAR1_PCI_IO_OFFSET) #define C6205_BAR1_HDCR (C6205_BAR1_PCI_IO_OFFSET+4) #define C6205_BAR1_DSPP (C6205_BAR1_PCI_IO_OFFSET+8)
/* used to control LED (revA) and reset C6713 (revB) */ #define C6205_BAR0_TIMER1_CTL (0x01980000L)
/* For first 6713 in CE1 space, using DA17,16,2 */ #define HPICL_ADDR 0x01400000L #define HPICH_ADDR 0x01400004L #define HPIAL_ADDR 0x01410000L #define HPIAH_ADDR 0x01410004L #define HPIDIL_ADDR 0x01420000L #define HPIDIH_ADDR 0x01420004L #define HPIDL_ADDR 0x01430000L #define HPIDH_ADDR 0x01430004L
u16 flag_outstream_just_reset[HPI_MAX_STREAMS]; /* a non-NULL handle means there is an HPI allocated buffer */ struct consistent_dma_area instream_host_buffers[HPI_MAX_STREAMS]; struct consistent_dma_area outstream_host_buffers[HPI_MAX_STREAMS]; /* non-zero size means a buffer exists, may be external */
u32 instream_host_buffer_size[HPI_MAX_STREAMS];
u32 outstream_host_buffer_size[HPI_MAX_STREAMS];
if (phm->object != HPI_OBJ_SUBSYSTEM) { /* normal messages must have valid adapter index */
pao = hpi_find_adapter(phm->adapter_index);
} else { /* subsys messages don't address an adapter */
phr->error = HPI_ERROR_INVALID_OBJ_INDEX; return;
}
/** Create an adapter object and initialise it based on resource information * passed in the message * *** NOTE - you cannot use this function AND the FindAdapters function at the * same time, the application must use only one of them to get the adapters ***
*/ staticvoid subsys_create_adapter(struct hpi_message *phm, struct hpi_response *phr)
{ /* create temp adapter obj, because we don't know what index yet */ struct hpi_adapter_obj ao;
u32 os_error_code;
u16 err;
HPI_DEBUG_LOG(DEBUG, " subsys_create_adapter\n");
memset(&ao, 0, sizeof(ao));
ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL); if (!ao.priv) {
HPI_DEBUG_LOG(ERROR, "can't get mem for adapter object\n");
phr->error = HPI_ERROR_MEMORY_ALLOC; return;
}
err = adapter_boot_load_dsp(pao, pos_error_code); if (err) {
HPI_DEBUG_LOG(ERROR, "DSP code load failed\n"); /* no need to clean up as SubSysCreateAdapter */ /* calls DeleteAdapter on error. */ return err;
}
HPI_DEBUG_LOG(INFO, "load DSP code OK\n");
/* allow boot load even if mem alloc wont work */ if (!phw->p_interface_buffer) return HPI_ERROR_MEMORY_ALLOC;
interface = phw->p_interface_buffer;
/* make sure the DSP has started ok */ if (!wait_dsp_ack(phw, H620_HIF_RESET, HPI6205_TIMEOUT * 10)) {
HPI_DEBUG_LOG(ERROR, "timed out waiting reset state \n"); return HPI6205_ERROR_6205_INIT_FAILED;
} /* Note that *pao, *phw are zeroed after allocation, * so pointers and flags are NULL by default. * Allocate bus mastering control cache buffer and tell the DSP about it
*/ if (interface->control_cache.number_of_controls) {
u8 *p_control_cache_virtual;
err = hpios_locked_mem_alloc(&phw->h_control_cache,
interface->control_cache.size_in_bytes,
pao->pci.pci_dev); if (!err)
err = hpios_locked_mem_get_virt_addr(&phw->
h_control_cache,
(void *)&p_control_cache_virtual); if (!err) {
memset(p_control_cache_virtual, 0,
interface->control_cache.size_in_bytes);
HPI_DEBUG_LOG(VERBOSE, "got adapter info type %x index %d serial %d\n",
hr.u.ax.info.adapter_type, hr.u.ax.info.adapter_index,
hr.u.ax.info.serial_number);
}
if (phw->p_cache)
phw->p_cache->adap_idx = pao->index;
/** Free memory areas allocated by adapter * this routine is called from AdapterDelete, * and SubSysCreateAdapter if duplicate index
*/ staticvoid delete_adapter_obj(struct hpi_adapter_obj *pao)
{ struct hpi_hw_obj *phw = pao->priv; int i;
if (hpios_locked_mem_valid(&phw->h_control_cache)) {
hpios_locked_mem_free(&phw->h_control_cache);
hpi_free_control_cache(phw->p_cache);
}
if (hpios_locked_mem_valid(&phw->h_locked_mem)) {
hpios_locked_mem_free(&phw->h_locked_mem);
phw->p_interface_buffer = NULL;
}
for (i = 0; i < HPI_MAX_STREAMS; i++) if (hpios_locked_mem_valid(&phw->instream_host_buffers[i])) {
hpios_locked_mem_free(&phw->instream_host_buffers[i]); /*?phw->InStreamHostBuffers[i] = NULL; */
phw->instream_host_buffer_size[i] = 0;
}
for (i = 0; i < HPI_MAX_STREAMS; i++) if (hpios_locked_mem_valid(&phw->outstream_host_buffers[i])) {
hpios_locked_mem_free(&phw->outstream_host_buffers
[i]);
phw->outstream_host_buffer_size[i] = 0;
}
kfree(phw);
}
if (command == HPI_BUFFER_CMD_EXTERNAL
|| command == HPI_BUFFER_CMD_INTERNAL_ALLOC) { /* ALLOC phase, allocate a buffer with power of 2 size, get its bus address for PCI bus mastering
*/
phm->u.d.u.buffer.buffer_size =
roundup_pow_of_two(phm->u.d.u.buffer.buffer_size); /* return old size and allocated size,
so caller can detect change */
phr->u.d.u.stream_info.data_available =
phw->outstream_host_buffer_size[phm->obj_index];
phr->u.d.u.stream_info.buffer_size =
phm->u.d.u.buffer.buffer_size;
if (phw->outstream_host_buffer_size[phm->obj_index] ==
phm->u.d.u.buffer.buffer_size) { /* Same size, no action required */ return;
}
if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
obj_index]))
hpios_locked_mem_free(&phw->outstream_host_buffers
[phm->obj_index]);
err = hpios_locked_mem_get_phys_addr
(&phw->outstream_host_buffers[phm->obj_index],
&phm->u.d.u.buffer.pci_address); /* get the phys addr into msg for single call alloc caller * needs to do this for split alloc (or use the same message) * return the phy address for split alloc in the respose too
*/
phr->u.d.u.stream_info.auxiliary_data_available =
phm->u.d.u.buffer.pci_address;
if (command == HPI_BUFFER_CMD_EXTERNAL
|| command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) { /* GRANT phase. Set up the BBM status, tell the DSP about the buffer so it can start using BBM.
*/ struct hpi_hostbuffer_status *status;
if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
buffer_size - 1)) {
HPI_DEBUG_LOG(ERROR, "Buffer size must be 2^N not %d\n",
phm->u.d.u.buffer.buffer_size);
phr->error = HPI_ERROR_INVALID_DATASIZE; return;
}
phw->outstream_host_buffer_size[phm->obj_index] =
phm->u.d.u.buffer.buffer_size;
status = &interface->outstream_host_buffer_status[phm->
obj_index];
status->samples_processed = 0;
status->stream_state = HPI_STATE_STOPPED;
status->dsp_index = 0;
status->host_index = status->dsp_index;
status->size_in_bytes = phm->u.d.u.buffer.buffer_size;
status->auxiliary_data_available = 0;
if (phw->outstream_host_buffer_size[phm->obj_index]) { if (command == HPI_BUFFER_CMD_EXTERNAL
|| command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) {
phw->outstream_host_buffer_size[phm->obj_index] = 0;
hw_message(pao, phm, phr); /* Tell adapter to stop using the host buffer. */
} if (command == HPI_BUFFER_CMD_EXTERNAL
|| command == HPI_BUFFER_CMD_INTERNAL_FREE)
hpios_locked_mem_free(&phw->outstream_host_buffers
[phm->obj_index]);
} /* Should HPI_ERROR_INVALID_OPERATION be returned
if no host buffer is allocated? */ else
hpi_init_response(phr, HPI_OBJ_OSTREAM,
HPI_OSTREAM_HOSTBUFFER_FREE, 0);
/* HostBuffers is used to indicate host buffer is internally allocated.
otherwise, assumed external, data written externally */ if (phm->u.d.u.data.pb_data
&& hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
obj_index])) {
u8 *p_bbm_data;
u32 l_first_write;
u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data;
/* either all data,
or enough to fit from current to end of BBM buffer */
l_first_write =
min(phm->u.d.u.data.data_size,
status->size_in_bytes -
(status->host_index & (status->size_in_bytes - 1)));
memcpy(p_bbm_data +
(status->host_index & (status->size_in_bytes - 1)),
p_app_data, l_first_write); /* remaining data if any */
memcpy(p_bbm_data, p_app_data + l_first_write,
phm->u.d.u.data.data_size - l_first_write);
}
/* * This version relies on the DSP code triggering an OStream buffer * update immediately following a SET_FORMAT call. The host has * already written data into the BBM buffer, but the DSP won't know * about it until dwHostIndex is adjusted.
*/ if (phw->flag_outstream_just_reset[phm->obj_index]) { /* Format can only change after reset. Must tell DSP. */
u16 function = phm->function;
phw->flag_outstream_just_reset[phm->obj_index] = 0;
phm->function = HPI_OSTREAM_SET_FORMAT;
hw_message(pao, phm, phr); /* send the format to the DSP */
phm->function = function; if (phr->error) return;
}
err = hpios_locked_mem_get_phys_addr
(&phw->instream_host_buffers[phm->obj_index],
&phm->u.d.u.buffer.pci_address); /* get the phys addr into msg for single call alloc. Caller
needs to do this for split alloc so return the phy address */
phr->u.d.u.stream_info.auxiliary_data_available =
phm->u.d.u.buffer.pci_address; if (err) {
hpios_locked_mem_free(&phw->instream_host_buffers
[phm->obj_index]);
phw->instream_host_buffer_size[phm->obj_index] = 0;
phr->error = HPI_ERROR_MEMORY_ALLOC; return;
}
}
if (phw->instream_host_buffer_size[phm->obj_index]) { if (command == HPI_BUFFER_CMD_EXTERNAL
|| command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) {
phw->instream_host_buffer_size[phm->obj_index] = 0;
hw_message(pao, phm, phr);
}
if (command == HPI_BUFFER_CMD_EXTERNAL
|| command == HPI_BUFFER_CMD_INTERNAL_FREE)
hpios_locked_mem_free(&phw->instream_host_buffers
[phm->obj_index]);
} else { /* Should HPI_ERROR_INVALID_OPERATION be returned
if no host buffer is allocated? */
hpi_init_response(phr, HPI_OBJ_ISTREAM,
HPI_ISTREAM_HOSTBUFFER_FREE, 0);
status = &interface->instream_host_buffer_status[phm->obj_index];
data_available = instream_get_bytes_available(status); if (data_available < phm->u.d.u.data.data_size) {
phr->error = HPI_ERROR_INVALID_DATASIZE; return;
}
if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
obj_index])) { if (hpios_locked_mem_get_virt_addr(&phw->
instream_host_buffers[phm->obj_index],
(void *)&p_bbm_data)) {
phr->error = HPI_ERROR_INVALID_OPERATION; return;
}
/* either all data,
or enough to fit from current to end of BBM buffer */
l_first_read =
min(phm->u.d.u.data.data_size,
status->size_in_bytes -
(status->host_index & (status->size_in_bytes - 1)));
memcpy(p_app_data,
p_bbm_data +
(status->host_index & (status->size_in_bytes - 1)),
l_first_read); /* remaining data if any */
memcpy(p_app_data + l_first_read, p_bbm_data,
phm->u.d.u.data.data_size - l_first_read);
}
status->host_index += phm->u.d.u.data.data_size;
}
/* fix up cases where bootcode id[1] != subsys id */ switch (boot_code_id[1]) { case HPI_ADAPTER_FAMILY_ASI(0x5000):
boot_code_id[0] = boot_code_id[1];
boot_code_id[1] = 0; break; case HPI_ADAPTER_FAMILY_ASI(0x5300): case HPI_ADAPTER_FAMILY_ASI(0x5400): case HPI_ADAPTER_FAMILY_ASI(0x6300):
boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6400); break; case HPI_ADAPTER_FAMILY_ASI(0x5500): case HPI_ADAPTER_FAMILY_ASI(0x5600): case HPI_ADAPTER_FAMILY_ASI(0x6500):
boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6600); break; case HPI_ADAPTER_FAMILY_ASI(0x8800):
boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x8900); break; default: break;
}
/* reset DSP by writing a 1 to the WARMRESET bit */
temp = C6205_HDCR_WARMRESET;
iowrite32(temp, phw->prHDCR);
hpios_delay_micro_seconds(1000);
/* check that PCI i/f was configured by EEPROM */
temp = ioread32(phw->prHSR); if ((temp & (C6205_HSR_CFGERR | C6205_HSR_EEREAD)) !=
C6205_HSR_EEREAD) return HPI6205_ERROR_6205_EEPROM;
temp |= 0x04; /* disable PINTA interrupt */
iowrite32(temp, phw->prHSR);
/* check control register reports PCI boot mode */
temp = ioread32(phw->prHDCR); if (!(temp & C6205_HDCR_PCIBOOT)) return HPI6205_ERROR_6205_REG;
/* try writing a few numbers to the DSP page register */ /* and reading them back. */
temp = 3;
iowrite32(temp, phw->prDSPP); if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) return HPI6205_ERROR_6205_DSPPAGE;
temp = 2;
iowrite32(temp, phw->prDSPP); if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) return HPI6205_ERROR_6205_DSPPAGE;
temp = 1;
iowrite32(temp, phw->prDSPP); if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) return HPI6205_ERROR_6205_DSPPAGE; /* reset DSP page to the correct number */
temp = 0;
iowrite32(temp, phw->prDSPP); if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP)) return HPI6205_ERROR_6205_DSPPAGE;
phw->dsp_page = 0;
/* release 6713 from reset before 6205 is bootloaded. This ensures that the EMIF is inactive, and the 6713 HPI gets the correct bootmode etc
*/ if (boot_code_id[1] != 0) { /* DSP 1 is a C6713 */ /* CLKX0 <- '1' release the C6205 bootmode pulldowns */
boot_loader_write_mem32(pao, 0, 0x018C0024, 0x00002202);
hpios_delay_micro_seconds(100); /* Reset the 6713 #1 - revB */
boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0); /* value of bit 3 is unknown after DSP reset, other bits shoudl be 0 */ if (0 != (boot_loader_read_mem32(pao, 0,
(C6205_BAR0_TIMER1_CTL)) & ~8)) return HPI6205_ERROR_6205_REG;
hpios_delay_micro_seconds(100);
for (dsp = 0; dsp < HPI6205_MAX_FILES_TO_LOAD; dsp++) { /* is there a DSP to load? */ if (boot_code_id[dsp] == 0) continue;
err = boot_loader_config_emif(pao, dsp); if (err) return err;
err = boot_loader_test_internal_memory(pao, dsp); if (err) return err;
err = boot_loader_test_external_memory(pao, dsp); if (err) return err;
err = boot_loader_test_pld(pao, dsp); if (err) return err;
/* write the DSP code down into the DSPs memory */
err = hpi_dsp_code_open(boot_code_id[dsp], pao->pci.pci_dev,
&dsp_code, pos_error_code); if (err) return err;
for (i = 0; i < (int)length; i++) {
data = boot_loader_read_mem32(pao, dsp,
address); if (data != *pcode) {
err = 0; break;
}
pcode++;
address += 4;
} if (err) break;
}
hpi_dsp_code_close(&dsp_code); if (err) return err;
}
/* After bootloading all DSPs, start DSP0 running * The DSP0 code will handle starting and synchronizing with its slaves
*/ if (phw->p_interface_buffer) { /* we need to tell the card the physical PCI address */
u32 physicalPC_iaddress; struct bus_master_interface *interface =
phw->p_interface_buffer;
u32 host_mailbox_address_on_dsp;
u32 physicalPC_iaddress_verify = 0; int time_out = 10; /* set ack so we know when DSP is ready to go */ /* (dwDspAck will be changed to HIF_RESET) */
interface->dsp_ack = H620_HIF_UNKNOWN;
wmb(); /* ensure ack is written before dsp writes back */
/* EMIF CE0 setup - 2Mx32 Sync DRAM on ASI5000 cards only */
setting = 0x00000030;
boot_loader_write_mem32(pao, dsp_index, 0x01800008, setting); if (setting != boot_loader_read_mem32(pao, dsp_index,
0x01800008)) return HPI6205_ERROR_DSP_EMIF1;
/* EMIF CE1 setup - 32 bit async. This is 6713 #1 HPI, */ /* which occupies D15..0. 6713 starts at 27MHz, so need */ /* plenty of wait states. See dsn8701.rtf, and 6713 errata. */ /* WST should be 71, but 63 is max possible */
setting =
(1L << WS_OFS) | (63L << WST_OFS) | (1L << WH_OFS) |
(1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
(2L << MTYPE_OFS);
boot_loader_write_mem32(pao, dsp_index, 0x01800004, setting); if (setting != boot_loader_read_mem32(pao, dsp_index,
0x01800004)) return HPI6205_ERROR_DSP_EMIF2;
/* EMIF CE2 setup - 32 bit async. This is 6713 #2 HPI, */ /* which occupies D15..0. 6713 starts at 27MHz, so need */ /* plenty of wait states */
setting =
(1L << WS_OFS) | (28L << WST_OFS) | (1L << WH_OFS) |
(1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
(2L << MTYPE_OFS);
boot_loader_write_mem32(pao, dsp_index, 0x01800010, setting); if (setting != boot_loader_read_mem32(pao, dsp_index,
0x01800010)) return HPI6205_ERROR_DSP_EMIF3;
/* EMIF CE3 setup - 32 bit async. */ /* This is the PLD on the ASI5000 cards only */
setting =
(1L << WS_OFS) | (10L << WST_OFS) | (1L << WH_OFS) |
(1L << RS_OFS) | (10L << RST_OFS) | (1L << RH_OFS) |
(2L << MTYPE_OFS);
boot_loader_write_mem32(pao, dsp_index, 0x01800014, setting); if (setting != boot_loader_read_mem32(pao, dsp_index,
0x01800014)) return HPI6205_ERROR_DSP_EMIF4;
/* set EMIF SDRAM control for 2Mx32 SDRAM (512x32x4 bank) */ /* need to use this else DSP code crashes? */
boot_loader_write_mem32(pao, dsp_index, 0x01800018,
0x07117000);
} elseif (dsp_index == 1) { /* test access to the C6713s HPI registers */
u32 write_data = 0, read_data = 0, i = 0;
/* Set up HPIC for little endian, by setiing HPIC:HWOB=1 */
write_data = 1;
boot_loader_write_mem32(pao, 0, HPICL_ADDR, write_data);
boot_loader_write_mem32(pao, 0, HPICH_ADDR, write_data); /* C67 HPI is on lower 16bits of 32bit EMIF */
read_data =
0xFFF7 & boot_loader_read_mem32(pao, 0, HPICL_ADDR); if (write_data != read_data) {
HPI_DEBUG_LOG(ERROR, "HPICL %x %x\n", write_data,
read_data); return HPI6205_ERROR_C6713_HPIC;
} /* HPIA - walking ones test */
write_data = 1; for (i = 0; i < 32; i++) {
boot_loader_write_mem32(pao, 0, HPIAL_ADDR,
write_data);
boot_loader_write_mem32(pao, 0, HPIAH_ADDR,
(write_data >> 16));
read_data =
0xFFFF & boot_loader_read_mem32(pao, 0,
HPIAL_ADDR);
read_data =
read_data | ((0xFFFF &
boot_loader_read_mem32(pao, 0,
HPIAH_ADDR))
<< 16); if (read_data != write_data) {
HPI_DEBUG_LOG(ERROR, "HPIA %x %x\n",
write_data, read_data); return HPI6205_ERROR_C6713_HPIA;
}
write_data = write_data << 1;
}
/* setup C67x PLL * ** C6713 datasheet says we cannot program PLL from HPI, * and indeed if we try to set the PLL multiply from the HPI, * the PLL does not seem to lock, so we enable the PLL and * use the default multiply of x 7, which for a 27MHz clock * gives a DSP speed of 189MHz
*/ /* bypass PLL */
boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0000);
hpios_delay_micro_seconds(1000); /* EMIF = 189/3=63MHz */
boot_loader_write_mem32(pao, dsp_index, 0x01B7C120, 0x8002); /* peri = 189/2 */
boot_loader_write_mem32(pao, dsp_index, 0x01B7C11C, 0x8001); /* cpu = 189/1 */
boot_loader_write_mem32(pao, dsp_index, 0x01B7C118, 0x8000);
hpios_delay_micro_seconds(1000); /* ** SGT test to take GPO3 high when we start the PLL */ /* and low when the delay is completed */ /* FSX0 <- '1' (GPO3) */
boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A0A); /* PLL not bypassed */
boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0001);
hpios_delay_micro_seconds(1000); /* FSX0 <- '0' (GPO3) */
boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A02);
/* check that we can read one of the PLL registers */ /* PLL should not be bypassed! */ if ((boot_loader_read_mem32(pao, dsp_index, 0x01B7C100) & 0xF)
!= 0x0001) { return HPI6205_ERROR_C6713_PLL;
} /* setup C67x EMIF (note this is the only use of
BAR1 via BootLoader_WriteMem32) */
boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_GCTL,
0x000034A8);
/* EMIF CE0 setup - 2Mx32 Sync DRAM 31..28 Wr setup 27..22 Wr strobe 21..20 Wr hold 19..16 Rd setup 15..14 - 13..8 Rd strobe 7..4 MTYPE 0011 Sync DRAM 32bits 3 Wr hold MSB 2..0 Rd hold
*/
boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_CE0,
0x00000030);
/* SDRAM refresh timing Need 4,096 refresh cycles every 64ms = 15.625us = 1562cycles of 100MHz = 0x61A
*/
boot_loader_write_mem32(pao, dsp_index,
C6713_EMIF_SDRAMTIMING, 0x00000410);
hpios_delay_micro_seconds(1000);
} elseif (dsp_index == 2) { /* DSP 2 is a C6713 */
}
return 0;
}
static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
u32 start_address, u32 length)
{
u32 i = 0, j = 0;
u32 test_addr = 0;
u32 test_data = 0, data = 0;
length = 1000;
/* for 1st word, test each bit in the 32bit word, */ /* dwLength specifies number of 32bit words to test */ /*for(i=0; i<dwLength; i++) */
i = 0;
{
test_addr = start_address + i * 4;
test_data = 0x00000001; for (j = 0; j < 32; j++) {
boot_loader_write_mem32(pao, dsp_index, test_addr,
test_data);
data = boot_loader_read_mem32(pao, dsp_index,
test_addr); if (data != test_data) {
HPI_DEBUG_LOG(VERBOSE, "Memtest error details " "%08x %08x %08x %i\n", test_addr,
test_data, data, dsp_index); return 1; /* error */
}
test_data = test_data << 1;
} /* for(j) */
} /* for(i) */
/* for the next 100 locations test each location, leaving it as zero */ /* write a zero to the next word in memory before we read */ /* the previous write to make sure every memory location is unique */ for (i = 0; i < 100; i++) {
test_addr = start_address + i * 4;
test_data = 0xA5A55A5A;
boot_loader_write_mem32(pao, dsp_index, test_addr, test_data);
boot_loader_write_mem32(pao, dsp_index, test_addr + 4, 0);
data = boot_loader_read_mem32(pao, dsp_index, test_addr); if (data != test_data) {
HPI_DEBUG_LOG(VERBOSE, "Memtest error details " "%08x %08x %08x %i\n", test_addr, test_data,
data, dsp_index); return 1; /* error */
} /* leave location as zero */
boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);
}
/* zero out entire memory block */ for (i = 0; i < length; i++) {
test_addr = start_address + i * 4;
boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);
} return 0;
}
static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao, int dsp_index)
{ int err = 0; if (dsp_index == 0) { /* DSP 0 is a C6205 */ /* 64K prog mem */
err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
0x10000); if (!err) /* 64K data mem */
err = boot_loader_test_memory(pao, dsp_index,
0x80000000, 0x10000);
} elseif (dsp_index == 1) { /* DSP 1 is a C6713 */ /* 192K internal mem */
err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
0x30000); if (!err) /* 64K internal mem / L2 cache */
err = boot_loader_test_memory(pao, dsp_index,
0x00030000, 0x10000);
}
if (err) return HPI6205_ERROR_DSP_INTMEM; else return 0;
}
if (dsp_index == 0) { /* only test for SDRAM if an ASI5000 card */ if (pao->pci.pci_dev->subsystem_device == 0x5000) { /* DSP 0 is always C6205 */
dRAM_start_address = 0x00400000;
dRAM_size = 0x200000; /*dwDRAMinc=1024; */
} else return 0;
} elseif (dsp_index == 1) { /* DSP 1 is a C6713 */
dRAM_start_address = 0x80000000;
dRAM_size = 0x200000; /*dwDRAMinc=1024; */
}
if (boot_loader_test_memory(pao, dsp_index, dRAM_start_address,
dRAM_size)) return HPI6205_ERROR_DSP_EXTMEM; return 0;
}
static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index)
{
u32 data = 0; if (dsp_index == 0) { /* only test for DSP0 PLD on ASI5000 card */ if (pao->pci.pci_dev->subsystem_device == 0x5000) { /* PLD is located at CE3=0x03000000 */
data = boot_loader_read_mem32(pao, dsp_index,
0x03000008); if ((data & 0xF) != 0x5) return HPI6205_ERROR_DSP_PLD;
data = boot_loader_read_mem32(pao, dsp_index,
0x0300000C); if ((data & 0xF) != 0xA) return HPI6205_ERROR_DSP_PLD;
}
} elseif (dsp_index == 1) { /* DSP 1 is a C6713 */ if (pao->pci.pci_dev->subsystem_device == 0x8700) { /* PLD is located at CE1=0x90000000 */
data = boot_loader_read_mem32(pao, dsp_index,
0x90000010); if ((data & 0xFF) != 0xAA) return HPI6205_ERROR_DSP_PLD; /* 8713 - LED on */
boot_loader_write_mem32(pao, dsp_index, 0x90000000,
0x02);
}
} return 0;
}
/** Transfer data to or from DSP nOperation = H620_H620_HIF_SEND_DATA or H620_HIF_GET_DATA
*/ staticshort hpi6205_transfer_data(struct hpi_adapter_obj *pao, u8 *p_data,
u32 data_size, int operation)
{ struct hpi_hw_obj *phw = pao->priv;
u32 data_transferred = 0;
u16 err = 0;
u32 temp2; struct bus_master_interface *interface = phw->p_interface_buffer;
if (!p_data) return HPI_ERROR_INVALID_DATA_POINTER;
data_size &= ~3L; /* round data_size down to nearest 4 bytes */
/* make sure state is IDLE */ if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) return HPI_ERROR_DSP_HARDWARE;
if (this_copy > HPI6205_SIZEOF_DATA)
this_copy = HPI6205_SIZEOF_DATA;
if (operation == H620_HIF_SEND_DATA)
memcpy((void *)&interface->u.b_data[0],
&p_data[data_transferred], this_copy);
interface->transfer_size_in_bytes = this_copy;
/* DSP must change this back to nOperation */
interface->dsp_ack = H620_HIF_IDLE;
send_dsp_command(phw, operation);
temp2 = wait_dsp_ack(phw, operation, HPI6205_TIMEOUT);
HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n",
HPI6205_TIMEOUT - temp2, this_copy);
if (!temp2) { /* timed out */
HPI_DEBUG_LOG(ERROR, "Timed out waiting for ""state %d got %d\n",
operation, interface->dsp_ack);
break;
} if (operation == H620_HIF_GET_DATA)
memcpy(&p_data[data_transferred],
(void *)&interface->u.b_data[0], this_copy);
/* wait for up to timeout_us microseconds for the DSP to signal state by DMA into dwDspAck
*/ staticint wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us)
{ struct bus_master_interface *interface = phw->p_interface_buffer; int t = timeout_us / 4;
rmb(); /* ensure interface->dsp_ack is up to date */ while ((interface->dsp_ack != state) && --t) {
hpios_delay_micro_seconds(4);
rmb(); /* DSP changes dsp_ack by DMA */
}
/*HPI_DEBUG_LOG(VERBOSE, "Spun %d for %d\n", timeout_us/4-t, state); */ return t * 4;
}
/* set the busmaster interface to cmd, then interrupt the DSP */ staticvoid send_dsp_command(struct hpi_hw_obj *phw, int cmd)
{ struct bus_master_interface *interface = phw->p_interface_buffer;
u32 r;
interface->host_cmd = cmd;
wmb(); /* DSP gets state by DMA, make sure it is written to memory */ /* before we interrupt the DSP */
r = ioread32(phw->prHDCR);
r |= (u32)C6205_HDCR_DSPINT;
iowrite32(r, phw->prHDCR);
r &= ~(u32)C6205_HDCR_DSPINT;
iowrite32(r, phw->prHDCR);
}
if (!time_out2) {
HPI_DEBUG_LOG(ERROR, "(%u) Timed out waiting for ""GET_RESP state [%x]\n",
message_count, interface->dsp_ack);
} else {
HPI_DEBUG_LOG(VERBOSE, "(%u) transition to GET_RESP after %u\n",
message_count, HPI6205_TIMEOUT - time_out2);
} /* spin waiting on HIF interrupt flag (end of msg process) */
time_out = HPI6205_TIMEOUT;
/* read the result */ if (time_out) { if (interface->u.response_buffer.response.size <= phr->size)
memcpy(phr, &interface->u.response_buffer,
interface->u.response_buffer.response.size); else {
HPI_DEBUG_LOG(ERROR, "response len %d too big for buffer %d\n",
interface->u.response_buffer.response.size,
phr->size);
memcpy(phr, &interface->u.response_buffer, sizeof(struct hpi_response_header));
phr->error = HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL;
phr->specific_error =
interface->u.response_buffer.response.size;
phr->size = sizeof(struct hpi_response_header);
}
} /* set interface back to idle */
send_dsp_command(phw, H620_HIF_IDLE);
if (!time_out || !time_out2) {
HPI_DEBUG_LOG(DEBUG, "something timed out!\n"); return HPI6205_ERROR_MSG_RESP_TIMEOUT;
} /* special case for adapter close - */ /* wait for the DSP to indicate it is idle */ if (phm->function == HPI_ADAPTER_CLOSE) { if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
HPI_DEBUG_LOG(DEBUG, "Timeout waiting for idle " "(on adapter_close)\n"); return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT;
}
}
err = hpi_validate_response(phm, phr); return err;
}
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