/* SPDX-License-Identifier: GPL-2.0-only */ /* sm501-regs.h * * Copyright 2006 Simtec Electronics * * Silicon Motion SM501 register definitions /* System Configuration area */ /* System config base */ #define SM501_SYS_CONFIG (0 x000000)/* config 1 */ #define SM501_SYSTEM_CONTROL (0 x000000)#define SM501_SYSCTRL_PANEL_TRISTATE (1 <<0 )#define SM501_SYSCTRL_MEM_TRISTATE (1 <<1 )#define SM501_SYSCTRL_CRT_TRISTATE (1 <<2 )#define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3 <<4 )#define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0 <<4 )#define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1 <<4 )#define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2 <<4 )#define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3 <<4 )#define SM501_SYSCTRL_PCI_CLOCK_RUN_EN (1 <<6 )#define SM501_SYSCTRL_PCI_RETRY_DISABLE (1 <<7 )#define SM501_SYSCTRL_PCI_SUBSYS_LOCK (1 <<11 )#define SM501_SYSCTRL_PCI_BURST_READ_EN (1 <<15 )#define SM501_SYSCTRL_2D_ENGINE_STATUS (1 <<19 )/* miscellaneous control */ #define SM501_MISC_CONTROL (0 x000004)#define SM501_MISC_BUS_SH (0 x0)#define SM501_MISC_BUS_PCI (0 x1)#define SM501_MISC_BUS_XSCALE (0 x2)#define SM501_MISC_BUS_NEC (0 x6)#define SM501_MISC_BUS_MASK (0 x7)#define SM501_MISC_VR_62MB (1 <<3 )#define SM501_MISC_CDR_RESET (1 <<7 )#define SM501_MISC_USB_LB (1 <<8 )#define SM501_MISC_USB_SLAVE (1 <<9 )#define SM501_MISC_BL_1 (1 <<10 )#define SM501_MISC_MC (1 <<11 )#define SM501_MISC_DAC_POWER (1 <<12 )#define SM501_MISC_IRQ_INVERT (1 <<16 )#define SM501_MISC_SH (1 <<17 )#define SM501_MISC_HOLD_EMPTY (0 <<18 )#define SM501_MISC_HOLD_8 (1 <<18 )#define SM501_MISC_HOLD_16 (2 <<18 )#define SM501_MISC_HOLD_24 (3 <<18 )#define SM501_MISC_HOLD_32 (4 <<18 )#define SM501_MISC_HOLD_MASK (7 <<18 )#define SM501_MISC_FREQ_12 (1 <<24 )#define SM501_MISC_PNL_24BIT (1 <<25 )#define SM501_MISC_8051_LE (1 <<26 )#define SM501_GPIO31_0_CONTROL (0 x000008)#define SM501_GPIO63_32_CONTROL (0 x00000C)#define SM501_DRAM_CONTROL (0 x000010)/* command list */ #define SM501_ARBTRTN_CONTROL (0 x000014)/* command list */ #define SM501_COMMAND_LIST_STATUS (0 x000024)/* interrupt debug */ #define SM501_RAW_IRQ_STATUS (0 x000028)#define SM501_RAW_IRQ_CLEAR (0 x000028)#define SM501_IRQ_STATUS (0 x00002C)#define SM501_IRQ_MASK (0 x000030)#define SM501_DEBUG_CONTROL (0 x000034)/* power management */ #define SM501_POWERMODE_P2X_SRC (1 <<29 )#define SM501_POWERMODE_V2X_SRC (1 <<20 )#define SM501_POWERMODE_M_SRC (1 <<12 )#define SM501_POWERMODE_M1_SRC (1 <<4 )#define SM501_CURRENT_GATE (0 x000038)#define SM501_CURRENT_CLOCK (0 x00003C)#define SM501_POWER_MODE_0_GATE (0 x000040)#define SM501_POWER_MODE_0_CLOCK (0 x000044)#define SM501_POWER_MODE_1_GATE (0 x000048)#define SM501_POWER_MODE_1_CLOCK (0 x00004C)#define SM501_SLEEP_MODE_GATE (0 x000050)#define SM501_POWER_MODE_CONTROL (0 x000054)/* power gates for units within the 501 */ #define SM501_GATE_HOST (0 )#define SM501_GATE_MEMORY (1 )#define SM501_GATE_DISPLAY (2 )#define SM501_GATE_2D_ENGINE (3 )#define SM501_GATE_CSC (4 )#define SM501_GATE_ZVPORT (5 )#define SM501_GATE_GPIO (6 )#define SM501_GATE_UART0 (7 )#define SM501_GATE_UART1 (8 )#define SM501_GATE_SSP (10 )#define SM501_GATE_USB_HOST (11 )#define SM501_GATE_USB_GADGET (12 )#define SM501_GATE_UCONTROLLER (17 )#define SM501_GATE_AC97 (18 )/* panel clock */ #define SM501_CLOCK_P2XCLK (24 )/* crt clock */ #define SM501_CLOCK_V2XCLK (16 )/* main clock */ #define SM501_CLOCK_MCLK (8 )/* SDRAM controller clock */ #define SM501_CLOCK_M1XCLK (0 )/* config 2 */ #define SM501_PCI_MASTER_BASE (0 x000058)#define SM501_ENDIAN_CONTROL (0 x00005C)#define SM501_DEVICEID (0 x000060)/* 0x050100A0 */ #define SM501_DEVICEID_SM501 (0 x05010000)#define SM501_DEVICEID_IDMASK (0 xffff0000)#define SM501_DEVICEID_REVMASK (0 x000000ff)#define SM501_PLLCLOCK_COUNT (0 x000064)#define SM501_MISC_TIMING (0 x000068)#define SM501_CURRENT_SDRAM_CLOCK (0 x00006C)#define SM501_PROGRAMMABLE_PLL_CONTROL (0 x000074)/* GPIO base */ #define SM501_GPIO (0 x010000)#define SM501_GPIO_DATA_LOW (0 x00)#define SM501_GPIO_DATA_HIGH (0 x04)#define SM501_GPIO_DDR_LOW (0 x08)#define SM501_GPIO_DDR_HIGH (0 x0C)#define SM501_GPIO_IRQ_SETUP (0 x10)#define SM501_GPIO_IRQ_STATUS (0 x14)#define SM501_GPIO_IRQ_RESET (0 x14)/* I2C controller base */ #define SM501_I2C (0 x010040)#define SM501_I2C_BYTE_COUNT (0 x00)#define SM501_I2C_CONTROL (0 x01)#define SM501_I2C_STATUS (0 x02)#define SM501_I2C_RESET (0 x02)#define SM501_I2C_SLAVE_ADDRESS (0 x03)#define SM501_I2C_DATA (0 x04)/* SSP base */ #define SM501_SSP (0 x020000)/* Uart 0 base */ #define SM501_UART0 (0 x030000)/* Uart 1 base */ #define SM501_UART1 (0 x030020)/* USB host port base */ #define SM501_USB_HOST (0 x040000)/* USB slave/gadget base */ #define SM501_USB_GADGET (0 x060000)/* USB slave/gadget data port base */ #define SM501_USB_GADGET_DATA (0 x070000)/* Display controller/video engine base */ #define SM501_DC (0 x080000)/* common defines for the SM501 address registers */ #define SM501_ADDR_FLIP (1 <<31 )#define SM501_ADDR_EXT (1 <<27 )#define SM501_ADDR_CS1 (1 <<26 )#define SM501_ADDR_MASK (0 x3f << 26 )#define SM501_FIFO_MASK (0 x3 << 16 )#define SM501_FIFO_1 (0 x0 << 16 )#define SM501_FIFO_3 (0 x1 << 16 )#define SM501_FIFO_7 (0 x2 << 16 )#define SM501_FIFO_11 (0 x3 << 16 )/* common registers for panel and the crt */ #define SM501_OFF_DC_H_TOT (0 x000)#define SM501_OFF_DC_V_TOT (0 x008)#define SM501_OFF_DC_H_SYNC (0 x004)#define SM501_OFF_DC_V_SYNC (0 x00C)#define SM501_DC_PANEL_CONTROL (0 x000)#define SM501_DC_PANEL_CONTROL_FPEN (1 <<27 )#define SM501_DC_PANEL_CONTROL_BIAS (1 <<26 )#define SM501_DC_PANEL_CONTROL_DATA (1 <<25 )#define SM501_DC_PANEL_CONTROL_VDD (1 <<24 )#define SM501_DC_PANEL_CONTROL_DP (1 <<23 )#define SM501_DC_PANEL_CONTROL_TFT_888 (0 <<21 )#define SM501_DC_PANEL_CONTROL_TFT_333 (1 <<21 )#define SM501_DC_PANEL_CONTROL_TFT_444 (2 <<21 )#define SM501_DC_PANEL_CONTROL_DE (1 <<20 )#define SM501_DC_PANEL_CONTROL_LCD_TFT (0 <<18 )#define SM501_DC_PANEL_CONTROL_LCD_STN8 (1 <<18 )#define SM501_DC_PANEL_CONTROL_LCD_STN12 (2 <<18 )#define SM501_DC_PANEL_CONTROL_CP (1 <<14 )#define SM501_DC_PANEL_CONTROL_VSP (1 <<13 )#define SM501_DC_PANEL_CONTROL_HSP (1 <<12 )#define SM501_DC_PANEL_CONTROL_CK (1 <<9 )#define SM501_DC_PANEL_CONTROL_TE (1 <<8 )#define SM501_DC_PANEL_CONTROL_VPD (1 <<7 )#define SM501_DC_PANEL_CONTROL_VP (1 <<6 )#define SM501_DC_PANEL_CONTROL_HPD (1 <<5 )#define SM501_DC_PANEL_CONTROL_HP (1 <<4 )#define SM501_DC_PANEL_CONTROL_GAMMA (1 <<3 )#define SM501_DC_PANEL_CONTROL_EN (1 <<2 )#define SM501_DC_PANEL_CONTROL_8BPP (0 <<0 )#define SM501_DC_PANEL_CONTROL_16BPP (1 <<0 )#define SM501_DC_PANEL_CONTROL_32BPP (2 <<0 )#define SM501_DC_PANEL_PANNING_CONTROL (0 x004)#define SM501_DC_PANEL_COLOR_KEY (0 x008)#define SM501_DC_PANEL_FB_ADDR (0 x00C)#define SM501_DC_PANEL_FB_OFFSET (0 x010)#define SM501_DC_PANEL_FB_WIDTH (0 x014)#define SM501_DC_PANEL_FB_HEIGHT (0 x018)#define SM501_DC_PANEL_TL_LOC (0 x01C)#define SM501_DC_PANEL_BR_LOC (0 x020)#define SM501_DC_PANEL_H_TOT (0 x024)#define SM501_DC_PANEL_H_SYNC (0 x028)#define SM501_DC_PANEL_V_TOT (0 x02C)#define SM501_DC_PANEL_V_SYNC (0 x030)#define SM501_DC_PANEL_CUR_LINE (0 x034)#define SM501_DC_VIDEO_CONTROL (0 x040)#define SM501_DC_VIDEO_FB0_ADDR (0 x044)#define SM501_DC_VIDEO_FB_WIDTH (0 x048)#define SM501_DC_VIDEO_FB0_LAST_ADDR (0 x04C)#define SM501_DC_VIDEO_TL_LOC (0 x050)#define SM501_DC_VIDEO_BR_LOC (0 x054)#define SM501_DC_VIDEO_SCALE (0 x058)#define SM501_DC_VIDEO_INIT_SCALE (0 x05C)#define SM501_DC_VIDEO_YUV_CONSTANTS (0 x060)#define SM501_DC_VIDEO_FB1_ADDR (0 x064)#define SM501_DC_VIDEO_FB1_LAST_ADDR (0 x068)#define SM501_DC_VIDEO_ALPHA_CONTROL (0 x080)#define SM501_DC_VIDEO_ALPHA_FB_ADDR (0 x084)#define SM501_DC_VIDEO_ALPHA_FB_OFFSET (0 x088)#define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR (0 x08C)#define SM501_DC_VIDEO_ALPHA_TL_LOC (0 x090)#define SM501_DC_VIDEO_ALPHA_BR_LOC (0 x094)#define SM501_DC_VIDEO_ALPHA_SCALE (0 x098)#define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0 x09C)#define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0 x0A0)#define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP (0 x0A4)#define SM501_DC_PANEL_HWC_BASE (0 x0F0)#define SM501_DC_PANEL_HWC_ADDR (0 x0F0)#define SM501_DC_PANEL_HWC_LOC (0 x0F4)#define SM501_DC_PANEL_HWC_COLOR_1_2 (0 x0F8)#define SM501_DC_PANEL_HWC_COLOR_3 (0 x0FC)#define SM501_HWC_EN (1 <<31 )#define SM501_OFF_HWC_ADDR (0 x00)#define SM501_OFF_HWC_LOC (0 x04)#define SM501_OFF_HWC_COLOR_1_2 (0 x08)#define SM501_OFF_HWC_COLOR_3 (0 x0C)#define SM501_DC_ALPHA_CONTROL (0 x100)#define SM501_DC_ALPHA_FB_ADDR (0 x104)#define SM501_DC_ALPHA_FB_OFFSET (0 x108)#define SM501_DC_ALPHA_TL_LOC (0 x10C)#define SM501_DC_ALPHA_BR_LOC (0 x110)#define SM501_DC_ALPHA_CHROMA_KEY (0 x114)#define SM501_DC_ALPHA_COLOR_LOOKUP (0 x118)#define SM501_DC_CRT_CONTROL (0 x200)#define SM501_DC_CRT_CONTROL_TVP (1 <<15 )#define SM501_DC_CRT_CONTROL_CP (1 <<14 )#define SM501_DC_CRT_CONTROL_VSP (1 <<13 )#define SM501_DC_CRT_CONTROL_HSP (1 <<12 )#define SM501_DC_CRT_CONTROL_VS (1 <<11 )#define SM501_DC_CRT_CONTROL_BLANK (1 <<10 )#define SM501_DC_CRT_CONTROL_SEL (1 <<9 )#define SM501_DC_CRT_CONTROL_TE (1 <<8 )#define SM501_DC_CRT_CONTROL_PIXEL_MASK (0 xF << 4 )#define SM501_DC_CRT_CONTROL_GAMMA (1 <<3 )#define SM501_DC_CRT_CONTROL_ENABLE (1 <<2 )#define SM501_DC_CRT_CONTROL_8BPP (0 <<0 )#define SM501_DC_CRT_CONTROL_16BPP (1 <<0 )#define SM501_DC_CRT_CONTROL_32BPP (2 <<0 )#define SM501_DC_CRT_FB_ADDR (0 x204)#define SM501_DC_CRT_FB_OFFSET (0 x208)#define SM501_DC_CRT_H_TOT (0 x20C)#define SM501_DC_CRT_H_SYNC (0 x210)#define SM501_DC_CRT_V_TOT (0 x214)#define SM501_DC_CRT_V_SYNC (0 x218)#define SM501_DC_CRT_SIGNATURE_ANALYZER (0 x21C)#define SM501_DC_CRT_CUR_LINE (0 x220)#define SM501_DC_CRT_MONITOR_DETECT (0 x224)#define SM501_DC_CRT_HWC_BASE (0 x230)#define SM501_DC_CRT_HWC_ADDR (0 x230)#define SM501_DC_CRT_HWC_LOC (0 x234)#define SM501_DC_CRT_HWC_COLOR_1_2 (0 x238)#define SM501_DC_CRT_HWC_COLOR_3 (0 x23C)#define SM501_DC_PANEL_PALETTE (0 x400)#define SM501_DC_VIDEO_PALETTE (0 x800)#define SM501_DC_CRT_PALETTE (0 xC00)/* Zoom Video port base */ #define SM501_ZVPORT (0 x090000)/* AC97/I2S base */ #define SM501_AC97 (0 x0A0000)/* 8051 micro controller base */ #define SM501_UCONTROLLER (0 x0B0000)/* 8051 micro controller SRAM base */ #define SM501_UCONTROLLER_SRAM (0 x0C0000)/* DMA base */ #define SM501_DMA (0 x0D0000)/* 2d engine base */ #define SM501_2D_ENGINE (0 x100000)#define SM501_2D_SOURCE (0 x00)#define SM501_2D_DESTINATION (0 x04)#define SM501_2D_DIMENSION (0 x08)#define SM501_2D_CONTROL (0 x0C)#define SM501_2D_PITCH (0 x10)#define SM501_2D_FOREGROUND (0 x14)#define SM501_2D_BACKGROUND (0 x18)#define SM501_2D_STRETCH (0 x1C)#define SM501_2D_COLOR_COMPARE (0 x20)#define SM501_2D_COLOR_COMPARE_MASK (0 x24)#define SM501_2D_MASK (0 x28)#define SM501_2D_CLIP_TL (0 x2C)#define SM501_2D_CLIP_BR (0 x30)#define SM501_2D_MONO_PATTERN_LOW (0 x34)#define SM501_2D_MONO_PATTERN_HIGH (0 x38)#define SM501_2D_WINDOW_WIDTH (0 x3C)#define SM501_2D_SOURCE_BASE (0 x40)#define SM501_2D_DESTINATION_BASE (0 x44)#define SM501_2D_ALPHA (0 x48)#define SM501_2D_WRAP (0 x4C)#define SM501_2D_STATUS (0 x50)#define SM501_CSC_Y_SOURCE_BASE (0 xC8)#define SM501_CSC_CONSTANTS (0 xCC)#define SM501_CSC_Y_SOURCE_X (0 xD0)#define SM501_CSC_Y_SOURCE_Y (0 xD4)#define SM501_CSC_U_SOURCE_BASE (0 xD8)#define SM501_CSC_V_SOURCE_BASE (0 xDC)#define SM501_CSC_SOURCE_DIMENSION (0 xE0)#define SM501_CSC_SOURCE_PITCH (0 xE4)#define SM501_CSC_DESTINATION (0 xE8)#define SM501_CSC_DESTINATION_DIMENSION (0 xEC)#define SM501_CSC_DESTINATION_PITCH (0 xF0)#define SM501_CSC_SCALE_FACTOR (0 xF4)#define SM501_CSC_DESTINATION_BASE (0 xF8)#define SM501_CSC_CONTROL (0 xFC)/* 2d engine data port base */ #define SM501_2D_ENGINE_DATA (0 x110000)
Messung V0.5 in Prozent C=95 H=97 G=95
¤ Dauer der Verarbeitung: 0.10 Sekunden
(vorverarbeitet am 2026-06-08)
¤ *© Formatika GbR, Deutschland
