/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ #ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H#define DT_BINDINGS_RESET_TEGRA234_RESET_H/** * @file * @defgroup bpmp_reset_ids Reset ID's * @brief Identifiers for Resets controllable by firmware * @{ #define TEGRA234_RESET_ACTMON 1 U#define TEGRA234_RESET_ADSP_ALL 2 U#define TEGRA234_RESET_DSI_CORE 3 U#define TEGRA234_RESET_CAN1 4 U#define TEGRA234_RESET_CAN2 5 U#define TEGRA234_RESET_DLA0 6 U#define TEGRA234_RESET_DLA1 7 U#define TEGRA234_RESET_DPAUX 8 U#define TEGRA234_RESET_OFA 9 U#define TEGRA234_RESET_NVJPG1 10 U#define TEGRA234_RESET_PEX1_CORE_6 11 U#define TEGRA234_RESET_PEX1_CORE_6_APB 12 U#define TEGRA234_RESET_PEX1_COMMON_APB 13 U#define TEGRA234_RESET_PEX2_CORE_7 14 U#define TEGRA234_RESET_PEX2_CORE_7_APB 15 U#define TEGRA234_RESET_NVDISPLAY 16 U#define TEGRA234_RESET_EQOS 17 U#define TEGRA234_RESET_GPCDMA 18 U#define TEGRA234_RESET_GPU 19 U#define TEGRA234_RESET_HDA 20 U#define TEGRA234_RESET_HDACODEC 21 U#define TEGRA234_RESET_EQOS_MACSEC 22 U#define TEGRA234_RESET_EQOS_MACSEC_SECURE 23 U#define TEGRA234_RESET_I2C1 24 U#define TEGRA234_RESET_PEX2_CORE_8 25 U#define TEGRA234_RESET_PEX2_CORE_8_APB 26 U#define TEGRA234_RESET_PEX2_CORE_9 27 U#define TEGRA234_RESET_PEX2_CORE_9_APB 28 U#define TEGRA234_RESET_I2C2 29 U#define TEGRA234_RESET_I2C3 30 U#define TEGRA234_RESET_I2C4 31 U#define TEGRA234_RESET_I2C6 32 U#define TEGRA234_RESET_I2C7 33 U#define TEGRA234_RESET_I2C8 34 U#define TEGRA234_RESET_I2C9 35 U#define TEGRA234_RESET_ISP 36 U#define TEGRA234_RESET_MIPI_CAL 37 U#define TEGRA234_RESET_MPHY_CLK_CTL 38 U#define TEGRA234_RESET_MPHY_L0_RX 39 U#define TEGRA234_RESET_MPHY_L0_TX 40 U#define TEGRA234_RESET_MPHY_L1_RX 41 U#define TEGRA234_RESET_MPHY_L1_TX 42 U#define TEGRA234_RESET_NVCSI 43 U#define TEGRA234_RESET_NVDEC 44 U#define TEGRA234_RESET_MGBE0_PCS 45 U#define TEGRA234_RESET_MGBE0_MAC 46 U#define TEGRA234_RESET_MGBE0_MACSEC 47 U#define TEGRA234_RESET_MGBE0_MACSEC_SECURE 48 U#define TEGRA234_RESET_MGBE1_PCS 49 U#define TEGRA234_RESET_MGBE1_MAC 50 U#define TEGRA234_RESET_MGBE1_MACSEC 51 U#define TEGRA234_RESET_MGBE1_MACSEC_SECURE 52 U#define TEGRA234_RESET_MGBE2_PCS 53 U#define TEGRA234_RESET_MGBE2_MAC 54 U#define TEGRA234_RESET_MGBE2_MACSEC 55 U#define TEGRA234_RESET_PEX2_CORE_10 56 U#define TEGRA234_RESET_PEX2_CORE_10_APB 57 U#define TEGRA234_RESET_PEX2_COMMON_APB 58 U#define TEGRA234_RESET_NVENC 59 U#define TEGRA234_RESET_MGBE2_MACSEC_SECURE 60 U#define TEGRA234_RESET_NVJPG 61 U#define TEGRA234_RESET_LA 64 U#define TEGRA234_RESET_HWPM 65 U#define TEGRA234_RESET_PVA0_ALL 66 U#define TEGRA234_RESET_CEC 67 U#define TEGRA234_RESET_PWM1 68 U#define TEGRA234_RESET_PWM2 69 U#define TEGRA234_RESET_PWM3 70 U#define TEGRA234_RESET_PWM4 71 U#define TEGRA234_RESET_PWM5 72 U#define TEGRA234_RESET_PWM6 73 U#define TEGRA234_RESET_PWM7 74 U#define TEGRA234_RESET_PWM8 75 U#define TEGRA234_RESET_QSPI0 76 U#define TEGRA234_RESET_QSPI1 77 U#define TEGRA234_RESET_I2S7 78 U#define TEGRA234_RESET_I2S8 79 U#define TEGRA234_RESET_SCE_ALL 80 U#define TEGRA234_RESET_RCE_ALL 81 U#define TEGRA234_RESET_SDMMC1 82 U#define TEGRA234_RESET_RSVD_83 83 U#define TEGRA234_RESET_RSVD_84 84 U#define TEGRA234_RESET_SDMMC4 85 U#define TEGRA234_RESET_MGBE3_PCS 87 U#define TEGRA234_RESET_MGBE3_MAC 88 U#define TEGRA234_RESET_MGBE3_MACSEC 89 U#define TEGRA234_RESET_MGBE3_MACSEC_SECURE 90 U#define TEGRA234_RESET_SPI1 91 U#define TEGRA234_RESET_SPI2 92 U#define TEGRA234_RESET_SPI3 93 U#define TEGRA234_RESET_SPI4 94 U#define TEGRA234_RESET_TACH0 95 U#define TEGRA234_RESET_TACH1 96 U#define TEGRA234_RESET_SPI5 97 U#define TEGRA234_RESET_TSEC 98 U#define TEGRA234_RESET_UARTI 99 U#define TEGRA234_RESET_UARTA 100 U#define TEGRA234_RESET_UARTB 101 U#define TEGRA234_RESET_UARTC 102 U#define TEGRA234_RESET_UARTD 103 U#define TEGRA234_RESET_UARTE 104 U#define TEGRA234_RESET_UARTF 105 U#define TEGRA234_RESET_UARTJ 106 U#define TEGRA234_RESET_UARTH 107 U#define TEGRA234_RESET_UFSHC 108 U#define TEGRA234_RESET_UFSHC_AXI_M 109 U#define TEGRA234_RESET_UFSHC_LP_SEQ 110 U#define TEGRA234_RESET_RSVD_111 111 U#define TEGRA234_RESET_VI 112 U#define TEGRA234_RESET_VIC 113 U#define TEGRA234_RESET_XUSB_PADCTL 114 U#define TEGRA234_RESET_VI2 115 U#define TEGRA234_RESET_PEX0_CORE_0 116 U#define TEGRA234_RESET_PEX0_CORE_1 117 U#define TEGRA234_RESET_PEX0_CORE_2 118 U#define TEGRA234_RESET_PEX0_CORE_3 119 U#define TEGRA234_RESET_PEX0_CORE_4 120 U#define TEGRA234_RESET_PEX0_CORE_0_APB 121 U#define TEGRA234_RESET_PEX0_CORE_1_APB 122 U#define TEGRA234_RESET_PEX0_CORE_2_APB 123 U#define TEGRA234_RESET_PEX0_CORE_3_APB 124 U#define TEGRA234_RESET_PEX0_CORE_4_APB 125 U#define TEGRA234_RESET_PEX0_COMMON_APB 126 U#define TEGRA234_RESET_RSVD_127 127 U#define TEGRA234_RESET_NVHS_UPHY_PLL1 128 U#define TEGRA234_RESET_PEX1_CORE_5 129 U#define TEGRA234_RESET_PEX1_CORE_5_APB 130 U#define TEGRA234_RESET_GBE_UPHY 131 U#define TEGRA234_RESET_GBE_UPHY_PM 132 U#define TEGRA234_RESET_NVHS_UPHY 133 U#define TEGRA234_RESET_NVHS_UPHY_PLL0 134 U#define TEGRA234_RESET_NVHS_UPHY_L0 135 U#define TEGRA234_RESET_NVHS_UPHY_L1 136 U#define TEGRA234_RESET_NVHS_UPHY_L2 137 U#define TEGRA234_RESET_NVHS_UPHY_L3 138 U#define TEGRA234_RESET_NVHS_UPHY_L4 139 U#define TEGRA234_RESET_NVHS_UPHY_L5 140 U#define TEGRA234_RESET_NVHS_UPHY_L6 141 U#define TEGRA234_RESET_NVHS_UPHY_L7 142 U#define TEGRA234_RESET_NVHS_UPHY_PM 143 U#define TEGRA234_RESET_DMIC5 144 U#define TEGRA234_RESET_APE 145 U#define TEGRA234_RESET_PEX_USB_UPHY 146 U#define TEGRA234_RESET_PEX_USB_UPHY_L0 147 U#define TEGRA234_RESET_PEX_USB_UPHY_L1 148 U#define TEGRA234_RESET_PEX_USB_UPHY_L2 149 U#define TEGRA234_RESET_PEX_USB_UPHY_L3 150 U#define TEGRA234_RESET_PEX_USB_UPHY_L4 151 U#define TEGRA234_RESET_PEX_USB_UPHY_L5 152 U#define TEGRA234_RESET_PEX_USB_UPHY_L6 153 U#define TEGRA234_RESET_PEX_USB_UPHY_L7 154 U#define TEGRA234_RESET_PEX_USB_UPHY_PLL0 159 U#define TEGRA234_RESET_PEX_USB_UPHY_PLL1 160 U#define TEGRA234_RESET_PEX_USB_UPHY_PLL2 161 U#define TEGRA234_RESET_PEX_USB_UPHY_PLL3 162 U#define TEGRA234_RESET_GBE_UPHY_L0 163 U#define TEGRA234_RESET_GBE_UPHY_L1 164 U#define TEGRA234_RESET_GBE_UPHY_L2 165 U#define TEGRA234_RESET_GBE_UPHY_L3 166 U#define TEGRA234_RESET_GBE_UPHY_L4 167 U#define TEGRA234_RESET_GBE_UPHY_L5 168 U#define TEGRA234_RESET_GBE_UPHY_L6 169 U#define TEGRA234_RESET_GBE_UPHY_L7 170 U#define TEGRA234_RESET_GBE_UPHY_PLL0 171 U#define TEGRA234_RESET_GBE_UPHY_PLL1 172 U#define TEGRA234_RESET_GBE_UPHY_PLL2 173 U/** @} */ #endif
Messung V0.5 in Prozent C=94 H=95 G=94
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(vorverarbeitet am 2026-06-07)
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