/* SPDX-License-Identifier: GPL-2.0-only */
/*
* This header provides macros for X2000 DMA bindings.
*
* Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
*/
#ifndef __DT_BINDINGS_DMA_X2000_DMA_H__
#define __DT_BINDINGS_DMA_X2000_DMA_H__
/*
* Request type numbers for the X2000 DMA controller (written to the DRTn
* register for the channel).
*/
#define X2000_DMA_AUTO 0 x8
#define X2000_DMA_UART5_TX 0 xa
#define X2000_DMA_UART5_RX 0 xb
#define X2000_DMA_UART4_TX 0 xc
#define X2000_DMA_UART4_RX 0 xd
#define X2000_DMA_UART3_TX 0 xe
#define X2000_DMA_UART3_RX 0 xf
#define X2000_DMA_UART2_TX 0 x10
#define X2000_DMA_UART2_RX 0 x11
#define X2000_DMA_UART1_TX 0 x12
#define X2000_DMA_UART1_RX 0 x13
#define X2000_DMA_UART0_TX 0 x14
#define X2000_DMA_UART0_RX 0 x15
#define X2000_DMA_SSI0_TX 0 x16
#define X2000_DMA_SSI0_RX 0 x17
#define X2000_DMA_SSI1_TX 0 x18
#define X2000_DMA_SSI1_RX 0 x19
#define X2000_DMA_I2C0_TX 0 x24
#define X2000_DMA_I2C0_RX 0 x25
#define X2000_DMA_I2C1_TX 0 x26
#define X2000_DMA_I2C1_RX 0 x27
#define X2000_DMA_I2C2_TX 0 x28
#define X2000_DMA_I2C2_RX 0 x29
#define X2000_DMA_I2C3_TX 0 x2a
#define X2000_DMA_I2C3_RX 0 x2b
#define X2000_DMA_I2C4_TX 0 x2c
#define X2000_DMA_I2C4_RX 0 x2d
#define X2000_DMA_I2C5_TX 0 x2e
#define X2000_DMA_I2C5_RX 0 x2f
#define X2000_DMA_UART6_TX 0 x30
#define X2000_DMA_UART6_RX 0 x31
#define X2000_DMA_UART7_TX 0 x32
#define X2000_DMA_UART7_RX 0 x33
#define X2000_DMA_UART8_TX 0 x34
#define X2000_DMA_UART8_RX 0 x35
#define X2000_DMA_UART9_TX 0 x36
#define X2000_DMA_UART9_RX 0 x37
#define X2000_DMA_SADC_RX 0 x38
#endif /* __DT_BINDINGS_DMA_X2000_DMA_H__ */
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(vorverarbeitet am 2026-06-07)
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