#ifndef __DT_BINDINGS_DMA_JZ4780_DMA_H__
#define __DT_BINDINGS_DMA_JZ4780_DMA_H__
/*
* Request type numbers for the JZ4780 DMA controller (written to the DRTn
* register for the channel).
*/
#define JZ4780_DMA_I2S1_TX 0 x4
#define JZ4780_DMA_I2S1_RX 0 x5
#define JZ4780_DMA_I2S0_TX 0 x6
#define JZ4780_DMA_I2S0_RX 0 x7
#define JZ4780_DMA_AUTO 0 x8
#define JZ4780_DMA_SADC_RX 0 x9
#define JZ4780_DMA_UART4_TX 0 xc
#define JZ4780_DMA_UART4_RX 0 xd
#define JZ4780_DMA_UART3_TX 0 xe
#define JZ4780_DMA_UART3_RX 0 xf
#define JZ4780_DMA_UART2_TX 0 x10
#define JZ4780_DMA_UART2_RX 0 x11
#define JZ4780_DMA_UART1_TX 0 x12
#define JZ4780_DMA_UART1_RX 0 x13
#define JZ4780_DMA_UART0_TX 0 x14
#define JZ4780_DMA_UART0_RX 0 x15
#define JZ4780_DMA_SSI0_TX 0 x16
#define JZ4780_DMA_SSI0_RX 0 x17
#define JZ4780_DMA_SSI1_TX 0 x18
#define JZ4780_DMA_SSI1_RX 0 x19
#define JZ4780_DMA_MSC0_TX 0 x1a
#define JZ4780_DMA_MSC0_RX 0 x1b
#define JZ4780_DMA_MSC1_TX 0 x1c
#define JZ4780_DMA_MSC1_RX 0 x1d
#define JZ4780_DMA_MSC2_TX 0 x1e
#define JZ4780_DMA_MSC2_RX 0 x1f
#define JZ4780_DMA_PCM0_TX 0 x20
#define JZ4780_DMA_PCM0_RX 0 x21
#define JZ4780_DMA_SMB0_TX 0 x24
#define JZ4780_DMA_SMB0_RX 0 x25
#define JZ4780_DMA_SMB1_TX 0 x26
#define JZ4780_DMA_SMB1_RX 0 x27
#define JZ4780_DMA_SMB2_TX 0 x28
#define JZ4780_DMA_SMB2_RX 0 x29
#define JZ4780_DMA_SMB3_TX 0 x2a
#define JZ4780_DMA_SMB3_RX 0 x2b
#define JZ4780_DMA_SMB4_TX 0 x2c
#define JZ4780_DMA_SMB4_RX 0 x2d
#define JZ4780_DMA_DES_TX 0 x2e
#define JZ4780_DMA_DES_RX 0 x2f
#endif /* __DT_BINDINGS_DMA_JZ4780_DMA_H__ */
Messung V0.5 in Prozent C=96 H=95 G=95
¤ Dauer der Verarbeitung: 0.11 Sekunden
(vorverarbeitet am 2026-06-07)
¤
*© Formatika GbR, Deutschland