/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright 2017 Texas Instruments, Inc. #ifndef __DT_BINDINGS_CLK_AM3_H#define __DT_BINDINGS_CLK_AM3_H#define AM3_CLKCTRL_OFFSET 0 x0#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET)/* l4ls clocks */ #define AM3_L4LS_CLKCTRL_OFFSET 0 x38#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET)#define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 x38)#define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 x3c)#define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 x40)#define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 x44)#define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 x48)#define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 x4c)#define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 x50)#define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 x60)#define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 x6c)#define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 x70)#define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 x74)#define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 x78)#define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 x7c)#define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 x80)#define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 x84)#define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 x88)#define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 x90)#define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 xac)#define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 xb0)#define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 xb4)#define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 xc0)#define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 xc4)#define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 xcc)#define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 xd4)#define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 xd8)#define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 xec)#define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 xf0)#define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 xf4)#define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 x10c)#define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 x110)#define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0 x130)/* l3s clocks */ #define AM3_L3S_CLKCTRL_OFFSET 0 x1c#define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET)#define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0 x1c)#define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0 x30)#define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0 x34)#define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0 x68)#define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0 xf8)/* l3 clocks */ #define AM3_L3_CLKCTRL_OFFSET 0 x24#define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET)#define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0 x24)#define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0 x28)#define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0 x2c)#define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0 x94)#define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0 xa0)#define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0 xbc)#define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0 xdc)#define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0 xe0)#define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0 xfc)#define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0 x100)/* l4hs clocks */ #define AM3_L4HS_CLKCTRL_OFFSET 0 x120#define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET)#define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0 x120)/* pruss_ocp clocks */ #define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0 xe8#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET)#define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0 xe8)/* cpsw_125mhz clocks */ #define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0 x14)/* lcdc clocks */ #define AM3_LCDC_CLKCTRL_OFFSET 0 x18#define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET)#define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0 x18)/* clk_24mhz clocks */ #define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0 x14c#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET)#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0 x14c)/* l4_wkup clocks */ #define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0 x4)#define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0 x8)#define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0 xc)#define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0 xb4)#define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0 xb8)#define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0 xbc)#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0 xc0)#define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0 xc4)#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0 xc8)#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0 xd4)/* l3_aon clocks */ #define AM3_L3_AON_CLKCTRL_OFFSET 0 x14#define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET)#define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0 x14)/* l4_wkup_aon clocks */ #define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0 xb0#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET)#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0 xb0)/* mpu clocks */ #define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0 x4)/* l4_rtc clocks */ #define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0 x0)/* gfx_l3 clocks */ #define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0 x4)/* l4_cefuse clocks */ #define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0 x20)#endif
Messung V0.5 in Prozent C=64 H=94 G=80
¤ Dauer der Verarbeitung: 0.11 Sekunden
(vorverarbeitet am 2026-06-08)
¤ *© Formatika GbR, Deutschland
