/** * DOC: Quirk flags for different Samsung watchdog IP-cores * * This driver supports multiple Samsung SoCs, each of which might have * different set of registers and features supported. As watchdog block * sometimes requires modifying PMU registers for proper functioning, register * differences in both watchdog and PMU IP-cores should be accounted for. Quirk * flags described below serve the purpose of telling the driver about mentioned * SoC traits, and can be specified in driver data for each particular supported * device. * * %QUIRK_HAS_WTCLRINT_REG: Watchdog block has WTCLRINT register. It's used to * clear the interrupt once the interrupt service routine is complete. It's * write-only, writing any values to this register clears the interrupt, but * reading is not permitted. * * %QUIRK_HAS_PMU_MASK_RESET: PMU block has the register for disabling/enabling * WDT reset request. On old SoCs it's usually called MASK_WDT_RESET_REQUEST, * new SoCs have CLUSTERx_NONCPU_INT_EN register, which 'mask_bit' value is * inverted compared to the former one. * * %QUIRK_HAS_PMU_RST_STAT: PMU block has RST_STAT (reset status) register, * which contains bits indicating the reason for most recent CPU reset. If * present, driver will use this register to check if previous reboot was due to * watchdog timer reset. * * %QUIRK_HAS_PMU_AUTO_DISABLE: PMU block has AUTOMATIC_WDT_RESET_DISABLE * register. If 'mask_bit' bit is set, PMU will disable WDT reset when * corresponding processor is in reset state. * * %QUIRK_HAS_PMU_CNT_EN: PMU block has some register (e.g. CLUSTERx_NONCPU_OUT) * with "watchdog counter enable" bit. That bit should be set to make watchdog * counter running. * * %QUIRK_HAS_DBGACK_BIT: WTCON register has DBGACK_MASK bit. Setting the * DBGACK_MASK bit disables the watchdog outputs when the SoC is in debug mode. * Debug mode is determined by the DBGACK CPU signal.
*/ #define QUIRK_HAS_WTCLRINT_REG BIT(0) #define QUIRK_HAS_PMU_MASK_RESET BIT(1) #define QUIRK_HAS_PMU_RST_STAT BIT(2) #define QUIRK_HAS_PMU_AUTO_DISABLE BIT(3) #define QUIRK_HAS_PMU_CNT_EN BIT(4) #define QUIRK_HAS_DBGACK_BIT BIT(5)
/* These quirks require that we have a PMU register map */ #define QUIRKS_HAVE_PMUREG \
(QUIRK_HAS_PMU_MASK_RESET | QUIRK_HAS_PMU_RST_STAT | \
QUIRK_HAS_PMU_AUTO_DISABLE | QUIRK_HAS_PMU_CNT_EN)
MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. (default="
__MODULE_STRING(S3C2410_WATCHDOG_DEFAULT_TIME) ")");
MODULE_PARM_DESC(tmr_atboot, "Watchdog is started at boot time if set to 1, default="
__MODULE_STRING(S3C2410_WATCHDOG_ATBOOT));
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default 0)");
/** * struct s3c2410_wdt_variant - Per-variant config data * * @disable_reg: Offset in pmureg for the register that disables the watchdog * timer reset functionality. * @mask_reset_reg: Offset in pmureg for the register that masks the watchdog * timer reset functionality. * @mask_reset_inv: If set, mask_reset_reg value will have inverted meaning. * @mask_bit: Bit number for the watchdog timer in the disable register and the * mask reset register. * @rst_stat_reg: Offset in pmureg for the register that has the reset status. * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog * reset. * @cnt_en_reg: Offset in pmureg for the register that enables WDT counter. * @cnt_en_bit: Bit number for "watchdog counter enable" in cnt_en register. * @quirks: A bitfield of quirks.
*/
struct s3c2410_wdt_variant { int disable_reg; int mask_reset_reg; bool mask_reset_inv; int mask_bit; int rst_stat_reg; int rst_stat_bit; int cnt_en_reg; int cnt_en_bit;
u32 quirks;
};
/* disable watchdog, to be safe */
writel(0, wdt_base + S3C2410_WTCON);
/* put initial values into count and data */
writel(0x80, wdt_base + S3C2410_WTCNT);
writel(0x80, wdt_base + S3C2410_WTDAT);
/* set the watchdog to go and reset... */
writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 |
S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x20),
wdt_base + S3C2410_WTCON);
variant = of_device_get_match_data(dev); if (!variant) { /* Device matched by platform_device_id */
variant = (struct s3c2410_wdt_variant *)
platform_get_device_id(pdev)->driver_data;
}
#ifdef CONFIG_OF /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */ if (variant == &drv_data_exynos850_cl0 ||
variant == &drv_data_exynosautov9_cl0 ||
variant == &drv_data_gs101_cl0 ||
variant == &drv_data_exynosautov920_cl0 ||
variant == &drv_data_exynos990_cl0) {
u32 index; int err;
err = of_property_read_u32(dev->of_node, "samsung,cluster-index", &index); if (err) return dev_err_probe(dev, -EINVAL, "failed to get cluster index\n");
ret = s3c2410_get_wdt_drv_data(pdev, wdt); if (ret) return ret;
if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) {
wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, "samsung,syscon-phandle"); if (IS_ERR(wdt->pmureg)) return dev_err_probe(dev, PTR_ERR(wdt->pmureg), "syscon regmap lookup failed.\n");
}
wdt_irq = platform_get_irq(pdev, 0); if (wdt_irq < 0) return wdt_irq;
/* get the memory region for the watchdog timer */
wdt->reg_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(wdt->reg_base)) return PTR_ERR(wdt->reg_base);
wdt->bus_clk = devm_clk_get_enabled(dev, "watchdog"); if (IS_ERR(wdt->bus_clk)) return dev_err_probe(dev, PTR_ERR(wdt->bus_clk), "failed to get bus clock\n");
/* * "watchdog_src" clock is optional; if it's not present -- just skip it * and use "watchdog" clock as both bus and source clock.
*/
wdt->src_clk = devm_clk_get_optional_enabled(dev, "watchdog_src"); if (IS_ERR(wdt->src_clk)) return dev_err_probe(dev, PTR_ERR(wdt->src_clk), "failed to get source clock\n");
/* see if we can actually set the requested timer margin, and if
* not, try the default value */
watchdog_init_timeout(&wdt->wdt_device, tmr_margin, dev);
ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
wdt->wdt_device.timeout); if (ret) {
ret = s3c2410wdt_set_heartbeat(&wdt->wdt_device,
S3C2410_WATCHDOG_DEFAULT_TIME); if (ret == 0)
dev_warn(dev, "tmr_margin value out of range, default %d used\n",
S3C2410_WATCHDOG_DEFAULT_TIME); else return dev_err_probe(dev, ret, "failed to use default timeout\n");
}
ret = devm_request_irq(dev, wdt_irq, s3c2410wdt_irq, 0,
pdev->name, pdev); if (ret != 0) return dev_err_probe(dev, ret, "failed to install irq (%d)\n", ret);
/* * If "tmr_atboot" param is non-zero, start the watchdog right now. Also * set WDOG_HW_RUNNING bit, so that watchdog core can kick the watchdog. * * If we're not enabling the watchdog, then ensure it is disabled if it * has been left running from the bootloader or other source.
*/ if (tmr_atboot) {
dev_info(dev, "starting watchdog timer\n");
s3c2410wdt_start(&wdt->wdt_device);
set_bit(WDOG_HW_RUNNING, &wdt->wdt_device.status);
} else {
s3c2410wdt_stop(&wdt->wdt_device);
}
ret = devm_watchdog_register_device(dev, &wdt->wdt_device); if (ret) return ret;
ret = s3c2410wdt_enable(wdt, true); if (ret < 0) return ret;
ret = devm_add_action_or_reset(dev, s3c2410wdt_wdt_disable_action, wdt); if (ret) return ret;
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