/* * linux/drivers/video/savagefb.c -- S3 Savage Framebuffer Driver * * Copyright (c) 2001-2002 Denis Oliver Kropp <dok@directfb.org> * Sven Neumann <neo@directfb.org> * * * Card specific code is based on XFree86's savage driver. * Framebuffer framework code is based on code of cyber2000fb and tdfxfb. * * This file is subject to the terms and conditions of the GNU General * Public License. See the file COPYING in the main directory of this * archive for more details. * * 0.4.0 (neo) * - hardware accelerated clear and move * * 0.3.2 (dok) * - wait for vertical retrace before writing to cr67 * at the beginning of savagefb_set_par * - use synchronization registers cr23 and cr26 * * 0.3.1 (dok) * - reset 3D engine * - don't return alpha bits for 32bit format * * 0.3.0 (dok) * - added WaitIdle functions for all Savage types * - do WaitIdle before mode switching * - code cleanup * * 0.2.0 (dok) * - first working version * * * TODO * - clock validations in decode_var * * BUGS * - white margin on bootup * #include <linux/aperture.h>#include <linux/module.h>#include <linux/kernel.h>#include <linux/errno.h>#include <linux/string.h>#include <linux/mm.h>#include <linux/slab.h>#include <linux/delay.h>#include <linux/fb.h>#include <linux/pci.h>#include <linux/init.h>#include <linux/console.h>#include <asm /io.h>#include <asm /irq.h>#include "savagefb.h" #define SAVAGEFB_VERSION "0.4.0_2.6" /* --------------------------------------------------------------------- */ static char *mode_option = NULL;#ifdef MODULE"(c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>" );"GPL" );"FBDev driver for S3 Savage PCI/AGP Chips" );#endif /* --------------------------------------------------------------------- */ static void vgaHWSeqReset(struct savagefb_par *par, int start)if (start)0 x00, 0 x01, par); /* Synchronous Reset */ else 0 x00, 0 x03, par); /* End Reset */ static void vgaHWProtect(struct savagefb_par *par, int on)unsigned char tmp;if (on) {/* * Turn off screen and disable sequencer. 0 x01, par);1 ); /* start synchronous reset */ 0 x01, tmp | 0 x20, par);/* disable the display */ else {/* * Reenable sequencer, then turn on screen. 0 x01, par);0 x01, tmp & ~0 x20, par);/* reenable display */ 0 ); /* clear synchronous reset */ static void vgaHWRestore(struct savagefb_par *par, struct savage_reg *reg)int i;for (i = 1 ; i < 5 ; i++)/* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or 17 , reg->CRTC[17 ] & ~0 x80, par);for (i = 0 ; i < 25 ; i++)for (i = 0 ; i < 9 ; i++)for (i = 0 ; i < 21 ; i++)static void vgaHWInit(struct fb_var_screeninfo *var,struct savagefb_par *par,struct xtimings *timings,struct savage_reg *reg)0 x23;if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT))0 x40;if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT))0 x80;/* * Time Sequencer 0 x00] = 0 x00;0 x01] = 0 x01;0 x02] = 0 x0F;0 x03] = 0 x00; /* Font select */ 0 x04] = 0 x0E; /* Misc */ /* * CRTC Controller 0 x00] = (timings->HTotal >> 3 ) - 5 ;0 x01] = (timings->HDisplay >> 3 ) - 1 ;0 x02] = (timings->HSyncStart >> 3 ) - 1 ;0 x03] = (((timings->HSyncEnd >> 3 ) - 1 ) & 0 x1f) | 0 x80;0 x04] = (timings->HSyncStart >> 3 );0 x05] = ((((timings->HSyncEnd >> 3 ) - 1 ) & 0 x20) << 2 ) |3 )) & 0 x1f);0 x06] = (timings->VTotal - 2 ) & 0 xFF;0 x07] = (((timings->VTotal - 2 ) & 0 x100) >> 8 ) |1 ) & 0 x100) >> 7 ) |0 x100) >> 6 ) |1 ) & 0 x100) >> 5 ) |0 x10 |2 ) & 0 x200) >> 4 ) |1 ) & 0 x200) >> 3 ) |0 x200) >> 2 );0 x08] = 0 x00;0 x09] = (((timings->VSyncStart - 1 ) & 0 x200) >> 4 ) | 0 x40;if (timings->dblscan)0 x09] |= 0 x80;0 x0a] = 0 x00;0 x0b] = 0 x00;0 x0c] = 0 x00;0 x0d] = 0 x00;0 x0e] = 0 x00;0 x0f] = 0 x00;0 x10] = timings->VSyncStart & 0 xff;0 x11] = (timings->VSyncEnd & 0 x0f) | 0 x20;0 x12] = (timings->VDisplay - 1 ) & 0 xff;0 x13] = var->xres_virtual >> 4 ;0 x14] = 0 x00;0 x15] = (timings->VSyncStart - 1 ) & 0 xff;0 x16] = (timings->VSyncEnd - 1 ) & 0 xff;0 x17] = 0 xc3;0 x18] = 0 xff;/* * are these unnecessary? * vgaHWHBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO); * vgaHWVBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO); /* * Graphics Display Controller 0 x00] = 0 x00;0 x01] = 0 x00;0 x02] = 0 x00;0 x03] = 0 x00;0 x04] = 0 x00;0 x05] = 0 x40;0 x06] = 0 x05; /* only map 64k VGA memory !!!! */ 0 x07] = 0 x0F;0 x08] = 0 xFF;0 x00] = 0 x00; /* standard colormap translation */ 0 x01] = 0 x01;0 x02] = 0 x02;0 x03] = 0 x03;0 x04] = 0 x04;0 x05] = 0 x05;0 x06] = 0 x06;0 x07] = 0 x07;0 x08] = 0 x08;0 x09] = 0 x09;0 x0a] = 0 x0A;0 x0b] = 0 x0B;0 x0c] = 0 x0C;0 x0d] = 0 x0D;0 x0e] = 0 x0E;0 x0f] = 0 x0F;0 x10] = 0 x41;0 x11] = 0 xFF;0 x12] = 0 x0F;0 x13] = 0 x00;0 x14] = 0 x00;/* -------------------- Hardware specific routines ------------------------- */ /* * Hardware Acceleration for SavageFB /* Wait for fifo space */ static void struct savagefb_par *par, int space)int slots = MAXFIFO - space;while ((savage_in32(0 x48C00, par) & 0 x0000ffff) > slots);static void struct savagefb_par *par, int space)int slots = MAXFIFO - space;while ((savage_in32(0 x48C60, par) & 0 x001fffff) > slots);static void struct savagefb_par *par, int space)int slots = MAXFIFO - space;while ((savage_in32(0 x48C60, par) & 0 x0000ffff) > slots);/* Wait for idle accelerator */ static void struct savagefb_par *par)while ((savage_in32(0 x48C00, par) & 0 x0008ffff) != 0 x80000);static void struct savagefb_par *par)while ((savage_in32(0 x48C60, par) & 0 x00a00000) != 0 x00a00000);static void struct savagefb_par *par)while ((savage_in32(0 x48C60, par) & 0 x009fffff));#ifdef CONFIG_FB_SAVAGE_ACCELstatic void struct savagefb_par *par)unsigned long GlobalBitmapDescriptor;1 | 8 | BCI_BD_BW_DISABLE;switch (par->chip) {case S3_SAVAGE3D:case S3_SAVAGE_MX:/* Disable BCI */ 0 x48C18, savage_in32(0 x48C18, par) & 0 x3FF0, par);/* Setup BCI command overflow buffer */ 0 x48C14,11 ) | (par->cob_index << 29 ),/* Program shadow status update. */ 0 x48C10, 0 x78207220, par);0 x48C0C, 0 , par);/* Enable BCI and command overflow buffer */ 0 x48C18, savage_in32(0 x48C18, par) | 0 x0C, par);break ;case S3_SAVAGE4:case S3_TWISTER:case S3_PROSAVAGE:case S3_PROSAVAGEDDR:case S3_SUPERSAVAGE:/* Disable BCI */ 0 x48C18, savage_in32(0 x48C18, par) & 0 x3FF0, par);/* Program shadow status update */ 0 x48C10, 0 x00700040, par);0 x48C0C, 0 , par);/* Enable BCI without the COB */ 0 x48C18, savage_in32(0 x48C18, par) | 0 x08, par);break ;case S3_SAVAGE2000:/* Disable BCI */ 0 x48C18, 0 , par);/* Setup BCI command overflow buffer */ 0 x48C18,7 ) | (par->cob_index),/* Disable shadow status update */ 0 x48A30, 0 , par);/* Enable BCI and command overflow buffer */ 0 x48C18, savage_in32(0 x48C18, par) | 0 x00280000,break ;default :break ;/* Turn on 16-bit register access. */ 0 x3d4, 0 x31, par);0 x3d5, 0 x0c, par);/* Set stride to use GBD. */ 0 x3d4, 0 x50, par);0 x3d5, vga_in8(0 x3d5, par) | 0 xC1, par);/* Enable 2D engine. */ 0 x3d4, 0 x40, par);0 x3d5, 0 x01, par);0 , par);0 , par);/* Setup plane masks */ 0 x8128, ~0 , par); /* enable all write planes */ 0 x812C, ~0 , par); /* enable all read planes */ 0 x8134, 0 x27, par);0 x8136, 0 x07, par);/* Now set the GBD */ 0 ;4 );1 << 16 ) | BCI_GBD1);0 );1 << 16 ) | BCI_GBD2);/* * I don't know why, sending this twice fixes the initial black screen, * prevents X from crashing at least in Toshiba laptops with SavageIX. * --Tony 0 ;4 );1 << 16 ) | BCI_GBD1);0 );1 << 16 ) | BCI_GBD2);static void savagefb_set_clip(struct fb_info *info)struct savagefb_par *par = info->par;int cmd;0 ;3 );0 , 0 ));0 xfff, 0 xfff));#else static void SavageSetup2DEngine(struct savagefb_par *par) {}#endif static void SavageCalcClock(long freq, int min_m, int min_n1, int max_n1,int min_n2, int max_n2, long freq_min,long freq_max, unsigned int *mdiv,unsigned int *ndiv, unsigned int *r)long diff, best_diff;unsigned int m;unsigned char n1, n2, best_n1=16 +2 , best_n2=2 , best_m=125 +2 ;if (freq < freq_min / (1 << max_n2)) {"invalid frequency %ld Khz\n" , freq);1 << max_n2);if (freq > freq_max / (1 << min_n2)) {"invalid frequency %ld Khz\n" , freq);1 << min_n2);/* work out suitable timings */ for (n2=min_n2; n2<=max_n2; n2++) {for (n1=min_n1+2 ; n1<=max_n1+2 ; n1++) {1 << n2) + HALF_BASE_FREQ) /if (m < min_m+2 || m > 127 +2 )continue ;if ((m * BASE_FREQ >= freq_min * n1) &&1 << n2) * n1 - BASE_FREQ * m;if (diff < 0 )if (diff < best_diff) {2 ;2 ;static int common_calc_clock(long freq, int min_m, int min_n1, int max_n1,int min_n2, int max_n2, long freq_min,long freq_max, unsigned char *mdiv,unsigned char *ndiv)long diff, best_diff;unsigned int m;unsigned char n1, n2;unsigned char best_n1 = 16 +2 , best_n2 = 2 , best_m = 125 +2 ;for (n2 = min_n2; n2 <= max_n2; n2++) {for (n1 = min_n1+2 ; n1 <= max_n1+2 ; n1++) {1 << n2) + HALF_BASE_FREQ) /if (m < min_m + 2 || m > 127 +2 )continue ;if ((m * BASE_FREQ >= freq_min * n1) &&1 << n2) * n1 - BASE_FREQ * m;if (diff < 0 )if (diff < best_diff) {if (max_n1 == 63 )2 ) | (best_n2 << 6 );else 2 ) | (best_n2 << 5 );2 ;return 0 ;#ifdef SAVAGEFB_DEBUG/* This function is used to debug, it prints out the contents of s3 regs */ static void SavagePrintRegs(struct savagefb_par *par)unsigned char i;int vgaCRIndex = 0 x3d4;int vgaCRReg = 0 x3d5;"SR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE " "xF" );for (i = 0 ; i < 0 x70; i++) {if (!(i % 16 ))"\nSR%xx " , i >> 4 );0 x3c4, i, par);" %02x" , vga_in8(0 x3c5, par));"\n\nCR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC " "xD xE xF" );for (i = 0 ; i < 0 xB7; i++) {if (!(i % 16 ))"\nCR%xx " , i >> 4 );" %02x" , vga_in8(vgaCRReg, par));"\n\n" );#endif /* --------------------------------------------------------------------- */ static void savage_get_default_par(struct savagefb_par *par, struct savage_reg *reg)unsigned char cr3a, cr53, cr66;0 x3d4, 0 x4838, par);0 x3d4, 0 xa039, par);0 x3c4, 0 x0608, par);0 x3d4, 0 x66, par);0 x3d5, par);0 x3d5, cr66 | 0 x80, par);0 x3d4, 0 x3a, par);0 x3d5, par);0 x3d5, cr3a | 0 x80, par);0 x3d4, 0 x53, par);0 x3d5, par);0 x3d5, cr53 & 0 x7f, par);0 x3d4, 0 x66, par);0 x3d5, cr66, par);0 x3d4, 0 x3a, par);0 x3d5, cr3a, par);0 x3d4, 0 x66, par);0 x3d5, cr66, par);0 x3d4, 0 x3a, par);0 x3d5, cr3a, par);/* unlock extended seq regs */ 0 x3c4, 0 x08, par);0 x3c5, par);0 x3c5, 0 x06, par);/* now save all the extended regs we need */ 0 x3d4, 0 x31, par);0 x3d5, par);0 x3d4, 0 x32, par);0 x3d5, par);0 x3d4, 0 x34, par);0 x3d5, par);0 x3d4, 0 x36, par);0 x3d5, par);0 x3d4, 0 x3a, par);0 x3d5, par);0 x3d4, 0 x40, par);0 x3d5, par);0 x3d4, 0 x42, par);0 x3d5, par);0 x3d4, 0 x45, par);0 x3d5, par);0 x3d4, 0 x50, par);0 x3d5, par);0 x3d4, 0 x51, par);0 x3d5, par);0 x3d4, 0 x53, par);0 x3d5, par);0 x3d4, 0 x58, par);0 x3d5, par);0 x3d4, 0 x60, par);0 x3d5, par);0 x3d4, 0 x66, par);0 x3d5, par);0 x3d4, 0 x67, par);0 x3d5, par);0 x3d4, 0 x68, par);0 x3d5, par);0 x3d4, 0 x69, par);0 x3d5, par);0 x3d4, 0 x6f, par);0 x3d5, par);0 x3d4, 0 x33, par);0 x3d5, par);0 x3d4, 0 x86, par);0 x3d5, par);0 x3d4, 0 x88, par);0 x3d5, par);0 x3d4, 0 x90, par);0 x3d5, par);0 x3d4, 0 x91, par);0 x3d5, par);0 x3d4, 0 xb0, par);0 x3d5, par) | 0 x80;/* extended mode timing regs */ 0 x3d4, 0 x3b, par);0 x3d5, par);0 x3d4, 0 x3c, par);0 x3d5, par);0 x3d4, 0 x43, par);0 x3d5, par);0 x3d4, 0 x5d, par);0 x3d5, par);0 x3d4, 0 x5e, par);0 x3d5, par);0 x3d4, 0 x65, par);0 x3d5, par);/* save seq extended regs for DCLK PLL programming */ 0 x3c4, 0 x0e, par);0 x3c5, par);0 x3c4, 0 x0f, par);0 x3c5, par);0 x3c4, 0 x10, par);0 x3c5, par);0 x3c4, 0 x11, par);0 x3c5, par);0 x3c4, 0 x12, par);0 x3c5, par);0 x3c4, 0 x13, par);0 x3c5, par);0 x3c4, 0 x29, par);0 x3c5, par);0 x3c4, 0 x15, par);0 x3c5, par);0 x3c4, 0 x30, par);0 x3c5, par);0 x3c4, 0 x18, par);0 x3c5, par);/* Save flat panel expansion registers. */ if (par->chip == S3_SAVAGE_MX) {int i;for (i = 0 ; i < 8 ; i++) {0 x3c4, 0 x54+i, par);0 x3c5, par);0 x3d4, 0 x66, par);0 x3d5, par);0 x3d5, cr66 | 0 x80, par);0 x3d4, 0 x3a, par);0 x3d5, par);0 x3d5, cr3a | 0 x80, par);/* now save MIU regs */ if (par->chip != S3_SAVAGE_MX) {0 x3d4, 0 x3a, par);0 x3d5, cr3a, par);0 x3d4, 0 x66, par);0 x3d5, cr66, par);static void savage_set_default_par(struct savagefb_par *par,struct savage_reg *reg)unsigned char cr3a, cr53, cr66;0 x3d4, 0 x4838, par);0 x3d4, 0 xa039, par);0 x3c4, 0 x0608, par);0 x3d4, 0 x66, par);0 x3d5, par);0 x3d5, cr66 | 0 x80, par);0 x3d4, 0 x3a, par);0 x3d5, par);0 x3d5, cr3a | 0 x80, par);0 x3d4, 0 x53, par);0 x3d5, par);0 x3d5, cr53 & 0 x7f, par);0 x3d4, 0 x66, par);0 x3d5, cr66, par);0 x3d4, 0 x3a, par);0 x3d5, cr3a, par);0 x3d4, 0 x66, par);0 x3d5, cr66, par);0 x3d4, 0 x3a, par);0 x3d5, cr3a, par);/* unlock extended seq regs */ 0 x3c4, 0 x08, par);0 x3c5, reg->SR08, par);0 x3c5, 0 x06, par);/* now restore all the extended regs we need */ 0 x3d4, 0 x31, par);0 x3d5, reg->CR31, par);0 x3d4, 0 x32, par);0 x3d5, reg->CR32, par);0 x3d4, 0 x34, par);0 x3d5, reg->CR34, par);0 x3d4, 0 x36, par);0 x3d5,reg->CR36, par);0 x3d4, 0 x3a, par);0 x3d5, reg->CR3A, par);0 x3d4, 0 x40, par);0 x3d5, reg->CR40, par);0 x3d4, 0 x42, par);0 x3d5, reg->CR42, par);0 x3d4, 0 x45, par);0 x3d5, reg->CR45, par);0 x3d4, 0 x50, par);0 x3d5, reg->CR50, par);0 x3d4, 0 x51, par);0 x3d5, reg->CR51, par);0 x3d4, 0 x53, par);0 x3d5, reg->CR53, par);0 x3d4, 0 x58, par);0 x3d5, reg->CR58, par);0 x3d4, 0 x60, par);0 x3d5, reg->CR60, par);0 x3d4, 0 x66, par);0 x3d5, reg->CR66, par);0 x3d4, 0 x67, par);0 x3d5, reg->CR67, par);0 x3d4, 0 x68, par);0 x3d5, reg->CR68, par);0 x3d4, 0 x69, par);0 x3d5, reg->CR69, par);0 x3d4, 0 x6f, par);0 x3d5, reg->CR6F, par);0 x3d4, 0 x33, par);0 x3d5, reg->CR33, par);0 x3d4, 0 x86, par);0 x3d5, reg->CR86, par);0 x3d4, 0 x88, par);0 x3d5, reg->CR88, par);0 x3d4, 0 x90, par);0 x3d5, reg->CR90, par);0 x3d4, 0 x91, par);0 x3d5, reg->CR91, par);0 x3d4, 0 xb0, par);0 x3d5, reg->CRB0, par);/* extended mode timing regs */ 0 x3d4, 0 x3b, par);0 x3d5, reg->CR3B, par);0 x3d4, 0 x3c, par);0 x3d5, reg->CR3C, par);0 x3d4, 0 x43, par);0 x3d5, reg->CR43, par);0 x3d4, 0 x5d, par);0 x3d5, reg->CR5D, par);0 x3d4, 0 x5e, par);0 x3d5, reg->CR5E, par);0 x3d4, 0 x65, par);0 x3d5, reg->CR65, par);/* save seq extended regs for DCLK PLL programming */ 0 x3c4, 0 x0e, par);0 x3c5, reg->SR0E, par);0 x3c4, 0 x0f, par);0 x3c5, reg->SR0F, par);0 x3c4, 0 x10, par);0 x3c5, reg->SR10, par);0 x3c4, 0 x11, par);0 x3c5, reg->SR11, par);0 x3c4, 0 x12, par);0 x3c5, reg->SR12, par);0 x3c4, 0 x13, par);0 x3c5, reg->SR13, par);0 x3c4, 0 x29, par);0 x3c5, reg->SR29, par);0 x3c4, 0 x15, par);0 x3c5, reg->SR15, par);0 x3c4, 0 x30, par);0 x3c5, reg->SR30, par);0 x3c4, 0 x18, par);0 x3c5, reg->SR18, par);/* Save flat panel expansion registers. */ if (par->chip == S3_SAVAGE_MX) {int i;for (i = 0 ; i < 8 ; i++) {0 x3c4, 0 x54+i, par);0 x3c5, reg->SR54[i], par);0 x3d4, 0 x66, par);0 x3d5, par);0 x3d5, cr66 | 0 x80, par);0 x3d4, 0 x3a, par);0 x3d5, par);0 x3d5, cr3a | 0 x80, par);/* now save MIU regs */ if (par->chip != S3_SAVAGE_MX) {0 x3d4, 0 x3a, par);0 x3d5, cr3a, par);0 x3d4, 0 x66, par);0 x3d5, cr66, par);static void savage_update_var(struct fb_var_screeninfo *var,const struct fb_videomode *modedb)if (var->yres_virtual < var->yres)0 ;static int savagefb_check_var(struct fb_var_screeninfo *var,struct fb_info *info)struct savagefb_par *par = info->par;int memlen, vramlen, mode_valid = 0 ;"savagefb_check_var" );if (!var->pixclock)return -EINVAL;0 ;0 ;switch (var->bits_per_pixel) {case 8 :0 ;break ;case 16 :11 ;5 ;5 ;6 ;0 ;5 ;break ;case 32 :24 ;8 ;16 ;8 ;8 ;8 ;0 ;8 ;break ;default :return -EINVAL;if (!info->monspecs.hfmax || !info->monspecs.vfmax ||1 ;/* calculate modeline if supported by monitor */ if (!mode_valid && info->monspecs.gtf) {if (!fb_get_mode(FB_MAXTIMINGS, 0 , var, info))1 ;if (!mode_valid) {const struct fb_videomode *mode;if (mode) {1 ;if (!mode_valid && info->monspecs.modedb_len)return -EINVAL;/* Is the mode larger than the LCD panel? */ if (par->SavagePanelWidth &&"Mode (%dx%d) larger than the LCD panel " "(%dx%d)\n" , var->xres, var->yres,return -1 ;if (var->yres_virtual < var->yres)if (var->xres_virtual < var->xres)8 ;if (memlen > vramlen) {8 /8 ;/* we must round yres/xres down, we already rounded y/xres_virtual up if (var->yres_virtual < var->yres)if (var->xres_virtual < var->xres)if (var->xoffset + var->xres > var->xres_virtual)if (var->yoffset + var->yres > var->yres_virtual)return 0 ;static int savagefb_decode_var(struct fb_var_screeninfo *var,struct savagefb_par *par,struct savage_reg *reg)struct xtimings timings;int width, dclk, i, j; /*, refresh; */ unsigned int m, n, r;unsigned char tmp = 0 ;unsigned int pixclock = var->pixclock;"savagefb_decode_var" );0 , sizeof (timings));if (!pixclock) pixclock = 10000 ; /* 10ns = 100MHz */ 1000000000 / pixclock;if (timings.Clock < 1 ) timings.Clock = 1 ;if (var->bits_per_pixel == 16 && par->chip == S3_SAVAGE3D) {2 ;2 ;2 ;2 ;/* * This will allocate the datastructure and initialize all of the * generic VGA registers. /* We need to set CR67 whether or not we use the BIOS. */ 0 x00;switch (var->bits_per_pixel) {case 8 :if ((par->chip == S3_SAVAGE2000) && (dclk >= 230000 ))0 x10; /* 8bpp, 2 pixels/clock */ else 0 x00; /* 8bpp, 1 pixel/clock */ break ;case 15 :if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||230000 )))0 x30; /* 15bpp, 2 pixel/clock */ else 0 x20; /* 15bpp, 1 pixels/clock */ break ;case 16 :if (S3_SAVAGE_MOBILE_SERIES(par->chip) ||230000 )))0 x50; /* 16bpp, 2 pixel/clock */ else 0 x40; /* 16bpp, 1 pixels/clock */ break ;case 24 :0 x70;break ;case 32 :0 xd0;break ;/* * Either BIOS use is disabled, or we failed to find a suitable * match. Fall back to traditional register-crunching. 0 x3d4, 0 x3a, par);0 x3d5, par);if (1 /*FIXME:psav->pci_burst*/) 0 x7f) | 0 x15;else 0 x95;0 x00;0 x8c;0 x89;0 x3d4, 0 x58, par);0 x3d5, par) & 0 x80;0 x13;0 x03 | 0 x80;0 x00;0 x00;0 x3d4, 0 x40, par);0 x3d5, par) & ~0 x01;0 x010400;0 x00;0 x0808;0 x08080810;1 , 1 , 127 , 0 , 4 , 180000 , 360000 , &m, &n, &r);/* m = 107; n = 4; r = 2; */ if (par->MCLK <= 0 ) {255 ;255 ;else {1 , 1 , 31 , 0 , 3 , 135000 , 270000 ,/* reg->SR10 = 80; // MCLK == 286000 */ /* reg->SR11 = 125; */ 6 ) | (n & 0 x3f);0 xff;4 ) | (m & 0 x100) >> 5 | (n & 0 x40) >> 2 ;if (var->bits_per_pixel < 24 )0 x8000;else 0 x4000;if (timings.interlaced)0 x20;else 0 x00;0 x10; /* display fifo */ 3 ) - 5 ) & 0 x100) >> 8 ) |3 ) - 1 ) & 0 x100) >> 7 ) |3 ) - 1 ) & 0 x100) >> 6 ) |0 x800) >> 7 );if ((timings.HSyncEnd >> 3 ) - (timings.HSyncStart >> 3 ) > 64 )0 x08;if ((timings.HSyncEnd >> 3 ) - (timings.HSyncStart >> 3 ) > 32 )0 x20;0 ] + ((i & 0 x01) << 8 ) +4 ] + ((i & 0 x10) << 4 ) + 1 ) / 2 ;if (j - (reg->CRTC[4 ] + ((i & 0 x10) << 4 )) < 4 ) {if (reg->CRTC[4 ] + ((i & 0 x10) << 4 ) + 4 <=0 ] + ((i & 0 x01) << 8 ))4 ] + ((i & 0 x10) << 4 ) + 4 ;else 0 ] + ((i & 0 x01) << 8 ) + 1 ;0 xff;0 x100) >> 2 ;0 ] + ((i & 0 x01) << 8 )) / 2 ;2 ) & 0 x400) >> 10 ) |1 ) & 0 x400) >> 9 ) |0 x400) >> 8 ) |0 x400) >> 6 ) | 0 x40;7 ) / 8 )) >> 3 ;19 ] = 0 xff & width;0 x300 & width) >> 4 ;0 x80 | (width >> 8 );0 x0c;/* Set frame buffer description. */ if (var->bits_per_pixel <= 8 )0 ;else if (var->bits_per_pixel <= 16 )0 x10;else 0 x30;if (var->xres_virtual <= 640 )0 x40;else if (var->xres_virtual == 800 )0 x80;else if (var->xres_virtual == 1024 )0 x00;else if (var->xres_virtual == 1152 )0 x01;else if (var->xres_virtual == 1280 )0 xc0;else if (var->xres_virtual == 1600 )0 x81;else 0 xc1; /* Use GBD */ if (par->chip == S3_SAVAGE2000)0 x08;else 0 x20;0 x17] = 0 xeb;1 ;0 x3d4, 0 x36, par);0 x3d5, par);0 x3d4, 0 x68, par);0 x3d5, par);0 ;0 x3d4, 0 x6f, par);0 x3d5, par);0 x3d4, 0 x86, par);0 x3d5, par);0 x3d4, 0 x88, par);0 x3d5, par) | 0 x08;0 x3d4, 0 xb0, par);0 x3d5, par) | 0 x80;return 0 ;/* --------------------------------------------------------------------- */ /* * Set a single color register. Return != 0 for invalid regno. static int savagefb_setcolreg(unsigned regno,unsigned red,unsigned green,unsigned blue,unsigned transp,struct fb_info *info)struct savagefb_par *par = info->par;if (regno >= NR_PALETTE)return -EINVAL;switch (info->var.bits_per_pixel) {case 8 :0 x3c8, regno, par);0 x3c9, red >> 10 , par);0 x3c9, green >> 10 , par);0 x3c9, blue >> 10 , par);break ;case 16 :if (regno < 16 )0 xf800) ) |0 xfc00) >> 5 ) |0 xf800) >> 11 );break ;case 24 :if (regno < 16 )0 xff00) << 8 ) |0 xff00) ) |0 xff00) >> 8 );break ;case 32 :if (regno < 16 )0 xff00) << 16 ) |0 xff00) << 8 ) |0 xff00) ) |0 xff00) >> 8 );break ;default :return 1 ;return 0 ;static void savagefb_set_par_int(struct savagefb_par *par, struct savage_reg *reg)unsigned char tmp, cr3a, cr66, cr67;"savagefb_set_par_int" );0 x3c2, 0 x23, par);0 x3d4, 0 x4838, par);0 x3d4, 0 xa539, par);0 x3c4, 0 x0608, par);1 );/* * Some Savage/MX and /IX systems go nuts when trying to exit the * server after WindowMaker has displayed a gradient background. I * haven't been able to find what causes it, but a non-destructive * switch to mode 3 here seems to eliminate the issue. 0 x3d4, 0 x67, par);0 x3d5, par);0 x3d5, cr67/*par->CR67*/ & ~0x0c, par); /* no STREAMS yet */ 0 x3d4, 0 x23, par);0 x3d5, 0 x00, par);0 x3d4, 0 x26, par);0 x3d5, 0 x00, par);/* restore extended regs */ 0 x3d4, 0 x66, par);0 x3d5, reg->CR66, par);0 x3d4, 0 x3a, par);0 x3d5, reg->CR3A, par);0 x3d4, 0 x31, par);0 x3d5, reg->CR31, par);0 x3d4, 0 x32, par);0 x3d5, reg->CR32, par);0 x3d4, 0 x58, par);0 x3d5, reg->CR58, par);0 x3d4, 0 x53, par);0 x3d5, reg->CR53 & 0 x7f, par);0 x3c4, 0 x0608, par);/* Restore DCLK registers. */ 0 x3c4, 0 x0e, par);0 x3c5, reg->SR0E, par);0 x3c4, 0 x0f, par);0 x3c5, reg->SR0F, par);0 x3c4, 0 x29, par);0 x3c5, reg->SR29, par);0 x3c4, 0 x15, par);0 x3c5, reg->SR15, par);/* Restore flat panel expansion registers. */ if (par->chip == S3_SAVAGE_MX) {int i;for (i = 0 ; i < 8 ; i++) {0 x3c4, 0 x54+i, par);0 x3c5, reg->SR54[i], par);/* extended mode timing registers */ 0 x3d4, 0 x53, par);0 x3d5, reg->CR53, par);0 x3d4, 0 x5d, par);0 x3d5, reg->CR5D, par);0 x3d4, 0 x5e, par);0 x3d5, reg->CR5E, par);0 x3d4, 0 x3b, par);0 x3d5, reg->CR3B, par);0 x3d4, 0 x3c, par);0 x3d5, reg->CR3C, par);0 x3d4, 0 x43, par);0 x3d5, reg->CR43, par);0 x3d4, 0 x65, par);0 x3d5, reg->CR65, par);/* restore the desired video mode with cr67 */ 0 x3d4, 0 x67, par);/* following part not present in X11 driver */ 0 x3d5, par) & 0 xf;0 x3d5, 0 x50 | cr67, par);10 );0 x3d4, 0 x67, par);/* end of part */ 0 x3d5, reg->CR67 & ~0 x0c, par);/* other mode timing and extended regs */ 0 x3d4, 0 x34, par);0 x3d5, reg->CR34, par);0 x3d4, 0 x40, par);0 x3d5, reg->CR40, par);0 x3d4, 0 x42, par);0 x3d5, reg->CR42, par);0 x3d4, 0 x45, par);0 x3d5, reg->CR45, par);0 x3d4, 0 x50, par);0 x3d5, reg->CR50, par);0 x3d4, 0 x51, par);0 x3d5, reg->CR51, par);/* memory timings */ 0 x3d4, 0 x36, par);0 x3d5, reg->CR36, par);0 x3d4, 0 x60, par);0 x3d5, reg->CR60, par);0 x3d4, 0 x68, par);0 x3d5, reg->CR68, par);0 x3d4, 0 x69, par);0 x3d5, reg->CR69, par);0 x3d4, 0 x6f, par);0 x3d5, reg->CR6F, par);0 x3d4, 0 x33, par);0 x3d5, reg->CR33, par);0 x3d4, 0 x86, par);0 x3d5, reg->CR86, par);0 x3d4, 0 x88, par);0 x3d5, reg->CR88, par);0 x3d4, 0 x90, par);0 x3d5, reg->CR90, par);0 x3d4, 0 x91, par);0 x3d5, reg->CR91, par);if (par->chip == S3_SAVAGE4) {0 x3d4, 0 xb0, par);0 x3d5, reg->CRB0, par);0 x3d4, 0 x32, par);0 x3d5, reg->CR32, par);/* unlock extended seq regs */ 0 x3c4, 0 x08, par);0 x3c5, 0 x06, par);/* Restore extended sequencer regs for MCLK. SR10 == 255 indicates * that we should leave the default SR10 and SR11 values there. if (reg->SR10 != 255 ) {0 x3c4, 0 x10, par);0 x3c5, reg->SR10, par);0 x3c4, 0 x11, par);0 x3c5, reg->SR11, par);/* restore extended seq regs for dclk */ 0 x3c4, 0 x0e, par);0 x3c5, reg->SR0E, par);0 x3c4, 0 x0f, par);0 x3c5, reg->SR0F, par);0 x3c4, 0 x12, par);0 x3c5, reg->SR12, par);0 x3c4, 0 x13, par);0 x3c5, reg->SR13, par);0 x3c4, 0 x29, par);0 x3c5, reg->SR29, par);0 x3c4, 0 x18, par);0 x3c5, reg->SR18, par);/* load new m, n pll values for dclk & mclk */ 0 x3c4, 0 x15, par);0 x3c5, par) & ~0 x21;0 x3c5, tmp | 0 x03, par);0 x3c5, tmp | 0 x23, par);0 x3c5, tmp | 0 x03, par);0 x3c5, reg->SR15, par);100 );0 x3c4, 0 x30, par);0 x3c5, reg->SR30, par);0 x3c4, 0 x08, par);0 x3c5, reg->SR08, par);/* now write out cr67 in full, possibly starting STREAMS */ 0 x3d4, 0 x67, par);0 x3d5, reg->CR67, par);0 x3d4, 0 x66, par);0 x3d5, par);0 x3d5, cr66 | 0 x80, par);0 x3d4, 0 x3a, par);0 x3d5, par);0 x3d5, cr3a | 0 x80, par);if (par->chip != S3_SAVAGE_MX) {0 x3d4, 0 x66, par);0 x3d5, cr66, par);0 x3d4, 0 x3a, par);0 x3d5, cr3a, par);0 );static void savagefb_update_start(struct savagefb_par *par, int base)/* program the start address registers */ 0 x3d4, (base & 0 x00ff00) | 0 x0c, par);0 x3d4, ((base & 0 x00ff) << 8 ) | 0 x0d, par);0 x3d4, 0 x69, par);0 x3d5, (base & 0 x7f0000) >> 16 , par);static void savagefb_set_fix(struct fb_info *info)8 ;if (info->var.bits_per_pixel == 8 ) {4 ;else {2 ;static int savagefb_set_par(struct fb_info *info)struct savagefb_par *par = info->par;struct fb_var_screeninfo *var = &info->var;int err;"savagefb_set_par" );if (err)return err;if (par->dacSpeedBpp <= 0 ) {if (var->bits_per_pixel > 24 )3 ];else if (var->bits_per_pixel >= 24 )2 ];else if ((var->bits_per_pixel > 8 ) && (var->bits_per_pixel < 24 ))1 ];else if (var->bits_per_pixel <= 8 )0 ];/* Set ramdac limits */ 10000 ;return 0 ;/* * Pan or Wrap the Display static int savagefb_pan_display(struct fb_var_screeninfo *var,struct fb_info *info)struct savagefb_par *par = info->par;int base;1 ) * ((info->var.bits_per_pixel+7 ) / 8 )) >> 2 ;return 0 ;static int savagefb_blank(int blank, struct fb_info *info)struct savagefb_par *par = info->par;0 , srd = 0 ;if (par->display_type == DISP_CRT) {0 x3c4, 0 x08, par);0 x3c5, par);0 x06;0 x3c5, sr8, par);0 x3c4, 0 x0d, par);0 x3c5, par);0 x50;switch (blank) {case FB_BLANK_UNBLANK:case FB_BLANK_NORMAL:break ;case FB_BLANK_VSYNC_SUSPEND:0 x10;break ;case FB_BLANK_HSYNC_SUSPEND:0 x40;break ;case FB_BLANK_POWERDOWN:0 x50;break ;0 x3c4, 0 x0d, par);0 x3c5, srd, par);if (par->display_type == DISP_LCD ||switch (blank) {case FB_BLANK_UNBLANK:case FB_BLANK_NORMAL:0 x3c4, 0 x31, par); /* SR31 bit 4 - FP enable */ 0 x3c5, vga_in8(0 x3c5, par) | 0 x10, par);break ;case FB_BLANK_VSYNC_SUSPEND:case FB_BLANK_HSYNC_SUSPEND:case FB_BLANK_POWERDOWN:0 x3c4, 0 x31, par); /* SR31 bit 4 - FP enable */ 0 x3c5, vga_in8(0 x3c5, par) & ~0 x10, par);break ;return (blank == FB_BLANK_NORMAL) ? 1 : 0 ;static int savagefb_open(struct fb_info *info, int user)struct savagefb_par *par = info->par;if (!par->open_count) {0 , sizeof (par->vgastate));0 x8000;return 0 ;static int savagefb_release(struct fb_info *info, int user)struct savagefb_par *par = info->par;if (par->open_count == 1 ) {return 0 ;static const struct fb_ops savagefb_ops = {#if defined (CONFIG_FB_SAVAGE_ACCEL)#else #endif /* --------------------------------------------------------------------- */ static const struct fb_var_screeninfo savagefb_var800x600x8 = {800 ,600 ,800 ,600 ,8 ,25000 ,88 ,40 ,23 ,1 ,128 ,4 ,static void savage_enable_mmio(struct savagefb_par *par)unsigned char val;"savage_enable_mmio\n" );0 x3c3, par);0 x3c3, val | 0 x01, par);0 x3cc, par);0 x3c2, val | 0 x01, par);if (par->chip >= S3_SAVAGE4) {0 x3d4, 0 x40, par);0 x3d5, par);0 x3d5, val | 1 , par);static void savage_disable_mmio(struct savagefb_par *par)unsigned char val;"savage_disable_mmio\n" );if (par->chip >= S3_SAVAGE4) {0 x3d4, 0 x40, par);0 x3d5, par);0 x3d5, val | 1 , par);static int savage_map_mmio(struct fb_info *info)struct savagefb_par *par = info->par;"savage_map_mmio" );if (S3_SAVAGE3D_SERIES(par->chip))0 ) +else 0 ) +if (!par->mmio.vbase) {"savagefb: unable to map memory mapped IO\n" );return -ENOMEM;else "savagefb: mapped io at %p\n" ,0 ;return 0 ;static void savage_unmap_mmio(struct fb_info *info)struct savagefb_par *par = info->par;"savage_unmap_mmio" );if (par->mmio.vbase) {static int savage_map_video(struct fb_info *info, int video_len)struct savagefb_par *par = info->par;int resource;"savage_map_video" );if (S3_SAVAGE3D_SERIES(par->chip))0 ;else 1 ;if (!par->video.vbase) {"savagefb: unable to map screen memory\n" );return -ENOMEM;else "savagefb: mapped framebuffer at %p, " "pbase == %x\n" , par->video.vbase, par->video.pbase);/* Clear framebuffer, it's all white in memory after boot */ 0 , par->video.len);return 0 ;static void savage_unmap_video(struct fb_info *info)struct savagefb_par *par = info->par;"savage_unmap_video" );if (par->video.vbase) {static int savage_init_hw(struct savagefb_par *par)unsigned char config1, m, n, n1, n2, sr8, cr3f, cr66 = 0 , tmp;static unsigned char RamSavage3D[] = { 8 , 4 , 4 , 2 };static unsigned char RamSavage4[] = { 2 , 4 , 8 , 12 , 16 , 32 , 64 , 32 };static unsigned char RamSavageMX[] = { 2 , 8 , 4 , 16 , 8 , 16 , 4 , 16 };static unsigned char RamSavageNB[] = { 0 , 2 , 4 , 8 , 16 , 32 , 2 , 2 };int videoRam, videoRambytes, dvi;"savage_init_hw" );/* unprotect CRTC[0-7] */ 0 x3d4, 0 x11, par);0 x3d5, par);0 x3d5, tmp & 0 x7f, par);/* unlock extended regs */ 0 x3d4, 0 x4838, par);0 x3d4, 0 xa039, par);0 x3c4, 0 x0608, par);0 x3d4, 0 x40, par);0 x3d5, par);0 x3d5, tmp & ~0 x01, par);/* unlock sys regs */ 0 x3d4, 0 x38, par);0 x3d5, 0 x48, par);/* Unlock system registers. */ 0 x3d4, 0 x4838, par);/* Next go on to detect amount of installed ram */ 0 x3d4, 0 x36, par); /* for register CR36 (CONFG_REG1), */ 0 x3d5, par); /* get amount of vram installed */ /* Compute the amount of video memory and offscreen memory. */ switch (par->chip) {case S3_SAVAGE3D:0 xC0) >> 6 ] * 1024 ;break ;case S3_SAVAGE4:/* * The Savage4 has one ugly special case to consider. On * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB * when it really means 8MB. Why do it the same when you * can do it different... 0 x3d4, 0 x68, par); /* memory control 1 */ if ((vga_in8(0 x3d5, par) & 0 xC0) == (0 x01 << 6 ))1 ] = 8 ;case S3_SAVAGE2000:0 xE0) >> 5 ] * 1024 ;break ;case S3_SAVAGE_MX:case S3_SUPERSAVAGE:0 x0E) >> 1 ] * 1024 ;break ;case S3_PROSAVAGE:case S3_PROSAVAGEDDR:case S3_TWISTER:0 xE0) >> 5 ] * 1024 ;break ;default :/* How did we get here? */ 0 ;break ;1024 ;"savagefb: probed videoram: %dk\n" , videoRam);/* reset graphics engine to avoid memory corruption */ 0 x3d4, 0 x66, par);0 x3d5, par);0 x3d5, cr66 | 0 x02, par);10000 , 11000 );0 x3d4, 0 x66, par);0 x3d5, cr66 & ~0 x02, par); /* clear reset flag */ 10000 , 11000 );/* * reset memory interface, 3D engine, AGP master, PCI master, * master engine unit, motion compensation/LPB 0 x3d4, 0 x3f, par);0 x3d5, par);0 x3d5, cr3f | 0 x08, par);10000 , 11000 );0 x3d4, 0 x3f, par);0 x3d5, cr3f & ~0 x08, par); /* clear reset flags */ 10000 , 11000 );/* Savage ramdac speeds */ 4 ;0 ] = 250000 ;1 ] = 250000 ;2 ] = 220000 ;3 ] = 220000 ;/* detect current mclk */ 0 x3c4, 0 x08, par);0 x3c5, par);0 x3c5, 0 x06, par);0 x3c4, 0 x10, par);0 x3c5, par);0 x3c4, 0 x11, par);0 x3c5, par);0 x3c4, 0 x08, par);0 x3c5, sr8, par);0 x7f;0 x1f;5 ) & 0 x03;1431818 * (m+2 )) / (n1+2 ) / (1 << n2) + 50 ) / 100 ;"savagefb: Detected current MCLK value of %d kHz\n" ,/* check for DVI/flat panel */ 0 ;if (par->chip == S3_SAVAGE4) {unsigned char sr30 = 0 x00;0 x3c4, 0 x30, par);/* clear bit 1 */ 0 x3c5, vga_in8(0 x3c5, par) & ~0 x02, par);0 x3c5, par);if (sr30 & 0 x02 /*0x04 */) { 1 ;"savagefb: Digital Flat Panel Detected\n" );if ((S3_SAVAGE_MOBILE_SERIES(par->chip) ||else if (dvi || (par->chip == S3_SAVAGE4 && par->dvi))else /* Check LCD panel parrmation */ if (par->display_type == DISP_LCD) {unsigned char cr6b = VGArCR(0 x6b, par);int panelX = (VGArSEQ(0 x61, par) +0 x66, par) & 0 x02) << 7 ) + 1 ) * 8 ;int panelY = (VGArSEQ(0 x69, par) +0 x6e, par) & 0 x70) << 4 ) + 1 );char * sTechnology = "Unknown" ;/* OK, I admit it. I don't know how to limit the max dot clock * for LCD panels of various sizes. I thought I copied the * formula from the BIOS, but many users have parrmed me of * my folly. * * Instead, I'll abandon any attempt to automatically limit the * clock, and add an LCDClock option to XF86Config. Some day, * I should come back to this. enum ACTIVE_DISPLAYS { /* These are the bits in CR6B */ 0 x01,0 x02,0 x04,0 x20,0 x80if ((VGArSEQ(0 x39, par) & 0 x03) == 0 ) {"TFT" ;else if ((VGArSEQ(0 x30, par) & 0 x01) == 0 ) {"DSTN" ;else {"STN" ;"savagefb: %dx%d %s LCD panel detected %s\n" ,"and active" : "but not active" );if (cr6b & ActiveLCD) {/* * If the LCD is active and panel expansion is enabled, * we probably want to kill the HW cursor. "savagefb: Limiting video mode to " "%dx%d\n" , panelX, panelY);else if (S3_SAVAGE4_SERIES(par->chip)) {/* * The Savage4 and ProSavage have COB coherency bugs which * render the buffer useless. We disable it. 2 ;0 x8000 << par->cob_index;else {/* We use 128kB for the COB on all chips. */ 7 ;0 x400 << par->cob_index;return videoRambytes;static int savage_init_fb_info(struct fb_info *info, struct pci_dev *dev,const struct pci_device_id *id)struct savagefb_par *par = info->par;int err = 0 ;0 ;1 ;0 ;switch (info->fix.accel) {case FB_ACCEL_SUPERSAVAGE:16 , "SuperSavage" );break ;case FB_ACCEL_SAVAGE4:16 , "Savage4" );break ;case FB_ACCEL_SAVAGE3D:16 , "Savage3D" );break ;case FB_ACCEL_SAVAGE3D_MV:16 , "Savage3D-MV" );break ;case FB_ACCEL_SAVAGE2000:16 , "Savage2000" );break ;case FB_ACCEL_SAVAGE_MX_MV:16 , "Savage/MX-MV" );break ;case FB_ACCEL_SAVAGE_MX:16 , "Savage/MX" );break ;case FB_ACCEL_SAVAGE_IX_MV:16 , "Savage/IX-MV" );break ;case FB_ACCEL_SAVAGE_IX:16 , "Savage/IX" );break ;case FB_ACCEL_PROSAVAGE_PM:16 , "ProSavagePM" );break ;case FB_ACCEL_PROSAVAGE_KM:16 , "ProSavageKM" );break ;case FB_ACCEL_S3TWISTER_P:16 , "TwisterP" );break ;case FB_ACCEL_S3TWISTER_K:16 , "TwisterK" );break ;case FB_ACCEL_PROSAVAGE_DDR:16 , "ProSavageDDR" );break ;case FB_ACCEL_PROSAVAGE_DDRK:16 , "ProSavage8" );break ;if (S3_SAVAGE3D_SERIES(par->chip)) {else if (S3_SAVAGE4_SERIES(par->chip) ||else {0 ;1 ;1 ;0 ;#if defined (CONFIG_FB_SAVAGE_ACCEL)/* FIFO size + padding for commands */ 8 , 1024 , GFP_KERNEL);if (info->pixmap.addr) {8 *1024 ;4 ;4 ;32 ;0 );if (!err)else #endif return err;/* --------------------------------------------------------------------- */ static int savagefb_probe(struct pci_dev *dev, const struct pci_device_id *id)struct fb_info *info;struct savagefb_par *par;unsigned char __maybe_unused *edid;int err, lpitch;int video_len;"savagefb_probe" );"savagefb" );if (err)return err;sizeof (struct savagefb_par), &dev->dev);if (!info)return -ENOMEM;if (err)goto failed_enable;if ((err = pci_request_regions(dev, "savagefb" ))) {"cannot request PCI regions\n" );goto failed_enable;if ((err = savage_init_fb_info(info, dev, id)))goto failed_init;if (err)goto failed_mmio;/* FIXME: can't be negative */ if (video_len < 0 ) {goto failed_mmio;if (err)goto failed_video;#if defined (CONFIG_FB_SAVAGE_I2C)#endif /* if a panel was detected, default to a CVT mode instead */ if (par->SavagePanelWidth) {struct fb_videomode cvt_mode;0 , sizeof (cvt_mode));60 ;/* FIXME: if we know there is only the panel if (fb_find_mode_cvt(&cvt_mode, 0 , 0 ))"No CVT mode found for panel\n" );else if (fb_find_mode(&info->var, info, NULL, NULL, 0 ,0 ) != 3 )if (mode_option) {8 );else if (info->monspecs.modedb != NULL) {const struct fb_videomode *mode;/* maximize virtual vertical length */ 7 ) >> 3 );if (info->var.yres_virtual < info->var.yres) {goto failed;#if defined (CONFIG_FB_SAVAGE_ACCEL)/* * The clipping coordinates are masked with 0xFFF, so limit our * virtual resolutions to these sizes. if (info->var.yres_virtual > 0 x1000)0 x1000;if (info->var.xres_virtual > 0 x1000)0 x1000;#endif if (err)goto failed;/* * Calculate the hsync and vsync frequencies. Note that * we split the 1e12 constant up so that we can preserve * the precision and fit the results into 32-bit registers. * (1953125000 * 512 = 1e12) 1953125000 / info->var.pixclock;512 / (info->var.xres + info->var.left_margin +"savagefb v" SAVAGEFB_VERSION ": " "%dkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n" ,10 ,1000 , h_sync % 1000 , v_sync);if (err < 0 )goto failed;"fb: S3 %s frame buffer device\n" ,/* * Our driver data return 0 ;#ifdef CONFIG_FB_SAVAGE_I2C#endif 0 , 0 );return err;static void savagefb_remove(struct pci_dev *dev)struct fb_info *info = pci_get_drvdata(dev);"savagefb_remove" );if (info) {#ifdef CONFIG_FB_SAVAGE_I2C#endif 0 , 0 );static int savagefb_suspend_late(struct device *dev, pm_message_t mesg)struct fb_info *info = dev_get_drvdata(dev);struct savagefb_par *par = info->par;"savagefb_suspend" );if (mesg.event == PM_EVENT_PRETHAW)/* * For PM_EVENT_FREEZE, do not power down so the console * can remain active. if (mesg.event == PM_EVENT_FREEZE)return 0 ;1 );if (info->fbops->fb_sync)return 0 ;static int __maybe_unused savagefb_suspend(struct device *dev)return savagefb_suspend_late(dev, PMSG_SUSPEND);static int __maybe_unused savagefb_hibernate(struct device *dev)return savagefb_suspend_late(dev, PMSG_HIBERNATE);static int __maybe_unused savagefb_freeze(struct device *dev)return savagefb_suspend_late(dev, PMSG_FREEZE);static int __maybe_unused savagefb_resume(struct device *dev)struct fb_info *info = dev_get_drvdata(dev);struct savagefb_par *par = info->par;int cur_state = par->pm_state;"savage_resume" );/* * The adapter was not powered down coming back from a * PM_EVENT_FREEZE. if (cur_state == PM_EVENT_FREEZE)return 0 ;0 );return 0 ;static const struct dev_pm_ops savagefb_pm_ops = {#ifdef CONFIG_PM_SLEEP#endif static const struct pci_device_id savagefb_devices[] = {0 , 0 , FB_ACCEL_SUPERSAVAGE},0 , 0 , FB_ACCEL_SUPERSAVAGE},0 , 0 , FB_ACCEL_SUPERSAVAGE},0 , 0 , FB_ACCEL_SUPERSAVAGE},0 , 0 , FB_ACCEL_SUPERSAVAGE},0 , 0 , FB_ACCEL_SUPERSAVAGE},0 , 0 , FB_ACCEL_SUPERSAVAGE},0 , 0 , FB_ACCEL_SUPERSAVAGE},0 , 0 , FB_ACCEL_SUPERSAVAGE},0 , 0 , FB_ACCEL_SAVAGE4},0 , 0 , FB_ACCEL_SAVAGE3D},0 , 0 , FB_ACCEL_SAVAGE3D_MV},0 , 0 , FB_ACCEL_SAVAGE2000},0 , 0 , FB_ACCEL_SAVAGE_MX_MV},0 , 0 , FB_ACCEL_SAVAGE_MX},0 , 0 , FB_ACCEL_SAVAGE_IX_MV},0 , 0 , FB_ACCEL_SAVAGE_IX},0 , 0 , FB_ACCEL_PROSAVAGE_PM},0 , 0 , FB_ACCEL_PROSAVAGE_KM},0 , 0 , FB_ACCEL_S3TWISTER_P},0 , 0 , FB_ACCEL_S3TWISTER_K},0 , 0 , FB_ACCEL_PROSAVAGE_DDR},0 , 0 , FB_ACCEL_PROSAVAGE_DDRK},0 , 0 , 0 , 0 , 0 , 0 , 0 }static struct pci_driver savagefb_driver = {"savagefb" ,/* **************************** exit-time only **************************** */ static void __exit savage_done(void )"savage_done" );/* ************************* init in-kernel code ************************** */ static int __init savagefb_setup(char *options)#ifndef MODULEchar *this_opt;if (!options || !*options)return 0 ;while ((this_opt = strsep(&options, "," )) != NULL) {#endif /* !MODULE */ return 0 ;static int __init savagefb_init(void )char *option;"savagefb_init" );if (fb_modesetting_disabled("savagefb" ))return -ENODEV;if (fb_get_options("savagefb" , &option))return -ENODEV;return pci_register_driver(&savagefb_driver);0 );"Specify initial video mode" );
Messung V0.5 in Prozent C=95 H=92 G=93
¤ Dauer der Verarbeitung: 0.51 Sekunden
(vorverarbeitet am 2026-06-07)
¤ *© Formatika GbR, Deutschland
