// SPDX-License-Identifier: GPL-2.0 /* * Probe module for 8250/16550-type PCI serial ports. * * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. * * Copyright (C) 2001 Russell King, All Rights Reserved. #undef DEBUG#include <linux/module.h>#include <linux/pci.h>#include <linux/string.h>#include <linux/kernel.h>#include <linux/math.h>#include <linux/slab.h>#include <linux/delay.h>#include <linux/tty.h>#include <linux/serial_reg.h>#include <linux/serial_core.h>#include <linux/8250 _pci.h>#include <linux/bitops.h>#include <linux/bitfield.h>#include <asm /byteorder.h>#include <asm /io.h>#include "8250.h" #include "8250_pcilib.h" #define PCI_VENDOR_ID_SBSMODULARIO 0 x124B#define PCI_SUBVENDOR_ID_SBSMODULARIO 0 x124B#define PCI_DEVICE_ID_OCTPRO 0 x0001#define PCI_SUBDEVICE_ID_OCTPRO232 0 x0108#define PCI_SUBDEVICE_ID_OCTPRO422 0 x0208#define PCI_SUBDEVICE_ID_POCTAL232 0 x0308#define PCI_SUBDEVICE_ID_POCTAL422 0 x0408#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0 x2500#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0 x2530#define PCI_VENDOR_ID_ADVANTECH 0 x13fe#define PCI_DEVICE_ID_INTEL_CE4100_UART 0 x2e66#define PCI_DEVICE_ID_ADVANTECH_PCI1600 0 x1600#define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0 x1611#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0 x3620#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0 x3618#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0 xf618#define PCI_DEVICE_ID_TITAN_200I 0 x8028#define PCI_DEVICE_ID_TITAN_400I 0 x8048#define PCI_DEVICE_ID_TITAN_800I 0 x8088#define PCI_DEVICE_ID_TITAN_800EH 0 xA007#define PCI_DEVICE_ID_TITAN_800EHB 0 xA008#define PCI_DEVICE_ID_TITAN_400EH 0 xA009#define PCI_DEVICE_ID_TITAN_100E 0 xA010#define PCI_DEVICE_ID_TITAN_200E 0 xA012#define PCI_DEVICE_ID_TITAN_400E 0 xA013#define PCI_DEVICE_ID_TITAN_800E 0 xA014#define PCI_DEVICE_ID_TITAN_200EI 0 xA016#define PCI_DEVICE_ID_TITAN_200EISI 0 xA017#define PCI_DEVICE_ID_TITAN_200V3 0 xA306#define PCI_DEVICE_ID_TITAN_400V3 0 xA310#define PCI_DEVICE_ID_TITAN_410V3 0 xA312#define PCI_DEVICE_ID_TITAN_800V3 0 xA314#define PCI_DEVICE_ID_TITAN_800V3B 0 xA315#define PCI_DEVICE_ID_OXSEMI_16PCI958 0 x9538#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0 x00F6#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0 xc001#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0 x1d3d#define PCI_DEVICE_ID_WCHCN_CH352_2S 0 x3253#define PCI_DEVICE_ID_WCHCN_CH355_4S 0 x7173#define PCI_VENDOR_ID_AGESTAR 0 x5372#define PCI_DEVICE_ID_AGESTAR_9375 0 x6872#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0 x160a#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0 x818e#define PCI_DEVICE_ID_WCHIC_CH384_4S 0 x3470#define PCI_DEVICE_ID_WCHIC_CH384_8S 0 x3853#define PCI_DEVICE_ID_MOXA_CP102E 0 x1024#define PCI_DEVICE_ID_MOXA_CP102EL 0 x1025#define PCI_DEVICE_ID_MOXA_CP102N 0 x1027#define PCI_DEVICE_ID_MOXA_CP104EL_A 0 x1045#define PCI_DEVICE_ID_MOXA_CP104N 0 x1046#define PCI_DEVICE_ID_MOXA_CP112N 0 x1121#define PCI_DEVICE_ID_MOXA_CP114EL 0 x1144#define PCI_DEVICE_ID_MOXA_CP114N 0 x1145#define PCI_DEVICE_ID_MOXA_CP116E_A_A 0 x1160#define PCI_DEVICE_ID_MOXA_CP116E_A_B 0 x1161#define PCI_DEVICE_ID_MOXA_CP118EL_A 0 x1182#define PCI_DEVICE_ID_MOXA_CP118E_A_I 0 x1183#define PCI_DEVICE_ID_MOXA_CP132EL 0 x1322#define PCI_DEVICE_ID_MOXA_CP132N 0 x1323#define PCI_DEVICE_ID_MOXA_CP134EL_A 0 x1342#define PCI_DEVICE_ID_MOXA_CP134N 0 x1343#define PCI_DEVICE_ID_MOXA_CP138E_A 0 x1381#define PCI_DEVICE_ID_MOXA_CP168EL_A 0 x1683/* Unknown vendors/cards - this should not be in linux/pci_ids.h */ #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0 x1584#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0 x1588/* * init function returns: * > 0 - number of ports * = 0 - use board->num_ports * < 0 - error struct pci_serial_quirk {int (*probe)(struct pci_dev *dev);int (*init)(struct pci_dev *dev);int (*setup)(struct serial_private *,const struct pciserial_board *,struct uart_8250_port *, int );void (*exit )(struct pci_dev *dev);struct f815xxa_data {int idx;struct serial_private {struct pci_dev *dev;unsigned int nr;struct pci_serial_quirk *quirk;const struct pciserial_board *board;int line[];#define PCI_DEVICE_ID_HPE_PCI_SERIAL 0 x37estatic const struct pci_device_id pci_use_msi[] = {0 xA000, 0 x1000) },0 xA000, 0 x1000) },0 xA000, 0 x1000) },0 xA000, 0 x1000) },static int pci_default_setup(struct serial_private*,const struct pciserial_board*, struct uart_8250_port *, int );static void moan_device(const char *str, struct pci_dev *dev)"%s\n" "Please send the output of lspci -vv, this\n" "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" "manufacturer and name of serial board or\n" "modem board to <linux-serial@vger.kernel.org>.\n" ,static int struct serial_private *priv, struct uart_8250_port *port,unsigned int offset, int regshift)return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift);/* * ADDI-DATA GmbH communication cards <info@addi-data.com> static int addidata_apci7800_setup(struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)unsigned int bar = 0 , offset = board->first_offset;if (idx < 2 ) {else if ((idx >= 2 ) && (idx < 4 )) {1 ;2 ) * board->uart_offset);else if ((idx >= 4 ) && (idx < 6 )) {2 ;4 ) * board->uart_offset);else if (idx >= 6 ) {3 ;6 ) * board->uart_offset);return setup_port(priv, port, bar, offset, board->reg_shift);/* * AFAVLAB uses a different mixture of BARs and offsets * Not that ugly ;) -- HW static int struct serial_private *priv, const struct pciserial_board *board,struct uart_8250_port *port, int idx)unsigned int bar, offset = board->first_offset;if (idx < 4 )else {4 ;4 ) * board->uart_offset;return setup_port(priv, port, bar, offset, board->reg_shift);/* * HP's Remote Management Console. The Diva chip came in several * different versions. N-class, L2000 and A500 have two Diva chips, each * with 3 UARTs (the third UART on the second chip is unused). Superdome * and Keystone have one Diva chip with 3 UARTs. Some later machines have * one Diva chip, but it has been expanded to 5 UARTs. static int pci_hp_diva_init(struct pci_dev *dev)int rc = 0 ;switch (dev->subsystem_device) {case PCI_DEVICE_ID_HP_DIVA_TOSCA1:case PCI_DEVICE_ID_HP_DIVA_HALFDOME:case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:case PCI_DEVICE_ID_HP_DIVA_EVEREST:3 ;break ;case PCI_DEVICE_ID_HP_DIVA_TOSCA2:2 ;break ;case PCI_DEVICE_ID_HP_DIVA_MAESTRO:4 ;break ;case PCI_DEVICE_ID_HP_DIVA_POWERBAR:case PCI_DEVICE_ID_HP_DIVA_HURRICANE:1 ;break ;return rc;/* * HP's Diva chip puts the 4th/5th serial port further out, and * some serial ports are supposed to be hidden on certain models. static int struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)unsigned int offset = board->first_offset;unsigned int bar = FL_GET_BASE(board->flags);switch (priv->dev->subsystem_device) {case PCI_DEVICE_ID_HP_DIVA_MAESTRO:if (idx == 3 )break ;case PCI_DEVICE_ID_HP_DIVA_EVEREST:if (idx > 0 )if (idx > 2 )break ;if (idx > 2 )0 x18;return setup_port(priv, port, bar, offset, board->reg_shift);/* * Added for EKF Intel i960 serial boards static int pci_inteli960ni_init(struct pci_dev *dev)if (!(dev->subsystem_device & 0 x1000))return -ENODEV;/* is firmware started? */ 0 x44, &oldval);if (oldval == 0 x00001000L) { /* RESET value */ "Local i960 firmware missing\n" );return -ENODEV;return 0 ;/* * Some PCI serial cards using the PLX 9050 PCI interface chip require * that the card interrupt be explicitly enabled or disabled. This * seems to be mainly needed on card using the PLX which also use I/O * mapped memory. static int pci_plx9050_init(struct pci_dev *dev)void __iomem *p;if ((pci_resource_flags(dev, 0 ) & IORESOURCE_MEM) == 0 ) {"no memory in bar 0" , dev);return 0 ;0 x41;if (dev->vendor == PCI_VENDOR_ID_PANACOM ||0 x43;if ((dev->vendor == PCI_VENDOR_ID_PLX) &&/* * As the megawolf cards have the int pins active * high, and have 2 UART chips, both ints must be * enabled on the 9050. Also, the UARTS are set in * 16450 mode by default, so we have to enable the * 16C950 'enhanced' mode so that we can use the * deep FIFOs 0 x5b;/* * enable/disable interrupts 0 ), 0 x80);if (p == NULL)return -ENOMEM;0 x4c);/* * Read the register back to ensure that it took effect. 0 x4c);return 0 ;static void pci_plx9050_exit(struct pci_dev *dev)if ((pci_resource_flags(dev, 0 ) & IORESOURCE_MEM) == 0 )return ;/* * disable interrupts 0 ), 0 x80);if (p != NULL) {0 , p + 0 x4c);/* * Read the register back to ensure that it took effect. 0 x4c);#define NI8420_INT_ENABLE_REG 0 x38#define NI8420_INT_ENABLE_BIT 0 x2000static void pci_ni8420_exit(struct pci_dev *dev)void __iomem *p;unsigned int bar = 0 ;if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0 ) {"no memory in bar" , dev);return ;if (p == NULL)return ;/* Disable the CPU Interrupt */ /* MITE registers */ #define MITE_IOWBSR1 0 xc4#define MITE_IOWCR1 0 xf4#define MITE_LCIMR1 0 x08#define MITE_LCIMR2 0 x10#define MITE_LCIMR2_CLR_CPU_IE (1 << 30 )static void pci_ni8430_exit(struct pci_dev *dev)void __iomem *p;unsigned int bar = 0 ;if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0 ) {"no memory in bar" , dev);return ;if (p == NULL)return ;/* Disable the CPU Interrupt */ /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ static int struct serial_private *priv, const struct pciserial_board *board,struct uart_8250_port *port, int idx)unsigned int bar, offset = board->first_offset;0 ;if (idx < 4 ) {/* first four channels map to 0, 0x100, 0x200, 0x300 */ else if (idx < 8 ) {/* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 0 xC00;else /* we have only 8 ports on PMC-OCTALPRO */ return 1 ;return setup_port(priv, port, bar, offset, board->reg_shift);/** This does initialization for PMC OCTALPRO cards: * maps the device memory, resets the UARTs (needed, bc * if the module is removed and inserted again, the card * is in the sleep mode) and enables global interrupt. /* global control register offset for SBS PMC-OctalPro */ #define OCT_REG_CR_OFF 0 x500static int sbs_init(struct pci_dev *dev)0 );if (p == NULL)return -ENOMEM;/* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 0 x10, p + OCT_REG_CR_OFF);50 );0 x0, p + OCT_REG_CR_OFF);/* Set bit-2 (INTENABLE) of Control Register */ 0 x4, p + OCT_REG_CR_OFF);return 0 ;/* * Disables the global interrupt of PMC-OctalPro static void sbs_exit(struct pci_dev *dev)0 );/* FIXME: What if resource_len < OCT_REG_CR_OFF */ if (p != NULL)0 , p + OCT_REG_CR_OFF);/* * SIIG serial cards have an PCI interface chip which also controls * the UART clocking frequency. Each UART can be clocked independently * (except cards equipped with 4 UARTs) and initial clocking settings * are stored in the EEPROM chip. It can cause problems because this * version of serial driver doesn't support differently clocked UART's * on single PCI card. To prevent this, initialization functions set * high frequency clocking for all UART's on given card. It is safe (I * hope) because it doesn't touch EEPROM settings to prevent conflicts * with other OSes (like M$ DOS). * * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 * * There is two family of SIIG serial cards with different PCI * interface chip and different configuration methods: * - 10x cards have control registers in IO and/or memory space; * - 20x cards have control registers in standard PCI configuration space. * * Note: all 10x cards have PCI device ids 0x10.. * all 20x cards have PCI device ids 0x20.. * * There are also Quartet Serial cards which use Oxford Semiconductor * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. * * Note: some SIIG cards are probed by the parport_serial object. #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0 xfffc)#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0 xfff8)static int pci_siig10x_init(struct pci_dev *dev)void __iomem *p;switch (dev->device & 0 xfff8) {case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 0 xffdf;break ;case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 0 xf7ff;break ;default : /* 1S1P, 4S */ 0 xfffb;break ;0 ), 0 x80);if (p == NULL)return -ENOMEM;0 x28) & data, p + 0 x28);0 x28);return 0 ;#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0 xfffc)#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0 xfffc)static int pci_siig20x_init(struct pci_dev *dev)/* Change clock frequency for the first UART. */ 0 x6f, &data);0 x6f, data & 0 xef);/* If this card has 2 UART, we have to do the same with second UART. */ if (((dev->device & 0 xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||0 xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {0 x73, &data);0 x73, data & 0 xef);return 0 ;static int pci_siig_init(struct pci_dev *dev)unsigned int type = dev->device & 0 xff00;if (type == 0 x1000)return pci_siig10x_init(dev);if (type == 0 x2000)return pci_siig20x_init(dev);"Unknown SIIG card" , dev);return -ENODEV;static int pci_siig_setup(struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0 ;if (idx > 3 ) {4 ;4 ) * 8 ;return setup_port(priv, port, bar, offset, 0 );/* * Timedia has an explosion of boards, and to avoid the PCI table from * growing *huge*, we use this function to collapse some 70 entries * in the PCI table into one, for sanity's and compactness's sake. static const unsigned short timedia_single_port[] = {0 x4025, 0 x4027, 0 x4028, 0 x5025, 0 x5027, 0 static const unsigned short timedia_dual_port[] = {0 x0002, 0 x4036, 0 x4037, 0 x4038, 0 x4078, 0 x4079, 0 x4085,0 x4088, 0 x4089, 0 x5037, 0 x5078, 0 x5079, 0 x5085, 0 x6079,0 x7079, 0 x8079, 0 x8137, 0 x8138, 0 x8237, 0 x8238, 0 x9079,0 x9137, 0 x9138, 0 x9237, 0 x9238, 0 xA079, 0 xB079, 0 xC079,0 xD079, 0 static const unsigned short timedia_quad_port[] = {0 x4055, 0 x4056, 0 x4095, 0 x4096, 0 x5056, 0 x8156, 0 x8157,0 x8256, 0 x8257, 0 x9056, 0 x9156, 0 x9157, 0 x9158, 0 x9159,0 x9256, 0 x9257, 0 xA056, 0 xA157, 0 xA158, 0 xA159, 0 xB056,0 xB157, 0 static const unsigned short timedia_eight_port[] = {0 x4065, 0 x4066, 0 x5065, 0 x5066, 0 x8166, 0 x9066, 0 x9166,0 x9167, 0 x9168, 0 xA066, 0 xA167, 0 xA168, 0 static const struct timedia_struct {int num;const unsigned short *ids;1 , timedia_single_port },2 , timedia_dual_port },4 , timedia_quad_port },8 , timedia_eight_port }/* * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of * listing them individually, this driver merely grabs them all with * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, * and should be left free to be claimed by parport_serial instead. static int pci_timedia_probe(struct pci_dev *dev)/* * Check the third digit of the subdevice ID * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) if ((dev->subsystem_device & 0 x00f0) >= 0 x70) {"ignoring Timedia subdevice %04x for parport_serial\n" ,return -ENODEV;return 0 ;static int pci_timedia_init(struct pci_dev *dev)const unsigned short *ids;int i, j;for (i = 0 ; i < ARRAY_SIZE(timedia_data); i++) {for (j = 0 ; ids[j]; j++)if (dev->subsystem_device == ids[j])return timedia_data[i].num;return 0 ;/* * Timedia/SUNIX uses a mixture of BARs and offsets * Ugh, this is ugly as all hell --- TYT static int struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)unsigned int bar = 0 , offset = board->first_offset;switch (idx) {case 0 :0 ;break ;case 1 :0 ;break ;case 2 :1 ;break ;case 3 :case 4 : /* BAR 2 */ case 5 : /* BAR 3 */ case 6 : /* BAR 4 */ case 7 : /* BAR 5 */ 2 ;return setup_port(priv, port, bar, offset, board->reg_shift);/* * Some Titan cards are also a little weird static int struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)unsigned int bar, offset = board->first_offset;switch (idx) {case 0 :1 ;break ;case 1 :2 ;break ;default :4 ;2 ) * board->uart_offset;return setup_port(priv, port, bar, offset, board->reg_shift);static int pci_xircom_init(struct pci_dev *dev)100 );return 0 ;static int pci_ni8420_init(struct pci_dev *dev)void __iomem *p;unsigned int bar = 0 ;if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0 ) {"no memory in bar" , dev);return 0 ;if (p == NULL)return -ENOMEM;/* Enable CPU Interrupt */ return 0 ;#define MITE_IOWBSR1_WSIZE 0 xa#define MITE_IOWBSR1_WIN_OFFSET 0 x800#define MITE_IOWBSR1_WENAB (1 << 7 )#define MITE_LCIMR1_IO_IE_0 (1 << 24 )#define MITE_LCIMR2_SET_CPU_IE (1 << 31 )#define MITE_IOWCR1_RAMSEL_MASK 0 xfffffffestatic int pci_ni8430_init(struct pci_dev *dev)void __iomem *p;struct pci_bus_region region;unsigned int bar = 0 ;if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0 ) {"no memory in bar" , dev);return 0 ;if (p == NULL)return -ENOMEM;/* * Set device window address and size in BAR0, while acknowledging that * the resource structure may contain a translated address that differs * from the address the device responds to. 0 xffffff00)/* Set window access to go to RAMSEL IO address space */ /* Enable IO Bus Interrupt 0 */ /* Enable CPU Interrupt */ return 0 ;/* UART Port Control Register */ #define NI8430_PORTCON 0 x0f#define NI8430_PORTCON_TXVR_ENABLE (1 << 3 )static int struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)struct pci_dev *dev = priv->dev;void __iomem *p;unsigned int bar, offset = board->first_offset;if (idx >= board->num_ports)return 1 ;if (!p)return -ENOMEM;/* enable the transceiver */ return setup_port(priv, port, bar, offset, board->reg_shift);static int pci_netmos_9900_setup(struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)unsigned int bar;if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&0 xff00) == 0 x3000) {/* netmos apparently orders BARs by datasheet layout, so serial * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 3 * idx;return setup_port(priv, port, bar, 0 , board->reg_shift);return pci_default_setup(priv, board, port, idx);/* the 99xx series comes with a range of device IDs and a variety * of capabilities: * * 9900 has varying capabilities and can cascade to sub-controllers * (cascading should be purely internal) * 9904 is hardwired with 4 serial ports * 9912 and 9922 are hardwired with 2 serial ports static int pci_netmos_9900_numports(struct pci_dev *dev)unsigned int c = dev->class ;unsigned int pi;unsigned short sub_serports;0 xff;if (pi == 2 )return 1 ;if ((pi == 0 ) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {/* two possibilities: 0x30ps encodes number of parallel and * serial ports, or 0x1000 indicates *something*. This is not * immediately obvious, since the 2s1p+4s configuration seems * to offer all functionality on functions 0..2, while still * advertising the same function 3 as the 4s+2s1p config. 0 xf;if (sub_serports > 0 )return sub_serports;"NetMos/Mostech serial driver ignoring port on ambiguous config.\n" );return 0 ;"unknown NetMos/Mostech program interface" , dev);return 0 ;static int pci_netmos_init(struct pci_dev *dev)/* subdevice 0x00PS means <P> parallel, <S> serial */ unsigned int num_serial = dev->subsystem_device & 0 xf;if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||return 0 ;if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&0 x0299)return 0 ;switch (dev->device) { /* FALLTHROUGH on all */ case PCI_DEVICE_ID_NETMOS_9904:case PCI_DEVICE_ID_NETMOS_9912:case PCI_DEVICE_ID_NETMOS_9922:case PCI_DEVICE_ID_NETMOS_9900:break ;default :break ;if (num_serial == 0 ) {"unknown NetMos/Mostech device" , dev);return -ENODEV;return num_serial;/* * These chips are available with optionally one parallel port and up to * two serial ports. Unfortunately they all have the same product id. * * Basic configuration is done over a region of 32 I/O ports. The base * ioport is called INTA or INTC, depending on docs/other drivers. * * The region of the 32 I/O ports is configured in POSIO0R... /* registers */ #define ITE_887x_MISCR 0 x9c#define ITE_887x_INTCBAR 0 x78#define ITE_887x_UARTBAR 0 x7c#define ITE_887x_PS0BAR 0 x10#define ITE_887x_POSIO0 0 x60/* I/O space size */ #define ITE_887x_IOSIZE 32 /* I/O space size (bits 26-24; 8 bytes = 011b) */ #define ITE_887x_POSIO_IOSIZE_8 (3 << 24 )/* I/O space size (bits 26-24; 32 bytes = 101b) */ #define ITE_887x_POSIO_IOSIZE_32 (5 << 24 )/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ #define ITE_887x_POSIO_SPEED (3 << 29 )/* enable IO_Space bit */ #define ITE_887x_POSIO_ENABLE (1 << 31 )/* inta_addr are the configuration addresses of the ITE */ static const short inta_addr[] = { 0 x2a0, 0 x2c0, 0 x220, 0 x240, 0 x1e0, 0 x200, 0 x280 };static int pci_ite887x_init(struct pci_dev *dev)int ret, i, type;struct resource *iobase = NULL;if (!IS_ENABLED(CONFIG_HAS_IOPORT))return serial_8250_warn_need_ioport(dev);/* search for the base-ioport */ for (i = 0 ; i < ARRAY_SIZE(inta_addr); i++) {"ite887x" );if (iobase != NULL) {/* write POSIO0R - speed | size | ioport */ /* write INTCBAR - ioport */ if (ret != 0 xff) {/* ioport connected */ break ;if (i == ARRAY_SIZE(inta_addr)) {"could not find iobase\n" );return -ENODEV;/* start of undocumented type checking (see parport_pc.c) */ 0 x18) & 0 x0f;switch (type) {case 0 x2: /* ITE8871 (1P) */ case 0 xa: /* ITE8875 (1P) */ 0 ;break ;case 0 xe: /* ITE8872 (2S1P) */ 2 ;break ;case 0 x6: /* ITE8873 (1S) */ 1 ;break ;case 0 x8: /* ITE8874 (2S) */ 2 ;break ;default :"Unknown ITE887x" , dev);/* configure all serial ports */ for (i = 0 ; i < ret; i++) {/* read the I/O port from the device */ 0 x4 * (i + 1 )),0 x0000FF00; /* the actual base address */ 0 x4 * (i + 1 )),/* write the ioport to the UARTBAR */ 0 xffff << (16 * i)); /* clear half the reg */ 16 * i)); /* set the ioport */ /* get current config */ /* disable interrupts (UARTx_Routing[3:0]) */ 0 xf << (12 - 4 * i));/* activate the UART (UARTx_En) */ 1 << (23 - i);/* write new config with activated UART */ if (ret <= 0 ) {/* the device has no UARTs if we get here */ return ret;static void pci_ite887x_exit(struct pci_dev *dev)/* the ioport is bit 0-15 in POSIO0R */ 0 xffff;/* * Oxford Semiconductor Inc. * Check if an OxSemi device is part of the Tornado range of devices. #define PCI_VENDOR_ID_ENDRUN 0 x7401#define PCI_DEVICE_ID_ENDRUN_1588 0 xe100static bool pci_oxsemi_tornado_p(struct pci_dev *dev)/* OxSemi Tornado devices are all 0xCxxx */ if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&0 xf000) != 0 xc000)return false ;/* EndRun devices are all 0xExxx */ if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&0 xf000) != 0 xe000)return false ;return true ;/* * Determine the number of ports available on a Tornado device. static int pci_oxsemi_tornado_init(struct pci_dev *dev)unsigned long deviceID;unsigned int number_uarts = 0 ;if (!pci_oxsemi_tornado_p(dev))return 0 ;0 , 5 );if (p == NULL)return -ENOMEM;/* Tornado device */ if (deviceID == 0 x07000200) {4 );"%d ports detected on %s PCI Express device\n" ,"EndRun" : "Oxford" );return number_uarts;/* Tornado-specific constants for the TCR and CPR registers; see below. */ #define OXSEMI_TORNADO_TCR_MASK 0 xf#define OXSEMI_TORNADO_CPR_MASK 0 x1ff#define OXSEMI_TORNADO_CPR_MIN 0 x008#define OXSEMI_TORNADO_CPR_DEF 0 x10f/* * Determine the oversampling rate, the clock prescaler, and the clock * divisor for the requested baud rate. The clock rate is 62.5 MHz, * which is four times the baud base, and the prescaler increments in * steps of 1/8. Therefore to make calculations on integers we need * to use a scaled clock rate, which is the baud base multiplied by 32 * (or our assumed UART clock rate multiplied by 2). * * The allowed oversampling rates are from 4 up to 16 inclusive (values * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows * values between 1.000 and 63.875 inclusive (operation for values from * 0.000 to 0.875 has not been specified). The clock divisor is the usual * unsigned 16-bit integer. * * For the most accurate baud rate we use a table of predetermined * oversampling rates and clock prescalers that records all possible * products of the two parameters in the range from 4 up to 255 inclusive, * and additionally 335 for the 1500000bps rate, with the prescaler scaled * by 8. The table is sorted by the decreasing value of the oversampling * rate and ties are resolved by sorting by the decreasing value of the * product. This way preference is given to higher oversampling rates. * * We iterate over the table and choose the product of an oversampling * rate and a clock prescaler that gives the lowest integer division * result deviation, or if an exact integer divider is found we stop * looking for it right away. We do some fixup if the resulting clock * divisor required would be out of its unsigned 16-bit integer range. * * Finally we abuse the supposed fractional part returned to encode the * 4-bit value of the oversampling rate and the 9-bit value of the clock * prescaler which will end up in the TCR and CPR/CPR2 registers. static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port,unsigned int baud,unsigned int *frac)static u8 p[][2 ] = {16 , 14 , }, { 16 , 13 , }, { 16 , 12 , }, { 16 , 11 , },16 , 10 , }, { 16 , 9 , }, { 16 , 8 , }, { 15 , 17 , },15 , 16 , }, { 15 , 15 , }, { 15 , 14 , }, { 15 , 13 , },15 , 12 , }, { 15 , 11 , }, { 15 , 10 , }, { 15 , 9 , },15 , 8 , }, { 14 , 18 , }, { 14 , 17 , }, { 14 , 14 , },14 , 13 , }, { 14 , 12 , }, { 14 , 11 , }, { 14 , 10 , },14 , 9 , }, { 14 , 8 , }, { 13 , 19 , }, { 13 , 18 , },13 , 17 , }, { 13 , 13 , }, { 13 , 12 , }, { 13 , 11 , },13 , 10 , }, { 13 , 9 , }, { 13 , 8 , }, { 12 , 19 , },12 , 18 , }, { 12 , 17 , }, { 12 , 11 , }, { 12 , 9 , },12 , 8 , }, { 11 , 23 , }, { 11 , 22 , }, { 11 , 21 , },11 , 20 , }, { 11 , 19 , }, { 11 , 18 , }, { 11 , 17 , },11 , 11 , }, { 11 , 10 , }, { 11 , 9 , }, { 11 , 8 , },10 , 25 , }, { 10 , 23 , }, { 10 , 20 , }, { 10 , 19 , },10 , 17 , }, { 10 , 10 , }, { 10 , 9 , }, { 10 , 8 , },9 , 27 , }, { 9 , 23 , }, { 9 , 21 , }, { 9 , 19 , },9 , 18 , }, { 9 , 17 , }, { 9 , 9 , }, { 9 , 8 , },8 , 31 , }, { 8 , 29 , }, { 8 , 23 , }, { 8 , 19 , },8 , 17 , }, { 8 , 8 , }, { 7 , 35 , }, { 7 , 31 , },7 , 29 , }, { 7 , 25 , }, { 7 , 23 , }, { 7 , 21 , },7 , 19 , }, { 7 , 17 , }, { 7 , 15 , }, { 7 , 14 , },7 , 13 , }, { 7 , 12 , }, { 7 , 11 , }, { 7 , 10 , },7 , 9 , }, { 7 , 8 , }, { 6 , 41 , }, { 6 , 37 , },6 , 31 , }, { 6 , 29 , }, { 6 , 23 , }, { 6 , 19 , },6 , 17 , }, { 6 , 13 , }, { 6 , 11 , }, { 6 , 10 , },6 , 9 , }, { 6 , 8 , }, { 5 , 67 , }, { 5 , 47 , },5 , 43 , }, { 5 , 41 , }, { 5 , 37 , }, { 5 , 31 , },5 , 29 , }, { 5 , 25 , }, { 5 , 23 , }, { 5 , 19 , },5 , 17 , }, { 5 , 15 , }, { 5 , 13 , }, { 5 , 11 , },5 , 10 , }, { 5 , 9 , }, { 5 , 8 , }, { 4 , 61 , },4 , 59 , }, { 4 , 53 , }, { 4 , 47 , }, { 4 , 43 , },4 , 41 , }, { 4 , 37 , }, { 4 , 31 , }, { 4 , 29 , },4 , 23 , }, { 4 , 19 , }, { 4 , 17 , }, { 4 , 13 , },4 , 9 , }, { 4 , 8 , },/* Scale the quotient for comparison to get the fractional part. */ const unsigned int quot_scale = 65536 ;unsigned int sclk = port->uartclk * 2 ;unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud);unsigned int best_squot;unsigned int squot;unsigned int quot;int i;/* Old custom speed handling. */ if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {unsigned int cust_div = port->custom_divisor;16 ) & OXSEMI_TORNADO_TCR_MASK;20 ) & OXSEMI_TORNADO_CPR_MASK;if (cpr < OXSEMI_TORNADO_CPR_MIN)else {for (i = 0 ; i < ARRAY_SIZE(p); i++) {unsigned int spre;unsigned int srem;0 ];1 ];if (srem > spre / 2 )if (srem == 0 ) {break ;else if (squot < best_squot) {while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1 ) >> 1 &&2 == 0 ) {1 ;1 ;while (quot > UART_DIV_MAX) {if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1 ) >> 1 ) {1 ;1 ;else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1 ) {1 ;1 ;else {8 ) | (tcr & OXSEMI_TORNADO_TCR_MASK);return quot;/* * Set the oversampling rate in the transmitter clock cycle register (TCR), * the clock prescaler in the clock prescaler register (CPR and CPR2), and * the clock divisor in the divisor latch (DLL and DLM). Note that for * backwards compatibility any write to CPR clears CPR2 and therefore CPR * has to be written first, followed by CPR2, which occupies the location * of CKS used with earlier UART designs. static void pci_oxsemi_tornado_set_divisor(struct uart_port *port,unsigned int baud,unsigned int quot,unsigned int quot_frac)struct uart_8250_port *up = up_to_u8250p(port);16 ;8 ;/* * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used. static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port,unsigned int mctrl)struct uart_8250_port *up = up_to_u8250p(port);/* * We require EFR features for clock programming, so set UPF_FULL_PROBE * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting. static int pci_oxsemi_tornado_setup(struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *up, int idx)struct pci_dev *dev = priv->dev;if (pci_oxsemi_tornado_p(dev)) {return pci_default_setup(priv, board, up, idx);#define QPCR_TEST_FOR1 0 x3F#define QPCR_TEST_GET1 0 x00#define QPCR_TEST_FOR2 0 x40#define QPCR_TEST_GET2 0 x40#define QPCR_TEST_FOR3 0 x80#define QPCR_TEST_GET3 0 x40#define QPCR_TEST_FOR4 0 xC0#define QPCR_TEST_GET4 0 x80#define QOPR_CLOCK_X1 0 x0000#define QOPR_CLOCK_X2 0 x0001#define QOPR_CLOCK_X4 0 x0002#define QOPR_CLOCK_X8 0 x0003#define QOPR_CLOCK_RATE_MASK 0 x0003/* Quatech devices have their own extra interface features */ static struct pci_device_id quatech_cards[] = {1 ) },1 ) },0 ) },1 ) },0 ) },1 ) },1 ) },1 ) },1 ) },1 ) },1 ) },0 ) },0 ) },0 ) },0 ) },0 ) },0 ) },0 ) },0 ) },0 , }static int pci_quatech_rqopr(struct uart_8250_port *port)unsigned long base = port->port.iobase;0 xBF, base + UART_LCR);return val;static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)unsigned long base = port->port.iobase;0 xBF, base + UART_LCR);static int pci_quatech_rqmcr(struct uart_8250_port *port)unsigned long base = port->port.iobase;0 xBF, base + UART_LCR);0 x10, base + UART_SCR);return qmcr;static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)unsigned long base = port->port.iobase;0 xBF, base + UART_LCR);0 x10, base + UART_SCR);static int pci_quatech_has_qmcr(struct uart_8250_port *port)unsigned long base = port->port.iobase;0 xBF, base + UART_LCR);if (val & 0 x20) {0 x80, UART_LCR);if (!(inb(UART_SCR) & 0 x20)) {return 1 ;return 0 ;static int pci_quatech_test(struct uart_8250_port *port)0 xC0;if (reg != QPCR_TEST_GET1)return -EINVAL;0 xC0;if (reg != QPCR_TEST_GET2)return -EINVAL;0 xC0;if (reg != QPCR_TEST_GET3)return -EINVAL;0 xC0;if (reg != QPCR_TEST_GET4)return -EINVAL;return 0 ;static int pci_quatech_clock(struct uart_8250_port *port)unsigned long clock;if (pci_quatech_test(port) < 0 )return 1843200 ;if (reg & QOPR_CLOCK_X8) {1843200 ;goto out;if (!(reg & QOPR_CLOCK_X8)) {1843200 ;goto out;if (reg == QOPR_CLOCK_X2) {3685400 ;else if (reg == QOPR_CLOCK_X4) {7372800 ;else if (reg == QOPR_CLOCK_X8) {14745600 ;else {1843200 ;return clock;static int pci_quatech_rs422(struct uart_8250_port *port)int rs422 = 0 ;if (!pci_quatech_has_qmcr(port))return 0 ;0 xFF);if (pci_quatech_rqmcr(port))1 ;return rs422;static int pci_quatech_init(struct pci_dev *dev)const struct pci_device_id *match;bool amcc = false ;if (!IS_ENABLED(CONFIG_HAS_IOPORT))return serial_8250_warn_need_ioport(dev);if (match)else "unknown port type '0x%04X'.\n" , dev->device);if (amcc) {unsigned long base = pci_resource_start(dev, 0 );if (base) {0 x38) | 0 x00002000, base + 0 x38);0 x3c);0 x01000000, base + 0 x3c);0 x01000000, base + 0 x3c);return 0 ;static int pci_quatech_setup(struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)if (!IS_ENABLED(CONFIG_HAS_IOPORT))return serial_8250_warn_need_ioport(priv->dev);/* Needed by pci_quatech calls below */ /* Set up the clocking */ /* For now just warn about RS422 */ if (pci_quatech_rs422(port))"software control of RS422 features not currently supported.\n" );return pci_default_setup(priv, board, port, idx);static int pci_default_setup(struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)unsigned int bar, offset = board->first_offset, maxnr;if (board->flags & FL_BASE_BARS)else 3 );if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)return 1 ;return setup_port(priv, port, bar, offset, board->reg_shift);static int struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)int ret;0 , board->reg_shift);2 ;return ret;static int struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)return setup_port(priv, port, 2 , idx * 8 , 0 );static int struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)int ret = pci_default_setup(priv, board, port, idx);return ret;/* RTS will control by MCR if this bit is 0 */ #define FINTEK_RTS_CONTROL_BY_HW BIT(4 )/* only worked with FINTEK_RTS_CONTROL_BY_HW on */ #define FINTEK_RTS_INVERT BIT(5 )/* We should do proper H/W transceiver setting before change to RS485 mode */ static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios,struct serial_rs485 *rs485)struct pci_dev *pci_dev = to_pci_dev(port->dev);0 x40 + 8 * *index + 7 , &setting);if (rs485->flags & SER_RS485_ENABLED) {/* Enable RTS H/W control mode */ if (rs485->flags & SER_RS485_RTS_ON_SEND) {/* RTS driving high on TX */ else {/* RTS driving low on TX */ else {/* Disable RTS H/W control mode */ 0 x40 + 8 * *index + 7 , setting);return 0 ;static const struct serial_rs485 pci_fintek_rs485_supported = {/* F81504/508/512 does not support RTS delay before or after send */ static int pci_fintek_setup(struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)struct pci_dev *pdev = priv->dev;if (!IS_ENABLED(CONFIG_HAS_IOPORT))return serial_8250_warn_need_ioport(pdev);0 x40 + 0 x08 * idx;/* Get the io address from configuration space */ 4 , &iobase);"idx=%d iobase=0x%x" , idx, iobase);sizeof (u8), GFP_KERNEL);if (!data)return -ENOMEM;/* preserve index in PCI configuration space */ return 0 ;static int pci_fintek_init(struct pci_dev *dev)unsigned long iobase;3 ];struct serial_private *priv = pci_get_drvdata(dev);if (!IS_ENABLED(CONFIG_HAS_IOPORT))return serial_8250_warn_need_ioport(dev);if (!(pci_resource_flags(dev, 5 ) & IORESOURCE_IO) ||4 ) & IORESOURCE_IO) ||3 ) & IORESOURCE_IO))return -ENODEV;switch (dev->device) {case 0 x1104: /* 4 ports */ case 0 x1108: /* 8 ports */ 0 xff;break ;case 0 x1112: /* 12 ports */ 12 ;break ;default :return -EINVAL;/* Get the io address dispatch from the BIOS */ 0 ] = pci_resource_start(dev, 5 );1 ] = pci_resource_start(dev, 4 );2 ] = pci_resource_start(dev, 3 );for (i = 0 ; i < max_port; ++i) {/* UART0 configuration offset start from 0x40 */ 0 x40 + 0 x08 * i;/* Calculate Real IO Port */ 4 ] & 0 xffffffe0) + (i % 4 ) * 8 ;/* Enable UART I/O port */ 0 x00, 0 x01);/* Select 128-byte FIFO and 8x FIFO threshold */ 0 x01, 0 x33);/* LSB UART */ 0 x04,0 xff));/* MSB UART */ 0 x05,0 xff00) >> 8 ));0 x06, dev->irq);if (!priv) {/* First init without port data * force init to RS232 Mode 0 x07, 0 x01);return max_port;static void f815xxa_mem_serial_out(struct uart_port *p, unsigned int offset, u32 value)struct f815xxa_data *data = p->private_data;unsigned long flags;/* Dummy read for flush pcie tx queue */ static int pci_fintek_f815xxa_setup(struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)struct pci_dev *pdev = priv->dev;struct f815xxa_data *data;sizeof (*data), GFP_KERNEL);if (!data)return -ENOMEM;0 ) + 8 * idx;return 0 ;static int pci_fintek_f815xxa_init(struct pci_dev *dev)int config_base;if (!(pci_resource_flags(dev, 0 ) & IORESOURCE_MEM))return -ENODEV;switch (dev->device) {case 0 x1204: /* 4 ports */ case 0 x1208: /* 8 ports */ 0 xff;break ;case 0 x1212: /* 12 ports */ 12 ;break ;default :return -EINVAL;/* Set to mmio decode */ 0 x209, 0 x40);for (i = 0 ; i < max_port; ++i) {/* UART0 configuration offset start from 0x2A0 */ 0 x2A0 + 0 x08 * i;/* Select 128-byte FIFO and 8x FIFO threshold */ 0 x01, 0 x33);/* Enable UART I/O port */ 0 , 0 x01);return max_port;static int skip_tx_en_setup(struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)"serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n" ,return pci_default_setup(priv, board, port, idx);static void kt_handle_break(struct uart_port *p)struct uart_8250_port *up = up_to_u8250p(p);/* * On receipt of a BI, serial device in Intel ME (Intel * management engine) needs to have its fifos cleared for sane * SOL (Serial Over Lan) output. static u32 kt_serial_in(struct uart_port *p, unsigned int offset)struct uart_8250_port *up = up_to_u8250p(p);/* * When the Intel ME (management engine) gets reset its serial * port registers could return 0 momentarily. Functions like * serial8250_console_write, read and save the IER, perform * some operation and then restore it. In order to avoid * setting IER register inadvertently to 0, if the value read * is 0, double check with ier value in uart_8250_port and use * that instead. up->ier should be the same value as what is * currently configured. if (offset == UART_IER) {if (val == 0 )return val;static int kt_serial_setup(struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)if (!IS_ENABLED(CONFIG_HAS_IOPORT))return serial_8250_warn_need_ioport(priv->dev);return skip_tx_en_setup(priv, board, port, idx);static int pci_eg20t_init(struct pci_dev *dev)#if defined (CONFIG_SERIAL_PCH_UART) || defined (CONFIG_SERIAL_PCH_UART_MODULE)return -ENODEV;#else return 0 ;#endif static int struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)if (!IS_ENABLED(CONFIG_HAS_IOPORT))return serial_8250_warn_need_ioport(priv->dev);return pci_default_setup(priv, board, port, idx);static int struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)if (!IS_ENABLED(CONFIG_HAS_IOPORT))return serial_8250_warn_need_ioport(priv->dev);return pci_default_setup(priv, board, port, idx);static int struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)if (!IS_ENABLED(CONFIG_HAS_IOPORT))return serial_8250_warn_need_ioport(priv->dev);return pci_default_setup(priv, board, port, idx);#define CH384_XINT_ENABLE_REG 0 xEB#define CH384_XINT_ENABLE_BIT 0 x02static int pci_wch_ch38x_init(struct pci_dev *dev)int max_port;unsigned long iobase;if (!IS_ENABLED(CONFIG_HAS_IOPORT))return serial_8250_warn_need_ioport(dev);switch (dev->device) {case 0 x3853: /* 8 ports */ 8 ;break ;default :return -EINVAL;0 );return max_port;static void pci_wch_ch38x_exit(struct pci_dev *dev)unsigned long iobase;if (!IS_ENABLED(CONFIG_HAS_IOPORT)) {return ;0 );0 x0, iobase + CH384_XINT_ENABLE_REG);static int struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)int bar;int offset;if (idx < 4 ) {0 ;else {1 ;4 ;4 , &offset);64 + offset * board->uart_offset;return setup_port(priv, port, bar, offset, 0 );#define MOXA_PUART_GPIO_EN 0 x09#define MOXA_PUART_GPIO_OUT 0 x0A#define MOXA_GPIO_PIN2 BIT(2 )#define MOXA_RS232 0 x00#define MOXA_RS422 0 x01#define MOXA_RS485_4W 0 x0B#define MOXA_RS485_2W 0 x0F#define MOXA_UIR_OFFSET 0 x04#define MOXA_EVEN_RS_MASK GENMASK(3 , 0 )#define MOXA_ODD_RS_MASK GENMASK(7 , 4 )enum {0 ),1 ),2 ),static unsigned short moxa_get_nports(unsigned short device)switch (device) {case PCI_DEVICE_ID_MOXA_CP116E_A_A:case PCI_DEVICE_ID_MOXA_CP116E_A_B:return 8 ;return FIELD_GET(0 x00F0, device);static bool pci_moxa_is_mini_pcie(unsigned short device)if (device == PCI_DEVICE_ID_MOXA_CP102N ||return true ;return false ;static unsigned int pci_moxa_supported_rs(struct pci_dev *dev)switch (dev->device & 0 x0F00) {case 0 x0000:case 0 x0600:return MOXA_SUPP_RS232;case 0 x0100:return MOXA_SUPP_RS232 | MOXA_SUPP_RS422 | MOXA_SUPP_RS485;case 0 x0300:return MOXA_SUPP_RS422 | MOXA_SUPP_RS485;return 0 ;static int pci_moxa_set_interface(const struct pci_dev *dev,unsigned int port_idx,2 );2 ;if (port_idx % 2 ) {else {return 0 ;static int pci_moxa_init(struct pci_dev *dev)unsigned short device = dev->device;2 );unsigned int i, num_ports = moxa_get_nports(device);if (!IS_ENABLED(CONFIG_HAS_IOPORT))return serial_8250_warn_need_ioport(dev);if (!(pci_moxa_supported_rs(dev) & MOXA_SUPP_RS232)) {for (i = 0 ; i < num_ports; ++i)/* * Enable hardware buffer to prevent break signal output when system boots up. * This hardware buffer is only supported on Mini PCIe series. if (pci_moxa_is_mini_pcie(device)) {/* Set GPIO direction */ /* Enable low GPIO */ return num_ports;static int struct serial_private *priv,const struct pciserial_board *board,struct uart_8250_port *port, int idx)unsigned int bar = FL_GET_BASE(board->flags);int offset;if (!IS_ENABLED(CONFIG_HAS_IOPORT))return serial_8250_warn_need_ioport(priv->dev);if (board->num_ports == 4 && idx == 3 )7 * board->uart_offset;else return setup_port(priv, port, bar, offset, 0 );/* * Master list of serial port init/setup/exit quirks. * This does not describe the general nature of the port. * (ie, baud base, number and location of ports, etc) * * This list is ordered alphabetically by vendor then device. * Specific entries must come before more generic entries. static struct pci_serial_quirk pci_serial_quirks[] = {/* * ADDI-DATA GmbH communication cards <info@addi-data.com> /* * AFAVLAB cards - these may be called via parport_serial * It is not clear whether this applies to all products. /* * HP Diva /* * HPE PCI serial device /* * Intel 0 xe4bf,/* * ITE exit = pci_ite887x_exit,/* * National Instruments exit = pci_ni8420_exit,exit = pci_ni8420_exit,exit = pci_ni8420_exit,exit = pci_ni8420_exit,exit = pci_ni8420_exit,exit = pci_ni8420_exit,exit = pci_ni8420_exit,exit = pci_ni8420_exit,exit = pci_ni8420_exit,exit = pci_ni8420_exit,exit = pci_ni8420_exit,exit = pci_ni8420_exit,exit = pci_ni8430_exit,/* Quatech */ /* * Panacom exit = pci_plx9050_exit,exit = pci_plx9050_exit,/* * PLX exit = pci_plx9050_exit,exit = pci_plx9050_exit,exit = pci_plx9050_exit,/* * SBS Technologies, Inc., PMC-OCTALPRO 232 exit = sbs_exit,/* * SBS Technologies, Inc., PMC-OCTALPRO 422 exit = sbs_exit,/* * SBS Technologies, Inc., P-Octal 232 exit = sbs_exit,/* * SBS Technologies, Inc., P-Octal 422 exit = sbs_exit,/* * SIIG cards - these may be called via parport_serial /* * Titan cards /* * Timedia cards /* * Sunix PCI serial boards /* * Xircom cards /* * Netmos cards - these may be called via parport_serial /* * EndRun Technologies /* * For Oxford Semiconductor Tornado based devices /* * Brainboxes devices - all Oxsemi based 0 x4027,0 x4028,0 x4029,0 x4019,0 x4016,0 x4015,0 x400A,0 x400E,0 x400C,0 x400B,0 x400F,0 x4010,0 x4011,0 x401D,0 x401E,0 x4013,0 x4017,0 x4018,0 x4026,0 x4021,0 x8811,0 x8812,0 x8813,0 x8814,0 x10DB,0 x8027,0 x10DB,0 x8028,0 x10DB,0 x8029,0 x10DB,0 x800C,0 x10DB,0 x800D,/* * Cronyx Omega PCI (PLX-chip based) /* WCH CH353 1S1P card (16550 clone) */ /* WCH CH353 2S1P card (16550 clone) */ /* WCH CH353 4S card (16550 clone) */ /* WCH CH353 2S1PF card (16550 clone) */ /* WCH CH352 2S card (16550 clone) */ /* WCH CH355 4S card (16550 clone) */ /* WCH CH382 2S card (16850 clone) */ /* WCH CH382 2S1P card (16850 clone) */ /* WCH CH384 4S card (16850 clone) */ /* WCH CH384 8S card (16850 clone) */ exit = pci_wch_ch38x_exit,/* * Broadcom TruManage (NetXtreme) 0 x1c29,0 x1104,0 x1c29,0 x1108,0 x1c29,0 x1112,/* * MOXA 0 x1c29,0 x1204,0 x1c29,0 x1208,0 x1c29,0 x1212,/* * Default "match everything" terminator entry static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)return quirk_id == PCI_ANY_ID || quirk_id == dev_id;static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)struct pci_serial_quirk *quirk;for (quirk = pci_serial_quirks; ; quirk++)if (quirk_id_matches(quirk->vendor, dev->vendor) &&break ;return quirk;/* * This is the configuration table for all of the PCI serial boards * which we support. It is directly indexed by the pci_board_num_t enum * value, which is encoded in the pci_device_id PCI probe table's * driver_data member. * * The makeup of these names are: * pbn_bn{_bt}_n_baud{_offsetinhex} * * bn = PCI BAR number * bt = Index using PCI BARs * n = number of serial ports * baud = baud rate * offsetinhex = offset for each sequential port (in hex) * * This table is sorted by (in order): bn, bt, baud, offsetindex, n. * * Please note: in theory if n = 1, _bt infix should make no difference. * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 enum pci_board_num_t {0 ,/* * Board-specific versions. /* * uart_offset - the space between channels * reg_shift - describes how the UART registers are mapped * to PCI memory by the card. * For example IER register on SBS, Inc. PMC-OctPro is located at * offset 0x10 from the UART base, while UART_IER is defined as 1 * in include/linux/serial_reg.h, * see first lines of serial_in() and serial_out() in 8250.c static struct pciserial_board pci_boards[] = {1 ,115200 ,8 ,1 ,115200 ,8 ,2 ,115200 ,8 ,4 ,115200 ,8 ,5 ,115200 ,8 ,8 ,115200 ,8 ,1 ,921600 ,8 ,2 ,921600 ,8 ,4 ,921600 ,8 ,2 ,1130000 ,8 ,4 ,1152000 ,8 ,4 ,1250000 ,8 ,2 ,1843200 ,8 ,4 ,1843200 ,8 ,1 ,15625000 ,8 ,1 ,115200 ,8 ,2 ,115200 ,8 ,4 ,115200 ,8 ,8 ,115200 ,8 ,1 ,460800 ,8 ,2 ,460800 ,8 ,4 ,460800 ,8 ,1 ,921600 ,8 ,2 ,921600 ,8 ,4 ,921600 ,8 ,8 ,921600 ,8 ,1 ,115200 ,8 ,2 ,115200 ,8 ,4 ,115200 ,8 ,8 ,115200 ,8 ,16 ,115200 ,8 ,1 ,921600 ,8 ,2 ,921600 ,8 ,4 ,921600 ,8 ,8 ,921600 ,8 ,2 ,1250000 ,8 ,1 ,115200 ,8 ,2 ,115200 ,8 ,4 ,115200 ,8 ,2 ,921600 ,8 ,1 ,1382400 ,8 ,2 ,1382400 ,8 ,4 ,1382400 ,8 ,8 ,1382400 ,8 ,1 ,115200 ,8 ,2 ,115200 ,8 ,4 ,115200 ,8 ,8 ,115200 ,8 ,1 ,460800 ,8 ,4 ,460800 ,8 ,8 ,460800 ,8 ,16 ,460800 ,8 ,1 ,921600 ,8 ,4 ,921600 ,8 ,8 ,921600 ,8 ,8 ,1152000 ,8 ,1 ,115200 ,8 ,2 ,115200 ,8 ,4 ,115200 ,8 ,2 ,921600 ,8 ,4 ,921600 ,8 ,2 ,115200 ,8 ,4 ,115200 ,8 ,8 ,115200 ,8 ,2 ,921600 ,8 ,4 ,921600 ,8 ,8 ,921600 ,8 ,/* * Entries following this are board-specific. /* * Panacom - IOMEM 2 ,921600 ,0 x400,7 ,2 ,921600 ,0 x400,7 ,4 ,921600 ,0 x400,7 ,/* I think this entry is broken - the first_offset looks wrong --rmk */ 4 ,921600 ,8 << 2 ,2 ,0 x03,/* * This board uses the size of PCI Base region 0 to * signal now many ports are available 32 ,115200 ,8 ,1 ,15625000 ,0 x200,0 x1000,2 ,15625000 ,0 x200,0 x1000,4 ,15625000 ,0 x200,0 x1000,8 ,15625000 ,0 x200,0 x1000,/* * EKF addition for i960 Boards form EKF with serial port. * Max 256 ports. 32 ,921600 ,8 << 2 ,2 ,0 x10000,1 ,458333 ,8 ,0 ,0 x20178,/* * Computone - uses IOMEM. 4 ,921600 ,0 x40,2 ,0 x200,6 ,921600 ,0 x40,2 ,0 x200,8 ,921600 ,0 x40,2 ,0 x200,8 ,460800 ,256 ,4 ,/* * PA Semi PWRficient PA6T-1682M on-chip UART 1 ,8333333 ,/* * National Instruments 843x 16 ,3686400 ,0 x10,0 x800,8 ,3686400 ,0 x10,0 x800,4 ,3686400 ,0 x10,0 x800,2 ,3686400 ,0 x10,0 x800,/* * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 1 ,3906250 ,0 x200,0 x1000,2 ,3906250 ,0 x200,0 x1000,4 ,3906250 ,0 x200,0 x1000,8 ,3906250 ,0 x200,0 x1000,2 ,921600 ,2 ,8 ,115200 ,0 x200,2 ,115200 ,1 ,2 ,115200 ,4 ,8 ,115200 ,0 x40,8 ,8 ,115200 ,0 x40,12 ,8 ,115200 ,0 x40,4 ,8 ,115200 ,8 ,8 ,115200 ,12 ,8 ,115200 ,2 ,115200 ,8 ,0 xC0,4 ,115200 ,8 ,0 xC0,8 ,115200 ,8 ,0 x00,1 ,921600 ,0 x8,2 ,921600 ,0 x8,4 ,921600 ,0 x8,8 ,921600 ,0 x8,16 ,921600 ,0 x8,1 ,4000000 ,0 x200,0 x1000,2 ,4000000 ,0 x200,0 x1000,4 ,4000000 ,0 x200,0 x1000,8 ,4000000 ,0 x200,0 x1000,2 ,921600 ,0 x200,4 ,921600 ,0 x200,8 ,921600 ,0 x200,#define REPORT_CONFIG(option) \## option) ? 0 : (kernel_ulong_t)&#option )#define REPORT_8250_CONFIG(option) \## option) ? \0 : (kernel_ulong_t)&"SERIAL_8250_" #option )static const struct pci_device_id blacklist[] = {/* softmodems */ 0 x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 0 x3052), }, /* Motorola Si3052-based modem */ 0 x1543, 0 x3052), }, /* Si3052-based modem, default IDs */ /* multi-io cards handled by parport_serial */ /* WCH CH353 2S1P */ 0 x7053), REPORT_CONFIG(PARPORT_SERIAL), },/* WCH CH353 1S1P */ 0 x5053), REPORT_CONFIG(PARPORT_SERIAL), },/* WCH CH382 2S1P */ 0 x3250), REPORT_CONFIG(PARPORT_SERIAL), },/* Intel platforms with MID UART */ 0 x081b), REPORT_8250_CONFIG(MID), },0 x081c), REPORT_8250_CONFIG(MID), },0 x081d), REPORT_8250_CONFIG(MID), },0 x1191), REPORT_8250_CONFIG(MID), },0 x18d8), REPORT_8250_CONFIG(MID), },0 x19d8), REPORT_8250_CONFIG(MID), },/* Intel platforms with DesignWare UART */ 0 x0936), REPORT_8250_CONFIG(LPSS), },0 x0f0a), REPORT_8250_CONFIG(LPSS), },0 x0f0c), REPORT_8250_CONFIG(LPSS), },0 x228a), REPORT_8250_CONFIG(LPSS), },0 x228c), REPORT_8250_CONFIG(LPSS), },0 x4b96), REPORT_8250_CONFIG(LPSS), },0 x4b97), REPORT_8250_CONFIG(LPSS), },0 x4b98), REPORT_8250_CONFIG(LPSS), },0 x4b99), REPORT_8250_CONFIG(LPSS), },0 x4b9a), REPORT_8250_CONFIG(LPSS), },0 x4b9b), REPORT_8250_CONFIG(LPSS), },0 x9ce3), REPORT_8250_CONFIG(LPSS), },0 x9ce4), REPORT_8250_CONFIG(LPSS), },/* Exar devices */ /* Pericom devices */ /* End of the black list */ static int serial_pci_is_class_communication(struct pci_dev *dev)/* * If it is not a communications device or the programming * interface is greater than 6, give up. if ((((dev->class >> 8 ) != PCI_CLASS_COMMUNICATION_SERIAL) &&class >> 8 ) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&class >> 8 ) != PCI_CLASS_COMMUNICATION_MODEM)) ||class & 0 xff) > 6 )return -ENODEV;return 0 ;/* * Given a complete unknown PCI device, try to use some heuristics to * guess what the configuration might be, based on the pitiful PCI * serial specs. Returns 0 on success, -ENODEV on failure. static int struct pci_dev *dev, struct pciserial_board *board)int num_iomem, num_port, first_port = -1 , i;int rc;if (rc)return rc;/* * Should we try to make guesses for multiport serial devices later? if ((dev->class >> 8 ) == PCI_CLASS_COMMUNICATION_MULTISERIAL)return -ENODEV;0 ;for (i = 0 ; i < PCI_STD_NUM_BARS; i++) {if (pci_resource_flags(dev, i) & IORESOURCE_IO) {if (first_port == -1 )if (pci_resource_flags(dev, i) & IORESOURCE_MEM)/* * If there is 1 or 0 iomem regions, and exactly one port, * use it. We guess the number of ports based on the IO * region size. if (num_iomem <= 1 && num_port == 1 ) {8 ;return 0 ;/* * Now guess if we've got a board which indexes by BARs. * Each IO BAR should be 8 bytes, and they should follow * consecutively. 1 ;0 ;for (i = 0 ; i < PCI_STD_NUM_BARS; i++) {if (pci_resource_flags(dev, i) & IORESOURCE_IO &&8 &&1 || (first_port + num_port) == i)) {if (first_port == -1 )if (num_port > 1 ) {return 0 ;return -ENODEV;static inline int const struct pciserial_board *board,const struct pciserial_board *guessed)return struct serial_private *struct pci_dev *dev, const struct pciserial_board *board)struct uart_8250_port uart;struct serial_private *priv;struct pci_serial_quirk *quirk;int rc, nr_ports, i;/* * Find an init and setup quirks. /* * Run the new-style initialization function. * The initialization function returns: * <0 - error * 0 - use board->num_ports * >0 - number of ports if (quirk->init) {if (rc < 0 ) {goto err_out;if (rc)if (!priv) {goto err_deinit;0 , sizeof (uart));16 ;if (board->flags & FL_NOIRQ) {0 ;else {if (pci_match_id(pci_use_msi, dev)) {"Using MSI(-X) interrupts\n" );1 , 1 , PCI_IRQ_ALL_TYPES);else {"Using legacy interrupts\n" );1 , 1 , PCI_IRQ_INTX);if (rc < 0 ) {goto err_deinit;0 );for (i = 0 ; i < nr_ports; i++) {if (quirk->setup(priv, board, &uart, i))break ;"Setup PCI port: port %lx, irq %d, type %d\n" ,if (priv->line[i] < 0 ) {"Couldn't register serial port %lx, irq %d, type %d, error %d\n" ,break ;return priv;if (quirk->exit )exit (dev);return priv;static void pciserial_detach_ports(struct serial_private *priv)struct pci_serial_quirk *quirk;int i;for (i = 0 ; i < priv->nr; i++)/* * Find the exit quirks. if (quirk->exit )exit (priv->dev);void pciserial_remove_ports(struct serial_private *priv)void pciserial_suspend_ports(struct serial_private *priv)int i;for (i = 0 ; i < priv->nr; i++)if (priv->line[i] >= 0 )/* * Ensure that every init quirk is properly torn down if (priv->quirk->exit )exit (priv->dev);void pciserial_resume_ports(struct serial_private *priv)int i;/* * Ensure that the board is correctly configured. if (priv->quirk->init)for (i = 0 ; i < priv->nr; i++)if (priv->line[i] >= 0 )/* * Probe one serial board. Unfortunately, there is no rhyme nor reason * to the arrangement of serial ports on a PCI card. static int struct pci_dev *dev, const struct pci_device_id *ent)struct pci_serial_quirk *quirk;struct serial_private *priv;const struct pciserial_board *board;const struct pci_device_id *exclude;struct pciserial_board tmp;int rc;if (quirk->probe) {if (rc)return rc;if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {"invalid driver_data: %ld\n" , ent->driver_data);return -EINVAL;if (exclude) {if (exclude->driver_data)"ignoring port, enable %s to handle\n" ,const char *)exclude->driver_data);return -ENODEV;if (rc)return rc;if (ent->driver_data == pbn_default) {/* * Use a copy of the pci_board entry for this; * avoid changing entries in the table. sizeof (struct pciserial_board));/* * We matched one of our class entries. Try to * determine the parameters of this board. if (rc)return rc;else {/* * We matched an explicit entry. If we are able to * detect this boards settings with our heuristic, * then we no longer need this entry. sizeof (struct pciserial_board));if (rc == 0 && serial_pci_matches(board, &tmp))"Redundant entry in serial pci_table." ,if (IS_ERR(priv))return PTR_ERR(priv);return 0 ;static void pciserial_remove_one(struct pci_dev *dev)struct serial_private *priv = pci_get_drvdata(dev);#ifdef CONFIG_PM_SLEEPstatic int pciserial_suspend_one(struct device *dev)struct serial_private *priv = dev_get_drvdata(dev);if (priv)return 0 ;static int pciserial_resume_one(struct device *dev)struct pci_dev *pdev = to_pci_dev(dev);struct serial_private *priv = pci_get_drvdata(pdev);int err;if (priv) {/* * The device may have been disabled. Re-enable it. /* FIXME: We cannot simply error out here */ if (err)"Unable to re-enable ports, trying to continue.\n" );return 0 ;#endif static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,static const struct pci_device_id serial_pci_tbl[] = {0 , 0 ,/* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 0 x0001, 0 , 0 ,/* Advantech also use 0x3618 and 0xf618 */ 0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,/* * VScom SPCOM800, from sl@s.pl 0 , 0 ,0 , 0 ,/* Unknown card - subdevice 0x1584 */ 0 , 0 ,/* Unknown card - subdevice 0x1588 */ 0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,/* * Megawolf Romulus PCI Serial Card, from Mike Hudson * (Exoray@isys.ca) 0 x10b5, 0 x106a, 0 , 0 ,/* * Quatech cards. These actually have configurable clocks but for * now we just use the default. * * 100 series are RS232, 200 series RS422, 0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 x9505,0 , 0 ,/* * The below card is a little controversial since it is the * subject of a PCI vendor/device ID clash. (See * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). * For now just used the hex ID 0x950a. 0 x950a,0 , 0 , pbn_b0_2_115200 },0 x950a,0 , 0 , pbn_b0_2_115200 },0 x950a,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,/* * Oxford Semiconductor Inc. Tornado PCI express device range. 0 xc101, /* OXPCIe952 1 Legacy UART */ 0 , 0 ,0 xc105, /* OXPCIe952 1 Legacy UART */ 0 , 0 ,0 xc11b, /* OXPCIe952 1 Native UART */ 0 , 0 ,0 xc11f, /* OXPCIe952 1 Native UART */ 0 , 0 ,0 xc120, /* OXPCIe952 1 Legacy UART */ 0 , 0 ,0 xc124, /* OXPCIe952 1 Legacy UART */ 0 , 0 ,0 xc138, /* OXPCIe952 1 Native UART */ 0 , 0 ,0 xc13d, /* OXPCIe952 1 Native UART */ 0 , 0 ,0 xc140, /* OXPCIe952 1 Legacy UART */ 0 , 0 ,0 xc141, /* OXPCIe952 1 Legacy UART */ 0 , 0 ,0 xc144, /* OXPCIe952 1 Legacy UART */ 0 , 0 ,0 xc145, /* OXPCIe952 1 Legacy UART */ 0 , 0 ,0 xc158, /* OXPCIe952 2 Native UART */ 0 , 0 ,0 xc15d, /* OXPCIe952 2 Native UART */ 0 , 0 ,0 xc208, /* OXPCIe954 4 Native UART */ 0 , 0 ,0 xc20d, /* OXPCIe954 4 Native UART */ 0 , 0 ,0 xc308, /* OXPCIe958 8 Native UART */ 0 , 0 ,0 xc30d, /* OXPCIe958 8 Native UART */ 0 , 0 ,0 xc40b, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc40f, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc41b, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc41f, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc42b, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc42f, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc43b, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc43f, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc44b, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc44f, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc45b, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc45f, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc46b, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc46f, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc47b, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc47f, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc48b, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc48f, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc49b, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc49f, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc4ab, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc4af, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc4bb, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc4bf, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc4cb, /* OXPCIe200 1 Native UART */ 0 , 0 ,0 xc4cf, /* OXPCIe200 1 Native UART */ 0 , 0 ,/* * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 0 x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 0 x4001, 0 , 0 ,0 x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 0 x4002, 0 , 0 ,0 x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 0 x4004, 0 , 0 ,0 x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 0 x4008, 0 , 0 ,/* * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 0 , 0 ,/* * EndRun Technologies. PCI express device range. * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952. 0 , 0 ,/* * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, * from skokodyn@yahoo.com 0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,/* * Digitan DS560-558, from jimd@esoft.com 0 , 0 ,/* * Titan Electronic cards * The 400L and 800L have a custom setup quirk. 0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,/* * Computone devices submitted by Doug McNash dmcnash@computone.com 0 , 0 , pbn_computone_4 },0 , 0 , pbn_computone_8 },0 , 0 , pbn_computone_6 },0 , 0 ,0 , 0 ,/* * Sunix PCI serial boards 0 x0001, 0 , 0 ,0 x0002, 0 , 0 ,0 x0004, 0 , 0 ,0 x0084, 0 , 0 ,0 x0008, 0 , 0 ,0 x0088, 0 , 0 ,0 x0010, 0 , 0 ,/* * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,/* * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). * Cards are identified by their subsystem vendor IDs, which * (in hex) match the model number. * * Note that JC140x are RS422/485 cards which require ox950 * ACR = 0x10, and as such are not currently fully supported. 0 x1204, 0 x0004, 0 , 0 ,0 x1208, 0 x0004, 0 , 0 ,/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 0x1402, 0x0002, 0, 0, /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 0x1404, 0x0004, 0, 0, 0 x1208, 0 x0004, 0 , 0 ,0 x1204, 0 x0004, 0 , 0 ,0 x1208, 0 x0004, 0 , 0 ,0 x1208, 0 x0004, 0 , 0 ,/* * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 0 , 0 ,/* * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 0 , 0 ,/* * RAStel 2 port modem, gerg@moreton.com.au 0 , 0 ,/* * EKF addition for i960 Boards form EKF with serial port 0 xE4BF, PCI_ANY_ID, 0 , 0 ,/* * Xircom Cardbus/Ethernet combos 0 , 0 ,/* * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 0 , 0 ,/* * Untested PCI modems, sent in from various folks... /* * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 0 x1004,0 x1048, 0 x1500, 0 , 0 ,0 xFF00, 0 , 0 , 0 ,/* * HP Diva card 0 , 0 ,0 , 0 ,0 , 0 ,/* HPE PCI serial device */ 0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,/* * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 0 , 0 ,/* * ITE 0 , 0 ,/* * IntaShield IS-100 0 x0D60,0 , 0 ,/* * IntaShield IS-200 0 , 0 , /* 135a.0d80 */ /* * IntaShield IS-400 0 , 0 , /* 135a.0dc0 */ /* * IntaShield IX-100 0 x4027,0 , 0 ,/* * IntaShield IX-200 0 x4028,0 , 0 ,/* * IntaShield IX-400 0 x4029,0 , 0 ,/* Brainboxes Devices */ /* * Brainboxes UC-101 0 x0BA1,0 , 0 ,0 x0BA2,0 , 0 ,0 x0BA3,0 , 0 ,/* * Brainboxes UC-235/246 0 x0AA1,0 , 0 ,0 x0AA2,0 , 0 ,/* * Brainboxes UC-253/UC-734 0 x0CA1,0 , 0 ,/* * Brainboxes UC-260/271/701/756 0 x0D21,8 , 0 xffff00,0 x0E34,8 , 0 xffff00,/* * Brainboxes UC-268 0 x0841,0 , 0 ,/* * Brainboxes UC-275/279 0 x0881,0 , 0 ,/* * Brainboxes UC-302 0 x08E1,0 , 0 ,0 x08E2,0 , 0 ,0 x08E3,0 , 0 ,/* * Brainboxes UC-310 0 x08C1,0 , 0 ,/* * Brainboxes UC-313 0 x08A1,0 , 0 ,0 x08A2,0 , 0 ,0 x08A3,0 , 0 ,/* * Brainboxes UC-320/324 0 x0A61,0 , 0 ,/* * Brainboxes UC-346 0 x0B01,0 , 0 ,0 x0B02,0 , 0 ,/* * Brainboxes UC-357 0 x0A81,0 , 0 ,0 x0A82,0 , 0 ,0 x0A83,0 , 0 ,/* * Brainboxes UC-368 0 x0C41,0 , 0 ,0 x0C42,0 , 0 ,0 x0C43,0 , 0 ,/* * Brainboxes UC-420 0 x0921,0 , 0 ,/* * Brainboxes UC-607 0 x09A1,0 , 0 ,0 x09A2,0 , 0 ,0 x09A3,0 , 0 ,/* * Brainboxes UC-836 0 x0D41,0 , 0 ,/* * Brainboxes UP-189 0 x0AC1,0 , 0 ,0 x0AC2,0 , 0 ,0 x0AC3,0 , 0 ,/* * Brainboxes UP-200 0 x0B21,0 , 0 ,0 x0B22,0 , 0 ,0 x0B23,0 , 0 ,/* * Brainboxes UP-869 0 x0C01,0 , 0 ,0 x0C02,0 , 0 ,0 x0C03,0 , 0 ,/* * Brainboxes UP-880 0 x0C21,0 , 0 ,0 x0C22,0 , 0 ,0 x0C23,0 , 0 ,/* * Brainboxes PX-101 0 x4005,0 , 0 ,0 x4019,0 , 0 ,/* * Brainboxes PX-235/246 0 x4004,0 , 0 ,0 x4016,0 , 0 ,/* * Brainboxes PX-203/PX-257 0 x4006,0 , 0 ,0 x4015,0 , 0 ,/* * Brainboxes PX-260/PX-701 0 x400A,0 , 0 ,/* * Brainboxes PX-275/279 0 x0E41,0 , 0 ,/* * Brainboxes PX-310 0 x400E,0 , 0 ,/* * Brainboxes PX-313 0 x400C,0 , 0 ,/* * Brainboxes PX-320/324/PX-376/PX-387 0 x400B,0 , 0 ,/* * Brainboxes PX-335/346 0 x400F,0 , 0 ,/* * Brainboxes PX-368 0 x4010,0 , 0 ,/* * Brainboxes PX-420 0 x4000,0 , 0 ,0 x4011,0 , 0 ,/* * Brainboxes PX-475 0 x401D,0 , 0 ,/* * Brainboxes PX-803/PX-857 0 x4009,0 , 0 ,0 x4018,0 , 0 ,0 x401E,0 , 0 ,/* * Brainboxes PX-820 0 x4002,0 , 0 ,0 x4013,0 , 0 ,/* * Brainboxes PX-835/PX-846 0 x4008,0 , 0 ,0 x4017,0 , 0 ,/* * Brainboxes XC-235 0 x4026,0 , 0 ,/* * Brainboxes XC-475 0 x4021,0 , 0 ,/* * Perle PCI-RAS cards 0 , 0 , pbn_b2_4_921600 },0 , 0 , pbn_b2_8_921600 },/* * Mainpine series cards: Fairly standard layout but fools * parts of the autodetect in some cases and uses otherwise * unmatched communications subclasses in the PCI Express case /* RockForceDUO */ 0 x0200,0 , 0 , pbn_b0_2_115200 },/* RockForceQUATRO */ 0 x0300,0 , 0 , pbn_b0_4_115200 },/* RockForceDUO+ */ 0 x0400,0 , 0 , pbn_b0_2_115200 },/* RockForceQUATRO+ */ 0 x0500,0 , 0 , pbn_b0_4_115200 },/* RockForce+ */ 0 x0600,0 , 0 , pbn_b0_2_115200 },/* RockForce+ */ 0 x0700,0 , 0 , pbn_b0_4_115200 },/* RockForceOCTO+ */ 0 x0800,0 , 0 , pbn_b0_8_115200 },/* RockForceDUO+ */ 0 x0C00,0 , 0 , pbn_b0_2_115200 },/* RockForceQUARTRO+ */ 0 x0D00,0 , 0 , pbn_b0_4_115200 },/* RockForceOCTO+ */ 0 x1D00,0 , 0 , pbn_b0_8_115200 },/* RockForceD1 */ 0 x2000,0 , 0 , pbn_b0_1_115200 },/* RockForceF1 */ 0 x2100,0 , 0 , pbn_b0_1_115200 },/* RockForceD2 */ 0 x2200,0 , 0 , pbn_b0_2_115200 },/* RockForceF2 */ 0 x2300,0 , 0 , pbn_b0_2_115200 },/* RockForceD4 */ 0 x2400,0 , 0 , pbn_b0_4_115200 },/* RockForceF4 */ 0 x2500,0 , 0 , pbn_b0_4_115200 },/* RockForceD8 */ 0 x2600,0 , 0 , pbn_b0_8_115200 },/* RockForceF8 */ 0 x2700,0 , 0 , pbn_b0_8_115200 },/* IQ Express D1 */ 0 x3000,0 , 0 , pbn_b0_1_115200 },/* IQ Express F1 */ 0 x3100,0 , 0 , pbn_b0_1_115200 },/* IQ Express D2 */ 0 x3200,0 , 0 , pbn_b0_2_115200 },/* IQ Express F2 */ 0 x3300,0 , 0 , pbn_b0_2_115200 },/* IQ Express D4 */ 0 x3400,0 , 0 , pbn_b0_4_115200 },/* IQ Express F4 */ 0 x3500,0 , 0 , pbn_b0_4_115200 },/* IQ Express D8 */ 0 x3C00,0 , 0 , pbn_b0_8_115200 },/* IQ Express F8 */ 0 x3D00,0 , 0 , pbn_b0_8_115200 },/* * PA Semi PA6T-1682M on-chip UART 0 xa004,0 , 0 ,/* * National Instruments 0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,/* * MOXA /* * ADDI-DATA GmbH communication cards <info@addi-data.com> 0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 x0299,0 , 0 , pbn_b0_bt_2_115200 },/* * other NetMos 9835 devices are most likely handled by the * parport_serial driver, check drivers/parport/parport_serial.c * before adding them here. 0 xA000, 0 x1000,0 , 0 , pbn_b0_1_115200 },/* the 9901 is a rebranded 9912 */ 0 xA000, 0 x1000,0 , 0 , pbn_b0_1_115200 },0 xA000, 0 x1000,0 , 0 , pbn_b0_1_115200 },0 xA000, 0 x1000,0 , 0 , pbn_b0_1_115200 },0 xA000, 0 x1000,0 , 0 , pbn_b0_1_115200 },0 xA000, 0 x3002,0 , 0 , pbn_NETMOS9900_2s_115200 },/* * Best Connectivity and Rosewill PCI Multi I/O cards 0 xA000, 0 x1000,0 , 0 , pbn_b0_1_115200 },0 xA000, 0 x3002,0 , 0 , pbn_b0_bt_2_115200 },0 xA000, 0 x3004,0 , 0 , pbn_b0_bt_4_115200 },/* * ASIX AX99100 PCIe to Multi I/O Controller 0 xA000, 0 x1000,0 , 0 , pbn_b0_1_115200 },/* Intel CE4100 */ 0 , 0 ,/* * Cronyx Omega PCI 0 , 0 ,/* * Broadcom TruManage 0 , 0 ,/* * AgeStar as-prs2-009 0 , 0 , pbn_b0_bt_2_115200 },/* * WCH CH353 series devices: The 2S1P is handled by parport_serial * so not listed here. 0 , 0 , pbn_b0_bt_4_115200 },0 , 0 , pbn_b0_bt_2_115200 },0 , 0 , pbn_b0_bt_4_115200 },0 , 0 , pbn_wch382_2 },0 , 0 , pbn_wch384_4 },0 , 0 , pbn_wch384_8 },/* * Realtek RealManage 0 x816a,0 , 0 , pbn_b0_1_115200 },0 x816b,0 , 0 , pbn_b0_1_115200 },/* Fintek PCI serial cards */ 0 x1c29, 0 x1104), .driver_data = pbn_fintek_4 },0 x1c29, 0 x1108), .driver_data = pbn_fintek_8 },0 x1c29, 0 x1112), .driver_data = pbn_fintek_12 },0 x1c29, 0 x1204), .driver_data = pbn_fintek_F81504A },0 x1c29, 0 x1208), .driver_data = pbn_fintek_F81508A },0 x1c29, 0 x1212), .driver_data = pbn_fintek_F81512A },/* MKS Tenta SCOM-080x serial cards */ 0 x1601, 0 x0800), .driver_data = pbn_b0_4_1250000 },0 x1601, 0 xa801), .driver_data = pbn_b0_4_1250000 },/* Amazon PCI serial device */ 0 x1d0f, 0 x8250), .driver_data = pbn_b0_1_115200 },/* * These entries match devices with class COMMUNICATION_SERIAL, * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 8 ,0 xffff00, pbn_default },8 ,0 xffff00, pbn_default },8 ,0 xffff00, pbn_default },0 , }static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,struct serial_private *priv = pci_get_drvdata(dev);if (state == pci_channel_io_perm_failure)return PCI_ERS_RESULT_DISCONNECT;if (priv)return PCI_ERS_RESULT_NEED_RESET;static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)int rc;if (rc)return PCI_ERS_RESULT_DISCONNECT;return PCI_ERS_RESULT_RECOVERED;static void serial8250_io_resume(struct pci_dev *dev)struct serial_private *priv = pci_get_drvdata(dev);struct serial_private *new ;if (!priv)return ;new = pciserial_init_ports(dev, priv->board);if (!IS_ERR(new )) {new );static const struct pci_error_handlers serial8250_err_handler = {static struct pci_driver serial_pci_driver = {"serial" ,"GPL" );"Generic 8250/16x50 PCI serial probe module" );"SERIAL_8250_PCI" );
Messung V0.5 in Prozent C=93 H=94 G=93
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