/* * The Thunderbolt host controller is present always in Ice Lake * but the firmware may not be loaded and running (depending * whether there is device connected and so on). Each time the * controller is used we need to "Force Power" it first and wait * for the firmware to indicate it is up and running. This "Force * Power" is really not about actually powering on/off the * controller so it is accessible even if "Force Power" is off. * * The actual power management happens inside shared ACPI power * resources using standard ACPI methods.
*/
pci_read_config_dword(nhi->pdev, VS_CAP_22, &vs_cap); if (power) {
vs_cap &= ~VS_CAP_22_DMA_DELAY_MASK;
vs_cap |= 0x22 << VS_CAP_22_DMA_DELAY_SHIFT;
vs_cap |= VS_CAP_22_FORCE_POWER;
} else {
vs_cap &= ~VS_CAP_22_FORCE_POWER;
}
pci_write_config_dword(nhi->pdev, VS_CAP_22, vs_cap);
if (power) { unsignedint retries = 350;
u32 val;
/* Wait until the firmware tells it is up and running */ do {
pci_read_config_dword(nhi->pdev, VS_CAP_9, &val); if (val & VS_CAP_9_FW_READY) return 0;
usleep_range(3000, 3100);
} while (--retries);
pci_read_config_dword(nhi->pdev, VS_CAP_16, &max_ltr);
max_ltr &= 0xffff; /* Program the same value for both snoop and no-snoop */
ltr = max_ltr << 16 | max_ltr;
pci_write_config_dword(nhi->pdev, VS_CAP_15, ltr);
}
if (tb_switch_is_icm(tb->root_switch)) { /* * If there is no device connected we need to perform * both: a handshake through LC mailbox and force power * down before entering D3.
*/
icl_nhi_lc_mailbox_cmd(nhi, ICL_LC_PREPARE_FOR_RESET);
ret = icl_nhi_lc_mailbox_cmd_complete(nhi, ICL_LC_MAILBOX_TIMEOUT); if (ret) return ret;
}
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