/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2025 Collabora Ltd * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> #ifndef __PMDOMAIN_MEDIATEK_MT6893_PM_DOMAINS_H#define __PMDOMAIN_MEDIATEK_MT6893_PM_DOMAINS_H#include <linux/soc/mediatek/infracfg.h>#include <dt-bindings/power/mediatek,mt6893-power.h>#include "mtk-pm-domains.h" #define MT6893_TOP_AXI_PROT_EN_MCU_STA1 0 x2e4#define MT6893_TOP_AXI_PROT_EN_MCU_SET 0 x2c4#define MT6893_TOP_AXI_PROT_EN_MCU_CLR 0 x2c8#define MT6893_TOP_AXI_PROT_EN_VDNR_1_SET 0 xba4#define MT6893_TOP_AXI_PROT_EN_VDNR_1_CLR 0 xba8#define MT6893_TOP_AXI_PROT_EN_VDNR_1_STA1 0 xbb0#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0 xbb8#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0 xbbc#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1 0 xbc4#define MT6893_TOP_AXI_PROT_EN_1_MFG1_STEP1 GENMASK(21 , 19 )#define MT6893_TOP_AXI_PROT_EN_2_MFG1_STEP2 GENMASK(6 , 5 )#define MT6893_TOP_AXI_PROT_EN_MFG1_STEP3 GENMASK(22 , 21 )#define MT6893_TOP_AXI_PROT_EN_2_MFG1_STEP4 BIT(7 )#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP5 GENMASK(19 , 17 )#define MT6893_TOP_AXI_PROT_EN_MM_VDEC0_STEP1 BIT(24 )#define MT6893_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2 BIT(25 )#define MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP1 BIT(6 )#define MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP2 BIT(7 )#define MT6893_TOP_AXI_PROT_EN_MM_VENC0_STEP1 BIT(26 )#define MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP2 BIT(0 )#define MT6893_TOP_AXI_PROT_EN_MM_VENC0_STEP3 BIT(27 )#define MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP4 BIT(1 )#define MT6893_TOP_AXI_PROT_EN_MM_VENC1_STEP1 GENMASK(30 , 28 )#define MT6893_TOP_AXI_PROT_EN_MM_VENC1_STEP2 GENMASK(31 , 29 )#define MT6893_TOP_AXI_PROT_EN_MDP_STEP1 BIT(10 )#define MT6893_TOP_AXI_PROT_EN_MM_MDP_STEP2 (BIT(2 ) | BIT(4 ) | BIT(6 ) | \8 ) | BIT(18 ) | BIT(22 ) | \28 ) | BIT(30 ))#define MT6893_TOP_AXI_PROT_EN_MM_2_MDP_STEP3 (BIT(0 ) | BIT(2 ) | BIT(4 ) | \6 ) | BIT(8 ))#define MT6893_TOP_AXI_PROT_EN_MDP_STEP4 BIT(23 )#define MT6893_TOP_AXI_PROT_EN_MM_MDP_STEP5 (BIT(3 ) | BIT(5 ) | BIT(7 ) | \9 ) | BIT(19 ) | BIT(23 ) | \29 ) | BIT(31 ))#define MT6893_TOP_AXI_PROT_EN_MM_2_MDP_STEP6 (BIT(1 ) | BIT(7 ) | BIT(9 ) | BIT(11 ))#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MDP_STEP7 BIT(20 )#define MT6893_TOP_AXI_PROT_EN_MM_DISP_STEP1 (BIT(0 ) | BIT(6 ) | BIT(8 ) | \10 ) | BIT(12 ) | BIT(14 ) | \16 ) | BIT(20 ) | BIT(24 ) | \26 ))#define MT6893_TOP_AXI_PROT_EN_DISP_STEP2 BIT(6 )#define MT6893_TOP_AXI_PROT_EN_MM_DISP_STEP3 (BIT(1 ) | BIT(7 ) | BIT(9 ) | \15 ) | BIT(17 ) | BIT(21 ) | \25 ) | BIT(27 ))#define MT6893_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_DISP_STEP4 BIT(21 )#define MT6893_TOP_AXI_PROT_EN_2_ADSP BIT(3 )#define MT6893_TOP_AXI_PROT_EN_2_CAM_STEP1 BIT(1 )#define MT6893_TOP_AXI_PROT_EN_MM_CAM_STEP2 (BIT(0 ) | BIT(2 ) | BIT(4 ))#define MT6893_TOP_AXI_PROT_EN_1_CAM_STEP3 BIT(22 )#define MT6893_TOP_AXI_PROT_EN_MM_CAM_STEP4 (BIT(1 ) | BIT(3 ) | BIT(5 ))#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWA_STEP1 BIT(18 )#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWA_STEP2 BIT(19 )#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWB_STEP1 BIT(20 )#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWB_STEP2 BIT(21 )#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWC_STEP1 BIT(22 )#define MT6893_TOP_AXI_PROT_EN_MM_CAM_RAWC_STEP2 BIT(23 )/* * MT6893 Power Domain (MTCMOS) support * * The register layout for this IP is very similar to MT8192 so where possible * the same definitions are reused to avoid duplication. * Where the bus protection bits are also the same, the entire set is reused. static const struct scpsys_domain_data scpsys_domain_data_mt6893[] = {"conn" ,1 ),0 x304,0 x16c,0 x170,0 ,0 ,"mfg0" ,2 ),0 x308,0 x16c,0 x170,8 ),12 ),"mfg1" ,3 ),0 x30c,0 x16c,0 x170,8 ),12 ),"mfg2" ,4 ),0 x310,0 x16c,0 x170,8 ),12 ),"mfg3" ,5 ),0 x314,0 x16c,0 x170,8 ),12 ),"mfg4" ,6 ),0 x318,0 x16c,0 x170,8 ),12 ),"mfg5" ,7 ),0 x31c,0 x16c,0 x170,8 ),12 ),"mfg6" ,8 ),0 x320,0 x16c,0 x170,8 ),12 ),"isp" ,12 ),0 x330,0 x16c,0 x170,8 ),12 ),"isp2" ,13 ),0 x334,0 x16c,0 x170,8 ),12 ),"ipe" ,14 ),0 x338,0 x16c,0 x170,8 ),12 ),"vdec0" ,15 ),0 x33c,0 x16c,0 x170,8 ),12 ),"vdec1" ,16 ),0 x340,0 x16c,0 x170,8 ),12 ),"venc0" ,17 ),0 x344,0 x16c,0 x170,8 ),12 ),"venc1" ,18 ),0 x348,0 x16c,0 x170,8 ),12 ),"mdp" ,19 ),0 x34c,0 x16c,0 x170,8 ),12 ),"disp" ,20 ),0 x350,0 x16c,0 x170,8 ),12 ),"audio" ,21 ),0 x354,0 x16c,0 x170,8 ),12 ),"audio" ,22 ),0 x358,0 x16c,0 x170,9 ),12 ),"cam" ,23 ),0 x35c,0 x16c,0 x170,8 ),12 ),"cam_rawa" ,24 ),0 x360,0 x16c,0 x170,8 ),12 ),"cam_rawb" ,25 ),0 x364,0 x16c,0 x170,8 ),12 ),"cam_rawc" ,26 ),0 x368,0 x16c,0 x170,8 ),12 ),"dp_tx" ,27 ),0 x3ac,0 x16c,0 x170,8 ),12 ),static const struct scpsys_soc_data mt6893_scpsys_data = {#endif /* __PMDOMAIN_MEDIATEK_MT6893_PM_DOMAINS_H */
Messung V0.5 in Prozent C=99 H=99 G=98
¤ Dauer der Verarbeitung: 0.12 Sekunden
(vorverarbeitet am 2026-06-08)
¤ *© Formatika GbR, Deutschland
