// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 /* * Mellanox platform driver * * Copyright (C) 2016-2018 Mellanox Technologies * Copyright (C) 2016-2018 Vadim Pasternak <vadimp@mellanox.com> #include <linux/device.h>#include <linux/dmi.h>#include <linux/i2c.h>#include <linux/i2c-mux.h>#include <linux/io.h>#include <linux/module.h>#include <linux/pci.h>#include <linux/platform_device.h>#include <linux/platform_data/i2c-mux-reg.h>#include <linux/platform_data/mlxreg.h>#include <linux/reboot.h>#include <linux/regmap.h>#define MLX_PLAT_DEVICE_NAME "mlxplat" /* LPC bus IO offsets */ #define MLXPLAT_CPLD_LPC_I2C_BASE_ADRR 0 x2000#define MLXPLAT_CPLD_LPC_REG_BASE_ADRR 0 x2500#define MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET 0 x00#define MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET 0 x01#define MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET 0 x02#define MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET 0 x03#define MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET 0 x04#define MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET 0 x05#define MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET 0 x06#define MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET 0 x07#define MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET 0 x08#define MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET 0 x09#define MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET 0 x0a#define MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET 0 x0b#define MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET 0 x17#define MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET 0 x19#define MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET 0 x1b#define MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET 0 x1c#define MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET 0 x1d#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET 0 x1e#define MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET 0 x1f#define MLXPLAT_CPLD_LPC_REG_LED1_OFFSET 0 x20#define MLXPLAT_CPLD_LPC_REG_LED2_OFFSET 0 x21#define MLXPLAT_CPLD_LPC_REG_LED3_OFFSET 0 x22#define MLXPLAT_CPLD_LPC_REG_LED4_OFFSET 0 x23#define MLXPLAT_CPLD_LPC_REG_LED5_OFFSET 0 x24#define MLXPLAT_CPLD_LPC_REG_LED6_OFFSET 0 x25#define MLXPLAT_CPLD_LPC_REG_LED7_OFFSET 0 x26#define MLXPLAT_CPLD_LPC_REG_LED8_OFFSET 0 x27#define MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION 0 x2a#define MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET 0 x2b#define MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET 0 x2d#define MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET 0 x2c#define MLXPLAT_CPLD_LPC_REG_GP0_OFFSET 0 x2e#define MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET 0 x2f#define MLXPLAT_CPLD_LPC_REG_GP1_OFFSET 0 x30#define MLXPLAT_CPLD_LPC_REG_WP1_OFFSET 0 x31#define MLXPLAT_CPLD_LPC_REG_GP2_OFFSET 0 x32#define MLXPLAT_CPLD_LPC_REG_WP2_OFFSET 0 x33#define MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE 0 x34#define MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET 0 x35#define MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET 0 x36#define MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET 0 x37#define MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET 0 x3a#define MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET 0 x3b#define MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET 0 x3c#define MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET 0 x40#define MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET 0 x41#define MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET 0 x42#define MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET 0 x43#define MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET 0 x44#define MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET 0 x45#define MLXPLAT_CPLD_LPC_REG_GP3_OFFSET 0 x46#define MLXPLAT_CPLD_LPC_REG_BRD_OFFSET 0 x47#define MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET 0 x48#define MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET 0 x49#define MLXPLAT_CPLD_LPC_REG_GWP_OFFSET 0 x4a#define MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET 0 x4b#define MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET 0 x4c#define MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET 0 x4e#define MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET 0 x50#define MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET 0 x51#define MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET 0 x52#define MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET 0 x53#define MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET 0 x54#define MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET 0 x55#define MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET 0 x56#define MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET 0 x57#define MLXPLAT_CPLD_LPC_REG_PSU_OFFSET 0 x58#define MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET 0 x59#define MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET 0 x5a#define MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET 0 x5e#define MLXPLAT_CPLD_LPC_REG_PWR_OFFSET 0 x64#define MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET 0 x65#define MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET 0 x66#define MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET 0 x6a#define MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET 0 x70#define MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET 0 x71#define MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET 0 x72#define MLXPLAT_CPLD_LPC_REG_FAN_OFFSET 0 x88#define MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET 0 x89#define MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET 0 x8a#define MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET 0 x8b#define MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET 0 x8c#define MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET 0 x8d#define MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET 0 x8e#define MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET 0 x8f#define MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET 0 x90#define MLXPLAT_CPLD_LPC_REG_EROT_OFFSET 0 x91#define MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET 0 x92#define MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET 0 x93#define MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET 0 x94#define MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET 0 x95#define MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET 0 x96#define MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET 0 x97#define MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET 0 x98#define MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET 0 x99#define MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET 0 x9a#define MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET 0 x9b#define MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET 0 x9c#define MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET 0 x9d#define MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET 0 x9e#define MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET 0 x9f#define MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET 0 xa0#define MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET 0 xa1#define MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET 0 xa2#define MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET 0 xa3#define MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET 0 xa4#define MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET 0 xa5#define MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET 0 xa6#define MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET 0 xa7#define MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET 0 xa8#define MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET 0 xa9#define MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET 0 xaa#define MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET 0 xab#define MLXPLAT_CPLD_LPC_REG_LC_PWR_ON 0 xb2#define MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET 0 xb4#define MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET 0 xb5#define MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET 0 xb6#define MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET 0 xb7#define MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET 0 xb8#define MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET 0 xb9#define MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET 0 xba#define MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET 0 xbb#define MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET 0 xc1#define MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET 0 xc2#define MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT 0 xc3#define MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET 0 xc4#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET 0 xc7#define MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET 0 xc8#define MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET 0 xc9#define MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET 0 xcb#define MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET 0 xcd#define MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET 0 xce#define MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET 0 xcf#define MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET 0 xd1#define MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET 0 xd2#define MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET 0 xd3#define MLXPLAT_CPLD_LPC_REG_CPLD6_MVER_OFFSET 0 xd9#define MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET 0 xdb#define MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET 0 xda#define MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET 0 xdc#define MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET 0 xdd#define MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET 0 xde#define MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET 0 xdf#define MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET 0 xe0#define MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET 0 xe1#define MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET 0 xe2#define MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET 0 xe3#define MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET 0 xe4#define MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET 0 xe5#define MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET 0 xe6#define MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET 0 xe7#define MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET 0 xe8#define MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET 0 xe9#define MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET 0 xea#define MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET 0 xeb#define MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET 0 xec#define MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET 0 xed#define MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET 0 xee#define MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET 0 xef#define MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET 0 xf0#define MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET 0 xf1#define MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET 0 xf2#define MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET 0 xf3#define MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET 0 xf4#define MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET 0 xf5#define MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET 0 xf6#define MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET 0 xf7#define MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET 0 xf8#define MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET 0 xf9#define MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET 0 xfa#define MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET 0 xfb#define MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET 0 xfc#define MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET 0 xfd#define MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET 0 xfe#define MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET 0 xff#define MLXPLAT_CPLD_LPC_IO_RANGE 0 x100#define MLXPLAT_CPLD_LPC_PIO_OFFSET 0 x10000UL#define MLXPLAT_CPLD_LPC_REG1 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \#define MLXPLAT_CPLD_LPC_REG2 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \#define MLXPLAT_CPLD_LPC_REG3 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \#define MLXPLAT_CPLD_LPC_REG4 ((MLXPLAT_CPLD_LPC_REG_BASE_ADRR + \/* Masks for aggregation, psu, pwr and fan event in CPLD related registers. */ #define MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF 0 x04#define MLXPLAT_CPLD_AGGR_PSU_MASK_DEF 0 x08#define MLXPLAT_CPLD_AGGR_PWR_MASK_DEF 0 x08#define MLXPLAT_CPLD_AGGR_FAN_MASK_DEF 0 x40#define MLXPLAT_CPLD_AGGR_MASK_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \#define MLXPLAT_CPLD_AGGR_ASIC_MASK_NG 0 x01#define MLXPLAT_CPLD_AGGR_MASK_NG_DEF 0 x04#define MLXPLAT_CPLD_AGGR_MASK_COMEX BIT(0 )#define MLXPLAT_CPLD_AGGR_MASK_LC BIT(3 )#define MLXPLAT_CPLD_AGGR_MASK_DPU_BRD BIT(4 )#define MLXPLAT_CPLD_AGGR_MASK_DPU_CORE BIT(5 )#define MLXPLAT_CPLD_AGGR_MASK_MODULAR (MLXPLAT_CPLD_AGGR_MASK_NG_DEF | \#define MLXPLAT_CPLD_AGGR_MASK_SMART_SW (MLXPLAT_CPLD_AGGR_MASK_COMEX | \#define MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT BIT(0 )#define MLXPLAT_CPLD_AGGR_MASK_LC_RDY BIT(1 )#define MLXPLAT_CPLD_AGGR_MASK_LC_PG BIT(2 )#define MLXPLAT_CPLD_AGGR_MASK_LC_SCRD BIT(3 )#define MLXPLAT_CPLD_AGGR_MASK_LC_SYNC BIT(4 )#define MLXPLAT_CPLD_AGGR_MASK_LC_ACT BIT(5 )#define MLXPLAT_CPLD_AGGR_MASK_LC_SDWN BIT(6 )#define MLXPLAT_CPLD_AGGR_MASK_LC_LOW (MLXPLAT_CPLD_AGGR_MASK_LC_PRSNT | \#define MLXPLAT_CPLD_LOW_AGGR_MASK_LOW 0 xc1#define MLXPLAT_CPLD_LOW_AGGR_MASK_ASIC2 BIT(2 )#define MLXPLAT_CPLD_LOW_AGGR_MASK_PWR_BUT GENMASK(5 , 4 )#define MLXPLAT_CPLD_LOW_AGGR_MASK_I2C BIT(6 )#define MLXPLAT_CPLD_PSU_MASK GENMASK(1 , 0 )#define MLXPLAT_CPLD_PWR_MASK GENMASK(1 , 0 )#define MLXPLAT_CPLD_PSU_EXT_MASK GENMASK(3 , 0 )#define MLXPLAT_CPLD_PWR_EXT_MASK GENMASK(3 , 0 )#define MLXPLAT_CPLD_PSU_XDR_MASK GENMASK(7 , 0 )#define MLXPLAT_CPLD_PWR_XDR_MASK GENMASK(7 , 0 )#define MLXPLAT_CPLD_FAN_MASK GENMASK(3 , 0 )#define MLXPLAT_CPLD_ASIC_MASK GENMASK(1 , 0 )#define MLXPLAT_CPLD_ASIC_XDR_MASK GENMASK(3 , 0 )#define MLXPLAT_CPLD_FAN_NG_MASK GENMASK(6 , 0 )#define MLXPLAT_CPLD_FAN_XDR_MASK GENMASK(7 , 0 )#define MLXPLAT_CPLD_LED_LO_NIBBLE_MASK GENMASK(7 , 4 )#define MLXPLAT_CPLD_LED_HI_NIBBLE_MASK GENMASK(3 , 0 )#define MLXPLAT_CPLD_VOLTREG_UPD_MASK GENMASK(5 , 4 )#define MLXPLAT_CPLD_GWP_MASK GENMASK(0 , 0 )#define MLXPLAT_CPLD_EROT_MASK GENMASK(1 , 0 )#define MLXPLAT_CPLD_FU_CAP_MASK GENMASK(1 , 0 )#define MLXPLAT_CPLD_BIOS_STATUS_MASK GENMASK(3 , 1 )#define MLXPLAT_CPLD_DPU_MASK GENMASK(3 , 0 )#define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0 )#define MLXPLAT_CPLD_LATCH_RST_MASK BIT(6 )#define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3 )#define MLXPLAT_CPLD_THERMAL2_PDB_MASK BIT(4 )#define MLXPLAT_CPLD_INTRUSION_MASK BIT(6 )#define MLXPLAT_CPLD_PWM_PG_MASK BIT(7 )#define MLXPLAT_CPLD_L1_CHA_HEALTH_MASK (MLXPLAT_CPLD_THERMAL1_PDB_MASK | \#define MLXPLAT_CPLD_I2C_CAP_BIT 0 x04#define MLXPLAT_CPLD_I2C_CAP_MASK GENMASK(5 , MLXPLAT_CPLD_I2C_CAP_BIT)#define MLXPLAT_CPLD_SYS_RESET_MASK BIT(0 )/* Masks for aggregation for comex carriers */ #define MLXPLAT_CPLD_AGGR_MASK_CARRIER BIT(1 )#define MLXPLAT_CPLD_AGGR_MASK_CARR_DEF (MLXPLAT_CPLD_AGGR_ASIC_MASK_DEF | \#define MLXPLAT_CPLD_LOW_AGGRCX_MASK 0 xc1/* Masks for aggregation for modular systems */ #define MLXPLAT_CPLD_LPC_LC_MASK GENMASK(7 , 0 )/* Masks for aggregation for smart switch systems */ #define MLXPLAT_CPLD_LPC_SM_SW_MASK GENMASK(7 , 0 )#define MLXPLAT_CPLD_HALT_MASK BIT(3 )#define MLXPLAT_CPLD_RESET_MASK GENMASK(7 , 1 )/* Default I2C parent bus number */ #define MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR 1 /* Maximum number of possible physical buses equipped on system */ #define MLXPLAT_CPLD_MAX_PHYS_ADAPTER_NUM 16 #define MLXPLAT_CPLD_MAX_PHYS_EXT_ADAPTER_NUM 24 /* Number of channels in group */ #define MLXPLAT_CPLD_GRP_CHNL_NUM 8 /* Start channel numbers */ #define MLXPLAT_CPLD_CH1 2 #define MLXPLAT_CPLD_CH2 10 #define MLXPLAT_CPLD_CH3 18 #define MLXPLAT_CPLD_CH2_ETH_MODULAR 3 #define MLXPLAT_CPLD_CH3_ETH_MODULAR 43 #define MLXPLAT_CPLD_CH4_ETH_MODULAR 51 #define MLXPLAT_CPLD_CH2_RACK_SWITCH 18 #define MLXPLAT_CPLD_CH2_NG800 34 /* Number of LPC attached MUX platform devices */ #define MLXPLAT_CPLD_LPC_MUX_DEVS 4 /* Hotplug devices adapter numbers */ #define MLXPLAT_CPLD_NR_NONE -1 #define MLXPLAT_CPLD_PSU_DEFAULT_NR 10 #define MLXPLAT_CPLD_PSU_MSNXXXX_NR 4 #define MLXPLAT_CPLD_PSU_XDR_NR 3 #define MLXPLAT_CPLD_FAN1_DEFAULT_NR 11 #define MLXPLAT_CPLD_FAN2_DEFAULT_NR 12 #define MLXPLAT_CPLD_FAN3_DEFAULT_NR 13 #define MLXPLAT_CPLD_FAN4_DEFAULT_NR 14 #define MLXPLAT_CPLD_NR_ASIC 3 #define MLXPLAT_CPLD_NR_LC_BASE 34 #define MLXPLAT_CPLD_NR_DPU_BASE 18 #define MLXPLAT_CPLD_NR_LC_SET(nr) (MLXPLAT_CPLD_NR_LC_BASE + (nr))#define MLXPLAT_CPLD_LC_ADDR 0 x32#define MLXPLAT_CPLD_DPU_ADDR 0 x68/* Masks and default values for watchdogs */ #define MLXPLAT_CPLD_WD1_CLEAR_MASK GENMASK(7 , 1 )#define MLXPLAT_CPLD_WD2_CLEAR_MASK (GENMASK(7 , 0 ) & ~BIT(1 ))#define MLXPLAT_CPLD_WD_TYPE1_TO_MASK GENMASK(7 , 4 )#define MLXPLAT_CPLD_WD_TYPE2_TO_MASK 0 #define MLXPLAT_CPLD_WD_RESET_ACT_MASK GENMASK(7 , 1 )#define MLXPLAT_CPLD_WD_FAN_ACT_MASK (GENMASK(7 , 0 ) & ~BIT(4 ))#define MLXPLAT_CPLD_WD_COUNT_ACT_MASK (GENMASK(7 , 0 ) & ~BIT(7 ))#define MLXPLAT_CPLD_WD_CPBLTY_MASK (GENMASK(7 , 0 ) & ~BIT(6 ))#define MLXPLAT_CPLD_WD_DFLT_TIMEOUT 30 #define MLXPLAT_CPLD_WD3_DFLT_TIMEOUT 600 #define MLXPLAT_CPLD_WD_MAX_DEVS 2 #define MLXPLAT_CPLD_DPU_MAX_DEVS 4 #define MLXPLAT_CPLD_LPC_SYSIRQ 17 /* Minimum power required for turning on Ethernet modular system (WATT) */ #define MLXPLAT_CPLD_ETH_MODULAR_PWR_MIN 50 /* Default value for PWM control register for rack switch system */ #define MLXPLAT_REGMAP_NVSWITCH_PWM_DEFAULT 0 xf4#define MLXPLAT_I2C_MAIN_BUS_NOTIFIED 0 x01#define MLXPLAT_I2C_MAIN_BUS_HANDLE_CREATED 0 x02/* Lattice FPGA PCI configuration */ #define PCI_VENDOR_ID_LATTICE 0 x1204#define PCI_DEVICE_ID_LATTICE_I2C_BRIDGE 0 x9c2f#define PCI_DEVICE_ID_LATTICE_JTAG_BRIDGE 0 x9c30#define PCI_DEVICE_ID_LATTICE_LPC_BRIDGE 0 x9c32/* mlxplat_priv - platform private data * @pdev_i2c - i2c controller platform device * @pdev_mux - array of mux platform devices * @pdev_hotplug - hotplug platform devices * @pdev_led - led platform devices * @pdev_io_regs - register access platform devices * @pdev_fan - FAN platform devices * @pdev_wd - array of watchdog platform devices * pdev_dpu - array of Data Processor Unit platform devices * @regmap: device register map * @hotplug_resources: system hotplug resources * @hotplug_resources_size: size of system hotplug resources * @hi2c_main_init_status: init status of I2C main bus * @irq_fpga: FPGA IRQ number struct mlxplat_priv {struct platform_device *pdev_i2c;struct platform_device *pdev_mux[MLXPLAT_CPLD_LPC_MUX_DEVS];struct platform_device *pdev_hotplug;struct platform_device *pdev_led;struct platform_device *pdev_io_regs;struct platform_device *pdev_fan;struct platform_device *pdev_wd[MLXPLAT_CPLD_WD_MAX_DEVS];struct platform_device *pdev_dpu[MLXPLAT_CPLD_DPU_MAX_DEVS];void *regmap;struct resource *hotplug_resources;unsigned int hotplug_resources_size;int irq_fpga;static struct platform_device *mlxplat_dev;static int mlxplat_i2c_main_completion_notify(void *handle, int id);static void __iomem *i2c_bridge_addr, *jtag_bridge_addr;/* Regions for LPC I2C controller and LPC base register space */ static const struct resource mlxplat_lpc_resources[] = {0 ] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_I2C_BASE_ADRR,"mlxplat_cpld_lpc_i2c_ctrl" , IORESOURCE_IO),1 ] = DEFINE_RES_NAMED(MLXPLAT_CPLD_LPC_REG_BASE_ADRR,"mlxplat_cpld_lpc_regs" ,/* Platform systems default i2c data */ static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_default_data = {/* Platform i2c next generation systems data */ static struct mlxreg_core_data mlxplat_mlxcpld_i2c_ng_items_data[] = {static struct mlxreg_core_item mlxplat_mlxcpld_i2c_ng_items[] = {/* Platform next generation systems i2c data */ static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_i2c_ng_data = {/* Platform default channels */ static const int mlxplat_default_channels[][MLXPLAT_CPLD_GRP_CHNL_NUM] = {1 , MLXPLAT_CPLD_CH1 + 2 ,3 , MLXPLAT_CPLD_CH1 + 4 , MLXPLAT_CPLD_CH1 +5 , MLXPLAT_CPLD_CH1 + 6 , MLXPLAT_CPLD_CH1 + 7 1 , MLXPLAT_CPLD_CH2 + 2 ,3 , MLXPLAT_CPLD_CH2 + 4 , MLXPLAT_CPLD_CH2 +5 , MLXPLAT_CPLD_CH2 + 6 , MLXPLAT_CPLD_CH2 + 7 /* Platform channels for MSN21xx system family */ static const int mlxplat_msn21xx_channels[] = { 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 };/* Platform mux data */ static struct i2c_mux_reg_platform_data mlxplat_default_mux_data[] = {1 ,1 ,void __iomem *)MLXPLAT_CPLD_LPC_REG1,1 ,1 ,1 ,1 ,void __iomem *)MLXPLAT_CPLD_LPC_REG2,1 ,1 ,/* Platform mux configuration variables */ static int mlxplat_max_adap_num;static int mlxplat_mux_num;static struct i2c_mux_reg_platform_data *mlxplat_mux_data;static struct notifier_block *mlxplat_reboot_nb;/* Platform extended mux data */ static struct i2c_mux_reg_platform_data mlxplat_extended_mux_data[] = {1 ,1 ,void __iomem *)MLXPLAT_CPLD_LPC_REG1,1 ,1 ,1 ,1 ,void __iomem *)MLXPLAT_CPLD_LPC_REG3,1 ,1 ,1 ,1 ,void __iomem *)MLXPLAT_CPLD_LPC_REG2,1 ,1 ,/* Platform channels for modular system family */ static const int mlxplat_modular_upper_channel[] = { 1 };static const int mlxplat_modular_channels[] = {1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 ,21 , 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 , 32 , 33 , 34 , 35 , 36 , 37 ,38 , 39 , 40 /* Platform modular mux data */ static struct i2c_mux_reg_platform_data mlxplat_modular_mux_data[] = {1 ,1 ,void __iomem *)MLXPLAT_CPLD_LPC_REG4,1 ,1 ,1 ,1 ,void __iomem *)MLXPLAT_CPLD_LPC_REG1,1 ,1 ,1 ,void __iomem *)MLXPLAT_CPLD_LPC_REG3,1 ,1 ,1 ,1 ,void __iomem *)MLXPLAT_CPLD_LPC_REG2,1 ,1 ,/* Platform channels for rack switch system family */ static const int mlxplat_rack_switch_channels[] = {1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 ,/* Platform rack switch mux data */ static struct i2c_mux_reg_platform_data mlxplat_rack_switch_mux_data[] = {1 ,1 ,void __iomem *)MLXPLAT_CPLD_LPC_REG1,1 ,1 ,1 ,1 ,void __iomem *)MLXPLAT_CPLD_LPC_REG2,1 ,1 ,/* Platform channels for ng800 system family */ static const int mlxplat_ng800_channels[] = {1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 ,18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 , 32 /* Platform ng800 mux data */ static struct i2c_mux_reg_platform_data mlxplat_ng800_mux_data[] = {1 ,1 ,void __iomem *)MLXPLAT_CPLD_LPC_REG1,1 ,1 ,1 ,1 ,void __iomem *)MLXPLAT_CPLD_LPC_REG2,1 ,1 ,/* Platform hotplug devices */ static struct i2c_board_info mlxplat_mlxcpld_pwr[] = {"dps460" , 0 x59),"dps460" , 0 x58),static struct i2c_board_info mlxplat_mlxcpld_ext_pwr[] = {"dps460" , 0 x5b),"dps460" , 0 x5a),static struct i2c_board_info mlxplat_mlxcpld_pwr_ng800[] = {"dps460" , 0 x59),"dps460" , 0 x5a),static struct i2c_board_info mlxplat_mlxcpld_xdr_pwr[] = {"dps460" , 0 x5d),"dps460" , 0 x5c),"dps460" , 0 x5e),"dps460" , 0 x5f),static struct i2c_board_info mlxplat_mlxcpld_fan[] = {"24c32" , 0 x50),"24c32" , 0 x50),"24c32" , 0 x50),"24c32" , 0 x50),/* Platform hotplug comex carrier system family data */ static struct mlxreg_core_data mlxplat_mlxcpld_comex_psu_items_data[] = {"psu1" ,0 ),"psu2" ,1 ),/* Platform hotplug default data */ static struct mlxreg_core_data mlxplat_mlxcpld_default_psu_items_data[] = {"psu1" ,0 ),"psu2" ,1 ),static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_items_data[] = {"pwr1" ,0 ),0 ],"pwr2" ,1 ),1 ],static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_wc_items_data[] = {"pwr1" ,0 ),"pwr2" ,1 ),static struct mlxreg_core_data mlxplat_mlxcpld_default_pwr_ng800_items_data[] = {"pwr1" ,0 ),0 ],"pwr2" ,1 ),1 ],static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_items_data[] = {"fan1" ,0 ),0 ],"fan2" ,1 ),1 ],"fan3" ,2 ),2 ],"fan4" ,3 ),3 ],static struct mlxreg_core_data mlxplat_mlxcpld_default_asic_items_data[] = {"asic1" ,static struct mlxreg_core_data mlxplat_mlxcpld_default_asic2_items_data[] = {"asic2" ,static struct mlxreg_core_item mlxplat_mlxcpld_default_items[] = {1 ,false ,0 ,false ,1 ,false ,0 ,true ,static struct mlxreg_core_item mlxplat_mlxcpld_comex_items[] = {1 ,false ,0 ,false ,1 ,false ,0 ,true ,static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_data = {static struct mlxreg_core_item mlxplat_mlxcpld_default_wc_items[] = {1 ,false ,0 ,false ,0 ,true ,static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_wc_data = {static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_comex_data = {static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_pwr_items_data[] = {"pwr1" ,0 ),"pwr2" ,1 ),/* Platform hotplug MSN21xx system family data */ static struct mlxreg_core_item mlxplat_mlxcpld_msn21xx_items[] = {0 ,false ,0 ,true ,static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn21xx_data = {/* Platform hotplug msn274x system family data */ static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_psu_items_data[] = {"psu1" ,0 ),"psu2" ,1 ),static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_pwr_items_data[] = {"pwr1" ,0 ),0 ],"pwr2" ,1 ),1 ],static struct mlxreg_core_data mlxplat_mlxcpld_msn274x_fan_items_data[] = {"fan1" ,0 ),"fan2" ,1 ),"fan3" ,2 ),"fan4" ,3 ),static struct mlxreg_core_item mlxplat_mlxcpld_msn274x_items[] = {1 ,false ,0 ,false ,1 ,false ,0 ,true ,static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn274x_data = {/* Platform hotplug MSN201x system family data */ static struct mlxreg_core_data mlxplat_mlxcpld_msn201x_pwr_items_data[] = {"pwr1" ,0 ),"pwr2" ,1 ),static struct mlxreg_core_item mlxplat_mlxcpld_msn201x_items[] = {0 ,false ,0 ,true ,static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_msn201x_data = {/* Platform hotplug next generation system family data */ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_psu_items_data[] = {"psu1" ,0 ),"psu2" ,1 ),static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_fan_items_data[] = {"fan1" ,0 ),0 ),"fan2" ,1 ),1 ),"fan3" ,2 ),2 ),"fan4" ,3 ),3 ),"fan5" ,4 ),4 ),"fan6" ,5 ),5 ),"fan7" ,6 ),6 ),static struct mlxreg_core_item mlxplat_mlxcpld_default_ng_items[] = {1 ,false ,0 ,false ,1 ,false ,0 ,true ,static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_default_ng_data = {/* Platform hotplug extended system family data */ static struct mlxreg_core_data mlxplat_mlxcpld_ext_psu_items_data[] = {"psu1" ,0 ),"psu2" ,1 ),"psu3" ,2 ),"psu4" ,3 ),static struct mlxreg_core_data mlxplat_mlxcpld_ext_pwr_items_data[] = {"pwr1" ,0 ),0 ],"pwr2" ,1 ),1 ],"pwr3" ,2 ),0 ],"pwr4" ,3 ),1 ],static struct mlxreg_core_item mlxplat_mlxcpld_ext_items[] = {1 ,false ,0 ,false ,1 ,false ,0 ,true ,0 ,true ,static struct mlxreg_core_item mlxplat_mlxcpld_ng800_items[] = {1 ,false ,0 ,false ,1 ,false ,0 ,true ,static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ext_data = {static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_data = {static struct mlxreg_core_data mlxplat_mlxcpld_modular_pwr_items_data[] = {"pwr1" ,0 ),0 ],"pwr2" ,1 ),1 ],"pwr3" ,2 ),0 ],"pwr4" ,3 ),1 ],static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_lc_act = {static struct mlxreg_core_data mlxplat_mlxcpld_modular_asic_items_data[] = {"asic1" ,static struct i2c_board_info mlxplat_mlxcpld_lc_i2c_dev[] = {"mlxreg-lc" , MLXPLAT_CPLD_LC_ADDR),"mlxreg-lc" , MLXPLAT_CPLD_LC_ADDR),"mlxreg-lc" , MLXPLAT_CPLD_LC_ADDR),"mlxreg-lc" , MLXPLAT_CPLD_LC_ADDR),"mlxreg-lc" , MLXPLAT_CPLD_LC_ADDR),"mlxreg-lc" , MLXPLAT_CPLD_LC_ADDR),"mlxreg-lc" , MLXPLAT_CPLD_LC_ADDR),"mlxreg-lc" , MLXPLAT_CPLD_LC_ADDR),static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_modular_lc_notifier[] = {"lc1" ,"lc2" ,"lc3" ,"lc4" ,"lc5" ,"lc6" ,"lc7" ,"lc8" ,static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pr_items_data[] = {"lc1_present" ,0 ),0 ],0 ),0 ],1 ,"lc2_present" ,1 ),1 ],1 ),1 ],2 ,"lc3_present" ,2 ),2 ],2 ),2 ],3 ,"lc4_present" ,3 ),3 ],3 ),3 ],4 ,"lc5_present" ,4 ),4 ],4 ),4 ],5 ,"lc6_present" ,5 ),5 ],5 ),5 ],6 ,"lc7_present" ,6 ),6 ],6 ),6 ],7 ,"lc8_present" ,7 ),7 ],7 ),7 ],8 ,static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ver_items_data[] = {"lc1_verified" ,0 ),0 ],0 ),0 ],1 ,"lc2_verified" ,1 ),1 ],1 ),1 ],2 ,"lc3_verified" ,2 ),2 ],2 ),2 ],3 ,"lc4_verified" ,3 ),3 ],3 ),3 ],4 ,"lc5_verified" ,4 ),4 ],4 ),4 ],5 ,"lc6_verified" ,5 ),5 ],5 ),5 ],6 ,"lc7_verified" ,6 ),6 ],6 ),6 ],7 ,"lc8_verified" ,7 ),7 ],7 ),7 ],8 ,static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_pg_data[] = {"lc1_powered" ,0 ),0 ],0 ),0 ],1 ,"lc2_powered" ,1 ),1 ],1 ),1 ],2 ,"lc3_powered" ,2 ),2 ],2 ),2 ],3 ,"lc4_powered" ,3 ),3 ],3 ),3 ],4 ,"lc5_powered" ,4 ),4 ],4 ),4 ],5 ,"lc6_powered" ,5 ),5 ],5 ),5 ],6 ,"lc7_powered" ,6 ),6 ],6 ),6 ],7 ,"lc8_powered" ,7 ),7 ],7 ),7 ],8 ,static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_ready_data[] = {"lc1_ready" ,0 ),0 ],0 ),0 ],1 ,"lc2_ready" ,1 ),1 ],1 ),1 ],2 ,"lc3_ready" ,2 ),2 ],2 ),2 ],3 ,"lc4_ready" ,3 ),3 ],3 ),3 ],4 ,"lc5_ready" ,4 ),4 ],4 ),4 ],5 ,"lc6_ready" ,5 ),5 ],5 ),5 ],6 ,"lc7_ready" ,6 ),6 ],6 ),6 ],7 ,"lc8_ready" ,7 ),7 ],7 ),7 ],8 ,static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_synced_data[] = {"lc1_synced" ,0 ),0 ],0 ),0 ],1 ,"lc2_synced" ,1 ),1 ],1 ),1 ],2 ,"lc3_synced" ,2 ),2 ],2 ),2 ],3 ,"lc4_synced" ,3 ),3 ],3 ),3 ],4 ,"lc5_synced" ,4 ),4 ],4 ),4 ],5 ,"lc6_synced" ,5 ),5 ],5 ),5 ],6 ,"lc7_synced" ,6 ),6 ],6 ),6 ],7 ,"lc8_synced" ,7 ),7 ],7 ),7 ],8 ,static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_act_data[] = {"lc1_active" ,0 ),0 ],0 ),0 ],1 ,"lc2_active" ,1 ),1 ],1 ),1 ],2 ,"lc3_active" ,2 ),2 ],2 ),2 ],3 ,"lc4_active" ,3 ),3 ],3 ),3 ],4 ,"lc5_active" ,4 ),4 ],4 ),4 ],5 ,"lc6_active" ,5 ),5 ],5 ),5 ],6 ,"lc7_active" ,6 ),6 ],6 ),6 ],7 ,"lc8_active" ,7 ),7 ],7 ),7 ],8 ,static struct mlxreg_core_data mlxplat_mlxcpld_modular_lc_sd_data[] = {"lc1_shutdown" ,0 ),0 ],0 ),0 ],1 ,"lc2_shutdown" ,1 ),1 ],1 ),1 ],2 ,"lc3_shutdown" ,2 ),2 ],2 ),2 ],3 ,"lc4_shutdown" ,3 ),3 ],3 ),3 ],4 ,"lc5_shutdown" ,4 ),4 ],4 ),4 ],5 ,"lc6_shutdown" ,5 ),5 ],5 ),5 ],6 ,"lc7_shutdown" ,6 ),6 ],6 ),6 ],7 ,"lc8_shutdown" ,7 ),7 ],7 ),7 ],8 ,static struct mlxreg_core_item mlxplat_mlxcpld_modular_items[] = {1 ,false ,0 ,false ,1 ,false ,0 ,true ,1 ,false ,0 ,false ,0 ,false ,0 ,false ,0 ,false ,0 ,false ,0 ,false ,static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_modular_data = {/* Platform hotplug for NVLink blade systems family data */ static struct mlxreg_core_data mlxplat_mlxcpld_global_wp_items_data[] = {"global_wp_grant" ,static struct mlxreg_core_item mlxplat_mlxcpld_chassis_blade_items[] = {0 ,false ,static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_chassis_blade_data = {/* Platform hotplug for switch systems family data */ static struct mlxreg_core_data mlxplat_mlxcpld_erot_ap_items_data[] = {"erot1_ap" ,0 ),"erot2_ap" ,1 ),static struct mlxreg_core_data mlxplat_mlxcpld_erot_error_items_data[] = {"erot1_error" ,0 ),"erot2_error" ,1 ),static struct mlxreg_core_item mlxplat_mlxcpld_rack_switch_items[] = {1 ,false ,0 ,false ,1 ,false ,1 ,false ,1 ,false ,static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_rack_switch_data = {/* Platform hotplug XDR and smart switch system family data */ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_psu_items_data[] = {"psu1" ,0 ),1 ,"psu2" ,1 ),2 ,"psu3" ,2 ),3 ,"psu4" ,3 ),4 ,"psu5" ,4 ),5 ,"psu6" ,5 ),6 ,"psu7" ,6 ),7 ,"psu8" ,7 ),8 ,static struct mlxreg_core_data mlxplat_mlxcpld_xdr_pwr_items_data[] = {"pwr1" ,0 ),1 ,0 ],"pwr2" ,1 ),2 ,1 ],"pwr3" ,2 ),3 ,0 ],"pwr4" ,3 ),4 ,1 ],"pwr5" ,4 ),5 ,0 ],"pwr6" ,5 ),6 ,1 ],"pwr7" ,6 ),7 ,2 ],"pwr8" ,7 ),8 ,3 ],static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_items_data[] = {"fan1" ,0 ),1 ,0 ),"fan2" ,1 ),2 ,1 ),"fan3" ,2 ),3 ,2 ),"fan4" ,3 ),4 ,3 ),"fan5" ,4 ),5 ,4 ),"fan6" ,5 ),6 ,5 ),"fan7" ,6 ),7 ,6 ),"fan8" ,7 ),8 ,7 ),static struct mlxreg_core_data mlxplat_mlxcpld_xdr_asic1_items_data[] = {"asic1" ,1 ,/* Platform hotplug for smart switch systems families data */ static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_ready_data[] = {"dpu1_ready" ,0 ),1 ,"dpu2_ready" ,1 ),2 ,"dpu3_ready" ,2 ),3 ,"dpu4_ready" ,3 ),4 ,static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_shtdn_ready_data[] = {"dpu1_shtdn_ready" ,0 ),1 ,"dpu2_shtdn_ready" ,1 ),2 ,"dpu3_shtdn_ready" ,2 ),3 ,"dpu4_shtdn_ready" ,3 ),4 ,static struct mlxreg_core_item mlxplat_mlxcpld_smart_switch_items[] = {1 ,false ,0 ,false ,1 ,false ,0 ,true ,1 ,false ,1 ,false ,static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_smart_switch_data = {/* Smart switch data processor units data */ static struct i2c_board_info mlxplat_mlxcpld_smart_switch_dpu_devs[] = {"mlxreg-dpu" , MLXPLAT_CPLD_DPU_ADDR),"mlxreg-dpu" , MLXPLAT_CPLD_DPU_ADDR),"mlxreg-dpu" , MLXPLAT_CPLD_DPU_ADDR),"mlxreg-dpu" , MLXPLAT_CPLD_DPU_ADDR),static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_dpu_data[] = {"dpu1" ,0 ],1 ,"dpu2" ,1 ],1 ,2 ,"dpu3" ,2 ],2 ,3 ,"dpu4" ,3 ],3 ,4 ,/* Callback performs graceful shutdown after notification about power button event */ static int void *handle, enum mlxreg_hotplug_kind kind,if (action) {"System shutdown due to short press of power button" );return 0 ;static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_pwr_events_notifier = {/* Platform hotplug for l1 switch systems family data */ static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_pwr_events_items_data[] = {"power_button" ,/* Callback activates latch reset flow after notification about intrusion event */ static int void *handle, enum mlxreg_hotplug_kind kind,struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);int err;if (err)goto fail_regmap_read;if (action) {"Detected intrusion - system latch is opened" );else {"System latch is properly closed" );if (err)goto fail_regmap_write;return 0 ;"Register access failed" );return err;static struct mlxreg_core_hotplug_notifier mlxplat_mlxcpld_l1_switch_intrusion_events_notifier = {static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_health_events_items_data[] = {"thermal1_pdb" ,"thermal2_pdb" ,"intrusion" ,"pwm_pg" ,static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = {1 ,false ,1 ,false ,1 ,false ,1 ,false ,1 ,false ,8 ,static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_l1_switch_data = {/* Platform hotplug for 800G systems family data */ static struct mlxreg_core_item mlxplat_mlxcpld_ng800_hi171_items[] = {1 ,false ,0 ,false ,1 ,false ,0 ,true ,static struct mlxreg_core_hotplug_platform_data mlxplat_mlxcpld_ng800_hi171_data = {/* Platform led default data */ static struct mlxreg_core_data mlxplat_mlxcpld_default_led_data[] = {"status:green" ,"status:red" ,"psu:green" ,"psu:red" ,"fan1:green" ,"fan1:red" ,"fan2:green" ,"fan2:red" ,"fan3:green" ,"fan3:red" ,"fan4:green" ,"fan4:red" ,static struct mlxreg_core_platform_data mlxplat_default_led_data = {/* Platform led default data for water cooling */ static struct mlxreg_core_data mlxplat_mlxcpld_default_led_wc_data[] = {"status:green" ,"status:red" ,"psu:green" ,"psu:red" ,static struct mlxreg_core_platform_data mlxplat_default_led_wc_data = {/* Platform led default data for water cooling Ethernet switch blade */ static struct mlxreg_core_data mlxplat_mlxcpld_default_led_eth_wc_blade_data[] = {"status:green" ,"status:red" ,static struct mlxreg_core_platform_data mlxplat_default_led_eth_wc_blade_data = {/* Platform led MSN21xx system family data */ static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_led_data[] = {"status:green" ,"status:red" ,"fan:green" ,"fan:red" ,"psu1:green" ,"psu1:red" ,"psu2:green" ,"psu2:red" ,"uid:blue" ,static struct mlxreg_core_platform_data mlxplat_msn21xx_led_data = {/* Platform led for default data for 200GbE systems */ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_led_data[] = {"status:green" ,"status:orange" ,"psu:green" ,"psu:orange" ,"fan1:green" ,0 ),"fan1:orange" ,0 ),"fan2:green" ,1 ),"fan2:orange" ,1 ),"fan3:green" ,2 ),"fan3:orange" ,2 ),"fan4:green" ,3 ),"fan4:orange" ,3 ),"fan5:green" ,4 ),"fan5:orange" ,4 ),"fan6:green" ,5 ),"fan6:orange" ,5 ),"fan7:green" ,6 ),"fan7:orange" ,6 ),"uid:blue" ,static struct mlxreg_core_platform_data mlxplat_default_ng_led_data = {/* Platform led for Comex based 100GbE systems */ static struct mlxreg_core_data mlxplat_mlxcpld_comex_100G_led_data[] = {"status:green" ,"status:red" ,"psu:green" ,"psu:red" ,"fan1:green" ,"fan1:red" ,"fan2:green" ,"fan2:red" ,"fan3:green" ,"fan3:red" ,"fan4:green" ,"fan4:red" ,"uid:blue" ,static struct mlxreg_core_platform_data mlxplat_comex_100G_led_data = {/* Platform led for data for modular systems */ static struct mlxreg_core_data mlxplat_mlxcpld_modular_led_data[] = {"status:green" ,"status:orange" ,"psu:green" ,"psu:orange" ,"fan1:green" ,0 ),"fan1:orange" ,0 ),"fan2:green" ,1 ),"fan2:orange" ,1 ),"fan3:green" ,2 ),"fan3:orange" ,2 ),"fan4:green" ,3 ),"fan4:orange" ,3 ),"fan5:green" ,4 ),"fan5:orange" ,4 ),"fan6:green" ,5 ),"fan6:orange" ,5 ),"fan7:green" ,6 ),"fan7:orange" ,6 ),"uid:blue" ,"fan_front:green" ,"fan_front:orange" ,"mgmt:green" ,"mgmt:orange" ,static struct mlxreg_core_platform_data mlxplat_modular_led_data = {/* Platform led data for chassis system */ static struct mlxreg_core_data mlxplat_mlxcpld_l1_switch_led_data[] = {"status:green" ,"status:orange" ,"fan1:green" ,0 ),"fan1:orange" ,0 ),"fan2:green" ,1 ),"fan2:orange" ,1 ),"fan3:green" ,2 ),"fan3:orange" ,2 ),"fan4:green" ,3 ),"fan4:orange" ,3 ),"fan5:green" ,4 ),"fan5:orange" ,4 ),"fan6:green" ,5 ),"fan6:orange" ,5 ),"uid:blue" ,static struct mlxreg_core_platform_data mlxplat_l1_switch_led_data = {/* Platform led data for XDR and smart switch systems */ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_led_data[] = {"status:green" ,"status:orange" ,"psu:green" ,"psu:orange" ,"fan1:green" ,1 ,"fan1:orange" ,1 ,"fan2:green" ,2 ,"fan2:orange" ,2 ,"fan3:green" ,3 ,"fan3:orange" ,3 ,"fan4:green" ,4 ,"fan4:orange" ,4 ,"fan5:green" ,5 ,"fan5:orange" ,5 ,"fan6:green" ,6 ,"fan6:orange" ,6 ,"fan7:green" ,7 ,"fan7:orange" ,7 ,"fan8:green" ,8 ,"fan8:orange" ,8 ,"fan9:green" ,9 ,"fan9:orange" ,9 ,"fan10:green" ,10 ,"fan10:orange" ,10 ,"uid:blue" ,static struct mlxreg_core_platform_data mlxplat_xdr_led_data = {/* Platform register access default */ static struct mlxreg_core_data mlxplat_mlxcpld_default_regs_io_data[] = {"cpld1_version" ,7 , 0 ),0444 ,"cpld2_version" ,7 , 0 ),0444 ,"cpld1_pn" ,15 , 0 ),0444 ,2 ,"cpld2_pn" ,15 , 0 ),0444 ,2 ,"cpld1_version_min" ,7 , 0 ),0444 ,"cpld2_version_min" ,7 , 0 ),0444 ,"reset_long_pb" ,7 , 0 ) & ~BIT(0 ),0444 ,"reset_short_pb" ,7 , 0 ) & ~BIT(1 ),0444 ,"reset_aux_pwr_or_ref" ,7 , 0 ) & ~BIT(2 ),0444 ,"reset_main_pwr_fail" ,7 , 0 ) & ~BIT(3 ),0444 ,"reset_sw_reset" ,7 , 0 ) & ~BIT(4 ),0444 ,"reset_fw_reset" ,7 , 0 ) & ~BIT(5 ),0444 ,"reset_hotswap_or_wd" ,7 , 0 ) & ~BIT(6 ),0444 ,"reset_asic_thermal" ,7 , 0 ) & ~BIT(7 ),0444 ,"psu1_on" ,7 , 0 ) & ~BIT(0 ),0200 ,"psu2_on" ,7 , 0 ) & ~BIT(1 ),0200 ,"pwr_cycle" ,7 , 0 ) & ~BIT(2 ),0200 ,"pwr_down" ,7 , 0 ) & ~BIT(3 ),0200 ,"select_iio" ,7 , 0 ) & ~BIT(6 ),0644 ,"asic_health" ,1 ,0444 ,static struct mlxreg_core_platform_data mlxplat_default_regs_io_data = {/* Platform register access MSN21xx, MSN201x, MSN274x systems families data */ static struct mlxreg_core_data mlxplat_mlxcpld_msn21xx_regs_io_data[] = {"cpld1_version" ,7 , 0 ),0444 ,"cpld2_version" ,7 , 0 ),0444 ,"cpld1_pn" ,15 , 0 ),0444 ,2 ,"cpld2_pn" ,15 , 0 ),0444 ,2 ,"cpld1_version_min" ,7 , 0 ),0444 ,"cpld2_version_min" ,7 , 0 ),0444 ,"reset_long_pb" ,7 , 0 ) & ~BIT(0 ),0444 ,"reset_short_pb" ,7 , 0 ) & ~BIT(1 ),0444 ,"reset_aux_pwr_or_ref" ,7 , 0 ) & ~BIT(2 ),0444 ,"reset_sw_reset" ,7 , 0 ) & ~BIT(3 ),0444 ,"reset_main_pwr_fail" ,7 , 0 ) & ~BIT(4 ),0444 ,"reset_asic_thermal" ,7 , 0 ) & ~BIT(5 ),0444 ,"reset_hotswap_or_halt" ,7 , 0 ) & ~BIT(6 ),0444 ,"reset_sff_wd" ,7 , 0 ) & ~BIT(6 ),0444 ,"psu1_on" ,7 , 0 ) & ~BIT(0 ),0200 ,"psu2_on" ,7 , 0 ) & ~BIT(1 ),0200 ,"pwr_cycle" ,7 , 0 ) & ~BIT(2 ),0200 ,"pwr_down" ,7 , 0 ) & ~BIT(3 ),0200 ,"select_iio" ,7 , 0 ) & ~BIT(6 ),0644 ,"asic_health" ,1 ,0444 ,static struct mlxreg_core_platform_data mlxplat_msn21xx_regs_io_data = {/* Platform register access for next generation systems families data */ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {"cpld1_version" ,7 , 0 ),0444 ,"cpld2_version" ,7 , 0 ),0444 ,"cpld3_version" ,7 , 0 ),0444 ,"cpld4_version" ,7 , 0 ),0444 ,"cpld5_version" ,7 , 0 ),0444 ,"cpld1_pn" ,15 , 0 ),0444 ,2 ,"cpld2_pn" ,15 , 0 ),0444 ,2 ,"cpld3_pn" ,15 , 0 ),0444 ,2 ,"cpld4_pn" ,15 , 0 ),0444 ,2 ,"cpld5_pn" ,15 , 0 ),0444 ,2 ,"cpld1_version_min" ,7 , 0 ),0444 ,"cpld2_version_min" ,7 , 0 ),0444 ,"cpld3_version_min" ,7 , 0 ),0444 ,"cpld4_version_min" ,7 , 0 ),0444 ,"cpld5_version_min" ,7 , 0 ),0444 ,"asic_reset" ,7 , 0 ) & ~BIT(3 ),0200 ,"asic2_reset" ,7 , 0 ) & ~BIT(2 ),0200 ,"erot1_reset" ,7 , 0 ) & ~BIT(6 ),0644 ,"erot2_reset" ,7 , 0 ) & ~BIT(7 ),0644 ,"clk_brd_prog_en" ,7 , 0 ) & ~BIT(1 ),0644 ,1 ,"erot1_recovery" ,7 , 0 ) & ~BIT(6 ),0644 ,"erot2_recovery" ,7 , 0 ) & ~BIT(7 ),0644 ,"erot1_wp" ,7 , 0 ) & ~BIT(4 ),0644 ,1 ,"erot2_wp" ,7 , 0 ) & ~BIT(5 ),0644 ,1 ,"reset_long_pb" ,7 , 0 ) & ~BIT(0 ),0444 ,"reset_short_pb" ,7 , 0 ) & ~BIT(1 ),0444 ,"reset_aux_pwr_or_ref" ,7 , 0 ) & ~BIT(2 ),0444 ,"reset_swb_dc_dc_pwr_fail" ,7 , 0 ) & ~BIT(3 ),0444 ,"reset_from_asic" ,7 , 0 ) & ~BIT(5 ),0444 ,"reset_swb_wd" ,7 , 0 ) & ~BIT(6 ),0444 ,"reset_asic_thermal" ,7 , 0 ) & ~BIT(7 ),0444 ,"reset_sw_reset" ,7 , 0 ) & ~BIT(0 ),0444 ,"reset_comex_pwr_fail" ,7 , 0 ) & ~BIT(3 ),0444 ,"reset_platform" ,7 , 0 ) & ~BIT(4 ),0444 ,"reset_soc" ,7 , 0 ) & ~BIT(5 ),0444 ,"reset_comex_wd" ,7 , 0 ) & ~BIT(6 ),0444 ,"reset_pwr_converter_fail" ,7 , 0 ) & ~BIT(0 ),0444 ,"reset_system" ,7 , 0 ) & ~BIT(1 ),0444 ,"reset_sw_pwr_off" ,7 , 0 ) & ~BIT(2 ),0444 ,"reset_comex_thermal" ,7 , 0 ) & ~BIT(3 ),0444 ,"reset_reload_bios" ,7 , 0 ) & ~BIT(5 ),0444 ,"reset_ac_pwr_fail" ,7 , 0 ) & ~BIT(6 ),0444 ,"reset_ac_ok_fail" ,7 , 0 ) & ~BIT(7 ),0444 ,"psu1_on" ,7 , 0 ) & ~BIT(0 ),0200 ,"psu2_on" ,7 , 0 ) & ~BIT(1 ),0200 ,"pwr_cycle" ,7 , 0 ) & ~BIT(2 ),0200 ,"pwr_down" ,7 , 0 ) & ~BIT(3 ),0200 ,"deep_pwr_cycle" ,7 , 0 ) & ~BIT(5 ),0200 ,"latch_reset" ,7 , 0 ) & ~BIT(6 ),0200 ,"jtag_cap" ,1 ,0444 ,"jtag_enable" ,7 , 0 ) & ~BIT(4 ),0644 ,"dbg1" ,7 , 0 ),0644 ,"dbg2" ,7 , 0 ),0644 ,"dbg3" ,7 , 0 ),0644 ,"dbg4" ,7 , 0 ),0644 ,"asic_health" ,1 ,0444 ,"asic2_health" ,1 ,0444 ,"fan_dir" ,7 , 0 ),0444 ,"bios_safe_mode" ,7 , 0 ) & ~BIT(4 ),0444 ,"bios_active_image" ,7 , 0 ) & ~BIT(5 ),0444 ,"bios_auth_fail" ,7 , 0 ) & ~BIT(6 ),0444 ,"bios_upgrade_fail" ,7 , 0 ) & ~BIT(7 ),0444 ,"voltreg_update_status" ,5 ,0444 ,"pwr_converter_prog_en" ,7 , 0 ) & ~BIT(0 ),0644 ,1 ,"vpd_wp" ,7 , 0 ) & ~BIT(3 ),0644 ,"pcie_asic_reset_dis" ,7 , 0 ) & ~BIT(4 ),0644 ,"shutdown_unlock" ,7 , 0 ) & ~BIT(5 ),0644 ,"erot1_ap_reset" ,7 , 0 ) & ~BIT(0 ),0444 ,"erot2_ap_reset" ,7 , 0 ) & ~BIT(1 ),0444 ,"lid_open" ,7 , 0 ) & ~BIT(2 ),0444 ,"clk_brd1_boot_fail" ,7 , 0 ) & ~BIT(4 ),0444 ,"clk_brd2_boot_fail" ,7 , 0 ) & ~BIT(5 ),0444 ,"clk_brd_fail" ,7 , 0 ) & ~BIT(6 ),0444 ,"asic_pg_fail" ,7 , 0 ) & ~BIT(7 ),0444 ,"spi_chnl_select" ,7 , 0 ),1 ,0644 ,"config1" ,7 , 0 ),0444 ,"config2" ,7 , 0 ),0444 ,"config3" ,7 , 0 ),0444 ,"ufm_version" ,7 , 0 ),0444 ,static struct mlxreg_core_platform_data mlxplat_default_ng_regs_io_data = {/* Platform register access for modular systems families data */ static struct mlxreg_core_data mlxplat_mlxcpld_modular_regs_io_data[] = {"cpld1_version" ,7 , 0 ),0444 ,"cpld2_version" ,7 , 0 ),0444 ,"cpld3_version" ,7 , 0 ),0444 ,"cpld4_version" ,7 , 0 ),0444 ,"cpld1_pn" ,15 , 0 ),0444 ,2 ,"cpld2_pn" ,15 , 0 ),0444 ,2 ,"cpld3_pn" ,15 , 0 ),0444 ,2 ,"cpld4_pn" ,15 , 0 ),0444 ,2 ,"cpld1_version_min" ,7 , 0 ),0444 ,"cpld2_version_min" ,7 , 0 ),0444 ,"cpld3_version_min" ,7 , 0 ),0444 ,"cpld4_version_min" ,7 , 0 ),0444 ,"lc1_enable" ,7 , 0 ) & ~BIT(0 ),0644 ,"lc2_enable" ,7 , 0 ) & ~BIT(1 ),0644 ,"lc3_enable" ,7 , 0 ) & ~BIT(2 ),0644 ,"lc4_enable" ,7 , 0 ) & ~BIT(3 ),0644 ,"lc5_enable" ,7 , 0 ) & ~BIT(4 ),0644 ,"lc6_enable" ,7 , 0 ) & ~BIT(5 ),0644 ,"lc7_enable" ,7 , 0 ) & ~BIT(6 ),0644 ,"lc8_enable" ,7 , 0 ) & ~BIT(7 ),0644 ,"reset_long_pb" ,7 , 0 ) & ~BIT(0 ),0444 ,"reset_short_pb" ,7 , 0 ) & ~BIT(1 ),0444 ,"reset_aux_pwr_or_fu" ,7 , 0 ) & ~BIT(2 ),0444 ,"reset_mgmt_dc_dc_pwr_fail" ,7 , 0 ) & ~BIT(3 ),0444 ,"reset_sys_comex_bios" ,7 , 0 ) & ~BIT(5 ),0444 ,"reset_sw_reset" ,7 , 0 ) & ~BIT(0 ),0444 ,"reset_aux_pwr_or_reload" ,7 , 0 ) & ~BIT(2 ),0444 ,"reset_comex_pwr_fail" ,7 , 0 ) & ~BIT(3 ),0444 ,"reset_platform" ,7 , 0 ) & ~BIT(4 ),0444 ,"reset_soc" ,7 , 0 ) & ~BIT(5 ),0444 ,"reset_pwr_off_from_carrier" ,7 , 0 ) & ~BIT(7 ),0444 ,"reset_swb_wd" ,7 , 0 ) & ~BIT(0 ),0444 ,"reset_swb_aux_pwr_or_fu" ,7 , 0 ) & ~BIT(2 ),0444 ,"reset_swb_dc_dc_pwr_fail" ,7 , 0 ) & ~BIT(3 ),0444 ,"reset_swb_12v_fail" ,7 , 0 ) & ~BIT(4 ),0444 ,"reset_system" ,7 , 0 ) & ~BIT(5 ),0444 ,"reset_thermal_spc_or_pciesw" ,7 , 0 ) & ~BIT(7 ),0444 ,"bios_safe_mode" ,7 , 0 ) & ~BIT(4 ),0444 ,"bios_active_image" ,7 , 0 ) & ~BIT(5 ),0444 ,"bios_auth_fail" ,7 , 0 ) & ~BIT(6 ),0444 ,"bios_upgrade_fail" ,7 , 0 ) & ~BIT(7 ),0444 ,"voltreg_update_status" ,5 ,0444 ,"vpd_wp" ,7 , 0 ) & ~BIT(3 ),0644 ,"pcie_asic_reset_dis" ,7 , 0 ) & ~BIT(4 ),0644 ,"shutdown_unlock" ,7 , 0 ) & ~BIT(5 ),0644 ,"lc1_rst_mask" ,7 , 0 ) & ~BIT(0 ),0200 ,"lc2_rst_mask" ,7 , 0 ) & ~BIT(1 ),0200 ,"lc3_rst_mask" ,7 , 0 ) & ~BIT(2 ),0200 ,"lc4_rst_mask" ,7 , 0 ) & ~BIT(3 ),0200 ,"lc5_rst_mask" ,7 , 0 ) & ~BIT(4 ),0200 ,"lc6_rst_mask" ,7 , 0 ) & ~BIT(5 ),0200 ,"lc7_rst_mask" ,7 , 0 ) & ~BIT(6 ),0200 ,"lc8_rst_mask" ,7 , 0 ) & ~BIT(7 ),0200 ,"psu1_on" ,7 , 0 ) & ~BIT(0 ),0200 ,"psu2_on" ,7 , 0 ) & ~BIT(1 ),0200 ,"pwr_cycle" ,7 , 0 ) & ~BIT(2 ),0200 ,"pwr_down" ,7 , 0 ) & ~BIT(3 ),0200 ,"psu3_on" ,7 , 0 ) & ~BIT(4 ),0200 ,"psu4_on" ,7 , 0 ) & ~BIT(5 ),0200 ,"auto_power_mode" ,7 , 0 ) & ~BIT(6 ),0644 ,"pm_mgmt_en" ,7 , 0 ) & ~BIT(7 ),0644 ,"jtag_enable" ,3 , 0 ),1 ,0644 ,"safe_bios_dis" ,7 , 0 ) & ~BIT(5 ),0644 ,"safe_bios_dis_wp" ,7 , 0 ) & ~BIT(5 ),0644 ,"asic_health" ,1 ,0444 ,"fan_dir" ,7 , 0 ),0444 ,"lc1_pwr" ,7 , 0 ) & ~BIT(0 ),0644 ,"lc2_pwr" ,7 , 0 ) & ~BIT(1 ),0644 ,"lc3_pwr" ,7 , 0 ) & ~BIT(2 ),0644 ,"lc4_pwr" ,7 , 0 ) & ~BIT(3 ),0644 ,"lc5_pwr" ,7 , 0 ) & ~BIT(4 ),0644 ,"lc6_pwr" ,7 , 0 ) & ~BIT(5 ),0644 ,"lc7_pwr" ,7 , 0 ) & ~BIT(6 ),0644 ,"lc8_pwr" ,7 , 0 ) & ~BIT(7 ),0644 ,"config1" ,7 , 0 ),0444 ,"config2" ,7 , 0 ),0444 ,"config3" ,7 , 0 ),0444 ,"ufm_version" ,7 , 0 ),0444 ,static struct mlxreg_core_platform_data mlxplat_modular_regs_io_data = {/* Platform register access for chassis blade systems family data */ static struct mlxreg_core_data mlxplat_mlxcpld_chassis_blade_regs_io_data[] = {"cpld1_version" ,7 , 0 ),0444 ,"cpld1_pn" ,15 , 0 ),0444 ,2 ,"cpld1_version_min" ,7 , 0 ),0444 ,"reset_aux_pwr_or_ref" ,7 , 0 ) & ~BIT(2 ),0444 ,"reset_from_comex" ,7 , 0 ) & ~BIT(4 ),0444 ,"reset_comex_pwr_fail" ,7 , 0 ) & ~BIT(3 ),0444 ,"reset_platform" ,7 , 0 ) & ~BIT(4 ),0444 ,"reset_soc" ,7 , 0 ) & ~BIT(5 ),0444 ,"reset_comex_wd" ,7 , 0 ) & ~BIT(6 ),0444 ,"reset_voltmon_upgrade_fail" ,7 , 0 ) & ~BIT(0 ),0444 ,"reset_system" ,7 , 0 ) & ~BIT(1 ),0444 ,"reset_sw_pwr_off" ,7 , 0 ) & ~BIT(2 ),0444 ,"reset_comex_thermal" ,7 , 0 ) & ~BIT(3 ),0444 ,"reset_reload_bios" ,7 , 0 ) & ~BIT(5 ),0444 ,"reset_ac_pwr_fail" ,7 , 0 ) & ~BIT(6 ),0444 ,"reset_long_pwr_pb" ,7 , 0 ) & ~BIT(7 ),0444 ,"pwr_cycle" ,7 , 0 ) & ~BIT(2 ),0200 ,"pwr_down" ,7 , 0 ) & ~BIT(3 ),0200 ,"global_wp_request" ,7 , 0 ) & ~BIT(0 ),0644 ,"jtag_enable" ,7 , 0 ) & ~BIT(4 ),0644 ,"comm_chnl_ready" ,7 , 0 ) & ~BIT(6 ),0200 ,"bios_safe_mode" ,7 , 0 ) & ~BIT(4 ),0444 ,"bios_active_image" ,7 , 0 ) & ~BIT(5 ),0444 ,"bios_auth_fail" ,7 , 0 ) & ~BIT(6 ),0444 ,"bios_upgrade_fail" ,7 , 0 ) & ~BIT(7 ),0444 ,"voltreg_update_status" ,5 ,0444 ,"vpd_wp" ,7 , 0 ) & ~BIT(3 ),0644 ,"pcie_asic_reset_dis" ,7 , 0 ) & ~BIT(4 ),0644 ,"global_wp_response" ,7 , 0 ) & ~BIT(0 ),0444 ,"config1" ,7 , 0 ),0444 ,"config2" ,7 , 0 ),0444 ,"config3" ,7 , 0 ),0444 ,"ufm_version" ,7 , 0 ),0444 ,static struct mlxreg_core_platform_data mlxplat_chassis_blade_regs_io_data = {/* Platform register access for smart switch systems families data */ static struct mlxreg_core_data mlxplat_mlxcpld_smart_switch_regs_io_data[] = {"cpld1_version" ,7 , 0 ),0444 ,"cpld2_version" ,7 , 0 ),0444 ,"cpld3_version" ,7 , 0 ),0444 ,"cpld1_pn" ,15 , 0 ),0444 ,2 ,"cpld2_pn" ,15 , 0 ),0444 ,2 ,"cpld3_pn" ,15 , 0 ),0444 ,2 ,"cpld1_version_min" ,7 , 0 ),0444 ,"cpld2_version_min" ,7 , 0 ),0444 ,"cpld3_version_min" ,7 , 0 ),0444 ,"kexec_activated" ,7 , 0 ) & ~BIT(1 ),0644 ,"asic_reset" ,7 , 0 ) & ~BIT(3 ),0644 ,"eth_switch_reset" ,7 , 0 ) & ~BIT(4 ),0644 ,"dpu1_rst" ,7 , 0 ) & ~BIT(0 ),0200 ,"dpu2_rst" ,7 , 0 ) & ~BIT(1 ),0200 ,"dpu3_rst" ,7 , 0 ) & ~BIT(2 ),0200 ,"dpu4_rst" ,7 , 0 ) & ~BIT(3 ),0200 ,"dpu1_pwr" ,7 , 0 ) & ~BIT(0 ),0200 ,"dpu2_pwr" ,7 , 0 ) & ~BIT(1 ),0200 ,"dpu3_pwr" ,7 , 0 ) & ~BIT(2 ),0200 ,"dpu4_pwr" ,7 , 0 ) & ~BIT(3 ),0200 ,"reset_long_pb" ,7 , 0 ) & ~BIT(0 ),0444 ,"reset_short_pb" ,7 , 0 ) & ~BIT(1 ),0444 ,"reset_aux_pwr_or_ref" ,7 , 0 ) & ~BIT(2 ),0444 ,"reset_swb_dc_dc_pwr_fail" ,7 , 0 ) & ~BIT(3 ),0444 ,"reset_swb_wd" ,7 , 0 ) & ~BIT(6 ),0444 ,"reset_asic_thermal" ,7 , 0 ) & ~BIT(7 ),0444 ,"reset_sw_reset" ,7 , 0 ) & ~BIT(0 ),0444 ,"reset_aux_pwr_or_reload" ,7 , 0 ) & ~BIT(2 ),0444 ,"reset_comex_pwr_fail" ,7 , 0 ) & ~BIT(3 ),0444 ,"reset_platform" ,7 , 0 ) & ~BIT(4 ),0444 ,"reset_soc" ,7 , 0 ) & ~BIT(5 ),0444 ,"reset_pwr" ,7 , 0 ) & ~BIT(7 ),0444 ,"reset_pwr_converter_fail" ,7 , 0 ) & ~BIT(0 ),0444 ,"reset_system" ,7 , 0 ) & ~BIT(1 ),0444 ,"reset_sw_pwr_off" ,7 , 0 ) & ~BIT(2 ),0444 ,"reset_comex_thermal" ,7 , 0 ) & ~BIT(3 ),0444 ,"reset_ac_pwr_fail" ,7 , 0 ) & ~BIT(6 ),0444 ,"voltreg_update_status" ,5 ,0444 ,"port80" ,7 , 0 ),0444 ,"bios_status" ,2 ,0444 ,"bios_start_retry" ,7 , 0 ) & ~BIT(4 ),0444 ,"bios_active_image" ,7 , 0 ) & ~BIT(5 ),0444 ,"vpd_wp" ,7 , 0 ) & ~BIT(3 ),0644 ,"pcie_asic_reset_dis" ,7 , 0 ) & ~BIT(4 ),0644 ,"shutdown_unlock" ,7 , 0 ) & ~BIT(5 ),0644 ,"fan_dir" ,7 , 0 ),0444 ,"dpu1_rst_en" ,7 , 0 ) & ~BIT(0 ),0200 ,"dpu2_rst_en" ,7 , 0 ) & ~BIT(1 ),0200 ,"dpu3_rst_en" ,7 , 0 ) & ~BIT(2 ),0200 ,"dpu4_rst_en" ,7 , 0 ) & ~BIT(3 ),0200 ,"psu1_on" ,7 , 0 ) & ~BIT(0 ),0200 ,"psu2_on" ,7 , 0 ) & ~BIT(1 ),0200 ,"pwr_cycle" ,7 , 0 ) & ~BIT(2 ),0200 ,"pwr_down" ,7 , 0 ) & ~BIT(3 ),0200 ,"jtag_cap" ,1 ,0444 ,"jtag_enable" ,1 , 0 ),1 ,0644 ,"non_active_bios_select" ,7 , 0 ) & ~BIT(4 ),0644 ,"bios_upgrade_fail" ,7 , 0 ) & ~BIT(5 ),0444 ,"bios_image_invert" ,7 , 0 ) & ~BIT(6 ),0644 ,"me_reboot" ,7 , 0 ) & ~BIT(7 ),0644 ,"dpu1_pwr_force" ,7 , 0 ) & ~BIT(0 ),0200 ,"dpu2_pwr_force" ,7 , 0 ) & ~BIT(1 ),0200 ,"dpu3_pwr_force" ,7 , 0 ) & ~BIT(2 ),0200 ,"dpu4_pwr_force" ,7 , 0 ) & ~BIT(3 ),0200 ,"ufm_done" ,7 , 0 ),0444 ,"asic_health" ,1 ,0444 ,"psu1_ac_ok" ,7 , 0 ) & ~BIT(0 ),0644 ,"psu2_ac_ok" ,7 , 0 ) & ~BIT(1 ),0644 ,"psu1_no_alert" ,7 , 0 ) & ~BIT(0 ),0644 ,"psu2_no_alert" ,7 , 0 ) & ~BIT(1 ),0644 ,"asic_pg_fail" ,7 , 0 ) & ~BIT(7 ),0444 ,"spi_chnl_select" ,7 , 0 ),1 ,0644 ,"config1" ,7 , 0 ),0444 ,"config2" ,7 , 0 ),0444 ,"config3" ,7 , 0 ),0444 ,"ufm_version" ,7 , 0 ),0444 ,static struct mlxreg_core_platform_data mlxplat_smart_switch_regs_io_data = {/* Platform FAN default */ static struct mlxreg_core_data mlxplat_mlxcpld_default_fan_data[] = {"pwm1" ,"pwm2" ,"pwm3" ,"pwm4" ,"tacho1" ,7 , 0 ),0 ),"tacho2" ,7 , 0 ),1 ),"tacho3" ,7 , 0 ),2 ),"tacho4" ,7 , 0 ),3 ),"tacho5" ,7 , 0 ),4 ),"tacho6" ,7 , 0 ),5 ),"tacho7" ,7 , 0 ),6 ),"tacho8" ,7 , 0 ),7 ),"tacho9" ,7 , 0 ),0 ),"tacho10" ,7 , 0 ),1 ),"tacho11" ,7 , 0 ),2 ),"tacho12" ,7 , 0 ),3 ),"tacho13" ,7 , 0 ),4 ),"tacho14" ,7 , 0 ),5 ),"conf" ,static struct mlxreg_core_platform_data mlxplat_default_fan_data = {/* XDR and smart switch platform fan data */ static struct mlxreg_core_data mlxplat_mlxcpld_xdr_fan_data[] = {"pwm1" ,"tacho1" ,7 , 0 ),1 ,"tacho2" ,7 , 0 ),2 ,"tacho3" ,7 , 0 ),3 ,"tacho4" ,7 , 0 ),4 ,"tacho5" ,7 , 0 ),5 ,"tacho6" ,7 , 0 ),6 ,"tacho7" ,7 , 0 ),7 ,"tacho8" ,7 , 0 ),8 ,"tacho9" ,7 , 0 ),9 ,"tacho10" ,7 , 0 ),10 ,"tacho11" ,7 , 0 ),11 ,"tacho12" ,7 , 0 ),12 ,"tacho13" ,7 , 0 ),13 ,"tacho14" ,7 , 0 ),14 ,"tacho15" ,7 , 0 ),15 ,"tacho16" ,7 , 0 ),16 ,"tacho17" ,7 , 0 ),17 ,"tacho18" ,7 , 0 ),18 ,"tacho19" ,7 , 0 ),19 ,"tacho20" ,7 , 0 ),20 ,"conf" ,static struct mlxreg_core_platform_data mlxplat_xdr_fan_data = {1 ,/* Watchdog type1: hardware implementation version1 * (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140 systems). static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type1[] = {"action" ,0 ,"timeout" ,"ping" ,0 ,"reset" ,7 , 0 ) & ~BIT(6 ),6 ,static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type1[] = {"action" ,4 ,"timeout" ,"ping" ,1 ,static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type1[] = {"mlx-wdt-main" ,"mlx-wdt-aux" ,/* Watchdog type2: hardware implementation version 2 * (all systems except (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140). static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type2[] = {"action" ,0 ,"timeout" ,"timeleft" ,"ping" ,0 ,"reset" ,7 , 0 ) & ~BIT(6 ),6 ,static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type2[] = {"action" ,4 ,"timeout" ,"timeleft" ,"ping" ,4 ,static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type2[] = {"mlx-wdt-main" ,"mlx-wdt-aux" ,/* Watchdog type3: hardware implementation version 3 * Can be on all systems. It's differentiated by WD capability bit. * Old systems (MSN2700, MSN2410, MSN2740, MSN2100 and MSN2140) * still have only one main watchdog. static struct mlxreg_core_data mlxplat_mlxcpld_wd_main_regs_type3[] = {"action" ,0 ,"timeout" ,"timeleft" ,"ping" ,0 ,"reset" ,7 , 0 ) & ~BIT(6 ),6 ,static struct mlxreg_core_data mlxplat_mlxcpld_wd_aux_regs_type3[] = {"action" ,4 ,"timeout" ,"timeleft" ,"ping" ,4 ,static struct mlxreg_core_platform_data mlxplat_mlxcpld_wd_set_type3[] = {"mlx-wdt-main" ,"mlx-wdt-aux" ,static bool mlxplat_mlxcpld_writeable_reg(struct device *dev, unsigned int reg)switch (reg) {case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET:case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET:case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET:case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET:case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET:case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET:case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET:case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET:case MLXPLAT_CPLD_LPC_REG_GP3_OFFSET:case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE:case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET:case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET:case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET:case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET:case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET:case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET:case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON:case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT:case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET:case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET:case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET:case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:return true ;return false ;static bool mlxplat_mlxcpld_readable_reg(struct device *dev, unsigned int reg)switch (reg) {case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET:case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET:case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET:case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET:case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET:case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET:case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET:case MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET:case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET:case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET:case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:case MLXPLAT_CPLD_LPC_REG_WP1_OFFSET:case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:case MLXPLAT_CPLD_LPC_REG_WP2_OFFSET:case MLXPLAT_CPLD_LPC_REG_GP3_OFFSET:case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE:case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET:case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET:case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET:case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET:case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET:case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET:case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET:case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET:case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN2_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN2_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN2_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET:case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET:case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON:case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET:case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT:case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD_CLEAR_WP_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD1_TMR_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD1_ACT_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD2_ACT_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD3_ACT_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD6_MVER_OFFSET:case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET:case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET:case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET:case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET:case MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET:case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET:case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET:case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET:case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET:case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET:case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET:return true ;return false ;static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)switch (reg) {case MLXPLAT_CPLD_LPC_REG_CPLD1_VER_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD2_VER_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD3_VER_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD4_VER_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD5_VER_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD1_PN_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD1_PN1_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD2_PN_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET:case MLXPLAT_CPLD_LPC_REG_RESET_GP1_OFFSET:case MLXPLAT_CPLD_LPC_REG_RESET_GP2_OFFSET:case MLXPLAT_CPLD_LPC_REG_RESET_GP3_OFFSET:case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET:case MLXPLAT_CPLD_LPC_REG_RESET_CAUSE_OFFSET:case MLXPLAT_CPLD_LPC_REG_RST_CAUSE1_OFFSET:case MLXPLAT_CPLD_LPC_REG_RST_CAUSE2_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED1_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED2_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED3_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED4_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED5_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED6_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED7_OFFSET:case MLXPLAT_CPLD_LPC_REG_LED8_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN_DIRECTION:case MLXPLAT_CPLD_LPC_REG_GP0_RO_OFFSET:case MLXPLAT_CPLD_LPC_REG_GPCOM0_OFFSET:case MLXPLAT_CPLD_LPC_REG_GP1_RO_OFFSET:case MLXPLAT_CPLD_LPC_REG_GP0_OFFSET:case MLXPLAT_CPLD_LPC_REG_GP_RST_OFFSET:case MLXPLAT_CPLD_LPC_REG_GP1_OFFSET:case MLXPLAT_CPLD_LPC_REG_GP2_OFFSET:case MLXPLAT_CPLD_LPC_REG_GP3_OFFSET:case MLXPLAT_CPLD_LPC_REG_FIELD_UPGRADE:case MLXPLAT_CPLD_LPC_SAFE_BIOS_OFFSET:case MLXPLAT_CPLD_LPC_SAFE_BIOS_WP_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGR_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGR_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_FU_CAP_OFFSET:case MLXPLAT_CPLD_LPC_REG_DBG1_OFFSET:case MLXPLAT_CPLD_LPC_REG_DBG2_OFFSET:case MLXPLAT_CPLD_LPC_REG_DBG3_OFFSET:case MLXPLAT_CPLD_LPC_REG_DBG4_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGRLO_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGRLO_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGRCO_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGRCO_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGRCX_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGRCX_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_GWP_OFFSET:case MLXPLAT_CPLD_LPC_REG_GWP_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_GWP_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_GPI_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_BRD_OFFSET:case MLXPLAT_CPLD_LPC_REG_BRD_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_BRD_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_ASIC_HEALTH_OFFSET:case MLXPLAT_CPLD_LPC_REG_ASIC_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_ASIC_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_ASIC2_HEALTH_OFFSET:case MLXPLAT_CPLD_LPC_REG_ASIC2_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_ASIC2_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_PSU_OFFSET:case MLXPLAT_CPLD_LPC_REG_PSU_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_PSU_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_PSU_AC_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWR_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWR_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWR_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_PSU_ALERT_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_EROT_OFFSET:case MLXPLAT_CPLD_LPC_REG_EROT_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_EROT_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_EROTE_OFFSET:case MLXPLAT_CPLD_LPC_REG_EROTE_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_EROTE_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWRB_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWRB_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGRLC_OFFSET:case MLXPLAT_CPLD_LPC_REG_AGGRLC_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_IN_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_IN_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_IN_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_VR_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_VR_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_VR_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_PG_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_PG_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_PG_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_RD_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_RD_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_RD_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_OK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_OK_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_OK_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_SN_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_SN_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_SN_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_SD_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_SD_EVENT_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_SD_MASK_OFFSET:case MLXPLAT_CPLD_LPC_REG_LC_PWR_ON:case MLXPLAT_CPLD_LPC_REG_GP4_RO_OFFSET:case MLXPLAT_CPLD_LPC_REG_SPI_CHNL_SELECT:case MLXPLAT_CPLD_LPC_REG_WD2_TMR_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD2_TLEFT_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD3_TMR_OFFSET:case MLXPLAT_CPLD_LPC_REG_WD3_TLEFT_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD6_MVER_OFFSET:case MLXPLAT_CPLD_LPC_REG_I2C_CH1_OFFSET:case MLXPLAT_CPLD_LPC_REG_I2C_CH2_OFFSET:case MLXPLAT_CPLD_LPC_REG_I2C_CH3_OFFSET:case MLXPLAT_CPLD_LPC_REG_I2C_CH4_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD1_MVER_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD2_MVER_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD3_MVER_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD4_MVER_OFFSET:case MLXPLAT_CPLD_LPC_REG_CPLD5_MVER_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWM1_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWM2_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWM3_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWM4_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO1_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO2_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO3_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO4_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO5_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO6_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO7_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO8_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO9_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO10_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO11_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO12_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO13_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO14_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO15_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO16_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO17_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO18_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO19_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO20_OFFSET:case MLXPLAT_CPLD_LPC_REG_ASIC_CAP_OFFSET:case MLXPLAT_CPLD_LPC_REG_PWM_CONTROL_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN_CAP1_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN_CAP2_OFFSET:case MLXPLAT_CPLD_LPC_REG_FAN_DRW_CAP_OFFSET:case MLXPLAT_CPLD_LPC_REG_TACHO_SPEED_OFFSET:case MLXPLAT_CPLD_LPC_REG_PSU_I2C_CAP_OFFSET:case MLXPLAT_CPLD_LPC_REG_SLOT_QTY_OFFSET:case MLXPLAT_CPLD_LPC_REG_CONFIG1_OFFSET:case MLXPLAT_CPLD_LPC_REG_CONFIG2_OFFSET:case MLXPLAT_CPLD_LPC_REG_CONFIG3_OFFSET:case MLXPLAT_CPLD_LPC_REG_UFM_VERSION_OFFSET:return true ;return false ;static const struct reg_default mlxplat_mlxcpld_regmap_default[] = {0 x00 },0 x00 },0 x00 },0 x00 },static const struct reg_default mlxplat_mlxcpld_regmap_ng[] = {0 x00 },0 x00 },static const struct reg_default mlxplat_mlxcpld_regmap_comex_default[] = {0 x00 },static const struct reg_default mlxplat_mlxcpld_regmap_ng400[] = {0 x00 },0 x00 },0 x00 },0 x00 },static const struct reg_default mlxplat_mlxcpld_regmap_rack_switch[] = {0 x00 },0 x00 },0 x00 },static const struct reg_default mlxplat_mlxcpld_regmap_eth_modular[] = {0 x61 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },0 x00 },static const struct reg_default mlxplat_mlxcpld_regmap_smart_switch[] = {0 x00 },0 x00 },0 x00 },0 x00 },struct mlxplat_mlxcpld_regmap_context {void __iomem *base;static struct mlxplat_mlxcpld_regmap_context mlxplat_mlxcpld_regmap_ctx;static int void *context, unsigned int reg, unsigned int *val)struct mlxplat_mlxcpld_regmap_context *ctx = context;return 0 ;static int void *context, unsigned int reg, unsigned int val)struct mlxplat_mlxcpld_regmap_context *ctx = context;return 0 ;static const struct regmap_config mlxplat_mlxcpld_regmap_config = {8 ,8 ,255 ,static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng = {8 ,8 ,255 ,static const struct regmap_config mlxplat_mlxcpld_regmap_config_comex = {8 ,8 ,255 ,static const struct regmap_config mlxplat_mlxcpld_regmap_config_ng400 = {8 ,8 ,255 ,static const struct regmap_config mlxplat_mlxcpld_regmap_config_rack_switch = {8 ,8 ,255 ,static const struct regmap_config mlxplat_mlxcpld_regmap_config_eth_modular = {8 ,8 ,255 ,static const struct regmap_config mlxplat_mlxcpld_regmap_config_smart_switch = {8 ,8 ,255 ,static struct resource mlxplat_mlxcpld_resources[] = {0 ] = DEFINE_RES_IRQ_NAMED(MLXPLAT_CPLD_LPC_SYSIRQ, "mlxreg-hotplug" ),static struct mlxreg_core_hotplug_platform_data *mlxplat_i2c;static struct mlxreg_core_hotplug_platform_data *mlxplat_hotplug;static struct mlxreg_core_platform_data *mlxplat_led;static struct mlxreg_core_platform_data *mlxplat_regs_io;static struct mlxreg_core_platform_data *mlxplat_fan;static struct mlxreg_core_platform_datastatic struct mlxreg_core_data *mlxplat_dpu_data[MLXPLAT_CPLD_DPU_MAX_DEVS];static const struct regmap_config *mlxplat_regmap_config;static struct pci_dev *lpc_bridge;static struct pci_dev *i2c_bridge;static struct pci_dev *jtag_bridge;/* Platform default reset function */ static int mlxplat_reboot_notifier(struct notifier_block *nb, unsigned long action, void *unused)struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);int ret;if (action == SYS_RESTART && !ret && regval & MLXPLAT_CPLD_SYS_RESET_MASK)return NOTIFY_DONE;static struct notifier_block mlxplat_reboot_default_nb = {/* Platform default poweroff function */ static void mlxplat_poweroff(void )struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);if (mlxplat_reboot_nb);static int __init mlxplat_register_platform_device(void )1 ,if (IS_ERR(mlxplat_dev))return PTR_ERR(mlxplat_dev);else return 1 ;static int __init mlxplat_dmi_default_matched(const struct dmi_system_id *dmi)int i;for (i = 0 ; i < mlxplat_mux_num; i++) {1 ][MLXPLAT_CPLD_GRP_CHNL_NUM - 1 ];0 ] = &mlxplat_mlxcpld_wd_set_type1[0 ];return mlxplat_register_platform_device();static int __init mlxplat_dmi_default_wc_matched(const struct dmi_system_id *dmi)int i;for (i = 0 ; i < mlxplat_mux_num; i++) {1 ][MLXPLAT_CPLD_GRP_CHNL_NUM - 1 ];0 ] = &mlxplat_mlxcpld_wd_set_type1[0 ];return mlxplat_register_platform_device();static int __init mlxplat_dmi_default_eth_wc_blade_matched(const struct dmi_system_id *dmi)int i;for (i = 0 ; i < mlxplat_mux_num; i++) {1 ];for (i = 0 ; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)return mlxplat_register_platform_device();static int __init mlxplat_dmi_msn21xx_matched(const struct dmi_system_id *dmi)int i;for (i = 0 ; i < mlxplat_mux_num; i++) {1 ];0 ] = &mlxplat_mlxcpld_wd_set_type1[0 ];return mlxplat_register_platform_device();static int __init mlxplat_dmi_msn274x_matched(const struct dmi_system_id *dmi)int i;for (i = 0 ; i < mlxplat_mux_num; i++) {1 ];0 ] = &mlxplat_mlxcpld_wd_set_type1[0 ];return mlxplat_register_platform_device();static int __init mlxplat_dmi_msn201x_matched(const struct dmi_system_id *dmi)int i;for (i = 0 ; i < mlxplat_mux_num; i++) {1 ][MLXPLAT_CPLD_GRP_CHNL_NUM - 1 ];0 ] = &mlxplat_mlxcpld_wd_set_type1[0 ];return mlxplat_register_platform_device();static int __init mlxplat_dmi_qmb7xx_matched(const struct dmi_system_id *dmi)int i;for (i = 0 ; i < mlxplat_mux_num; i++) {1 ];for (i = 0 ; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)return mlxplat_register_platform_device();static int __init mlxplat_dmi_comex_matched(const struct dmi_system_id *dmi)int i;for (i = 0 ; i < mlxplat_mux_num; i++) {for (i = 0 ; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)return mlxplat_register_platform_device();static int __init mlxplat_dmi_ng400_matched(const struct dmi_system_id *dmi)int i;for (i = 0 ; i < mlxplat_mux_num; i++) {1 ];for (i = 0 ; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)return mlxplat_register_platform_device();static int __init mlxplat_dmi_modular_matched(const struct dmi_system_id *dmi)int i;for (i = 0 ; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)return mlxplat_register_platform_device();static int __init mlxplat_dmi_chassis_blade_matched(const struct dmi_system_id *dmi)int i;1 ];for (i = 0 ; i < mlxplat_mux_num; i++) {return mlxplat_register_platform_device();static int __init mlxplat_dmi_rack_switch_matched(const struct dmi_system_id *dmi)int i;1 ];for (i = 0 ; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)return mlxplat_register_platform_device();static int __init mlxplat_dmi_ng800_matched(const struct dmi_system_id *dmi)int i;1 ];for (i = 0 ; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)return mlxplat_register_platform_device();static int __init mlxplat_dmi_l1_switch_matched(const struct dmi_system_id *dmi)int i;1 ];for (i = 0 ; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)return mlxplat_register_platform_device();static int __init mlxplat_dmi_smart_switch_matched(const struct dmi_system_id *dmi)int i;1 ];for (i = 0 ; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type2); i++)for (i = 0 ; i < ARRAY_SIZE(mlxplat_mlxcpld_smart_switch_dpu_data); i++)return mlxplat_register_platform_device();static int __init mlxplat_dmi_ng400_hi171_matched(const struct dmi_system_id *dmi)unsigned int i;1 ];for (i = 0 ; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++)return mlxplat_register_platform_device();static const struct dmi_system_id mlxplat_dmi_table[] __initconst = {"VMOD0001" ),"HI138" ),"VMOD0001" ),"VMOD0002" ),"VMOD0003" ),"VMOD0004" ),"VMOD0005" ),"HI139" ),"VMOD0005" ),"VMOD0007" ),"VMOD0009" ),"VMOD0010" ),"HI142" ),"VMOD0010" ),"VMOD0011" ),"VMOD0013" ),"VMOD0015" ),"VMOD0017" ),"VMOD0019" ),"VMOD0022" ),"HI171" ),"VMOD0022" ),"HI172" ),"Mellanox Technologies" ),"MSN274" ),"Mellanox Technologies" ),"MSN24" ),"Mellanox Technologies" ),"MSN27" ),"Mellanox Technologies" ),"MSB" ),"Mellanox Technologies" ),"MSX" ),"Mellanox Technologies" ),"MSN21" ),"Mellanox Technologies" ),"MSN201" ),"Mellanox Technologies" ),"MQM87" ),"Mellanox Technologies" ),"MSN37" ),"Mellanox Technologies" ),"MSN34" ),"Mellanox Technologies" ),"MSN38" ),static int mlxplat_mlxcpld_verify_bus_topology(int *nr)struct i2c_adapter *search_adap;int i, shift = 0 ;/* Scan adapters from expected id to verify it is free. */ for (i = MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR; i <if (search_adap) {continue ;/* Return if expected parent adapter is free. */ if (i == MLXPLAT_CPLD_PHYS_ADAPTER_DEF_NR)return 0 ;break ;/* Return with error if free id for adapter is not found. */ if (i == mlxplat_max_adap_num)return -ENODEV;/* Shift adapter ids, since expected parent adapter is not free. */ for (i = 0 ; i < mlxplat_mux_num; i++) {if (shift > 0 )return 0 ;static int mlxplat_mlxcpld_check_wd_capability(void *regmap)int i, rc;if (rc)return rc;if (!(regval & ~MLXPLAT_CPLD_WD_CPBLTY_MASK)) {for (i = 0 ; i < ARRAY_SIZE(mlxplat_mlxcpld_wd_set_type3); i++) {if (mlxplat_wd_data[i])return 0 ;static int mlxplat_lpc_cpld_device_init(struct resource **hotplug_resources,unsigned int *hotplug_resources_size)int err;1 ].start, 1 );if (!mlxplat_mlxcpld_regmap_ctx.base) {goto fail_devm_ioport_map;return 0 ;return err;static void mlxplat_lpc_cpld_device_exit(void )static int unsigned int device, const char *res_name, struct pci_dev **pci_bridge,void __iomem **pci_bridge_addr)void __iomem *pci_mem_addr;struct pci_dev *pci_dev;int err;if (!pci_dev)return -ENODEV;if (err) {"pci_enable_device failed with error %d\n" , err);goto fail_pci_enable_device;0 , res_name);if (err) {"pci_request_regions failed with error %d\n" , err);goto fail_pci_request_regions;64 ));if (err) {32 ));if (err) {"dma_set_mask failed with error %d\n" , err);goto fail_pci_set_dma_mask;0 ),0 ));if (!pci_mem_addr) {"ioremap failed\n" );goto fail_ioremap;return 0 ;return err;static void struct pci_dev *pci_bridge,void __iomem *pci_bridge_addr)static int struct resource **hotplug_resources,unsigned int *hotplug_resources_size)int err;"mlxplat_lpc_bridge" , &lpc_bridge,if (err)goto mlxplat_pci_fpga_device_init_lpc_fail;"mlxplat_i2c_bridge" , &i2c_bridge,if (err)goto mlxplat_pci_fpga_device_init_i2c_fail;"mlxplat_jtag_bridge" , &jtag_bridge,if (err)goto mlxplat_pci_fpga_device_init_jtag_fail;return 0 ;return err;static void mlxplat_pci_fpga_devices_exit(void )static int struct resource **hotplug_resources, unsigned int *hotplug_resources_size)int err;if (err == -ENODEV)return mlxplat_lpc_cpld_device_init(hotplug_resources, hotplug_resources_size);return err;static void mlxplat_logicdev_exit(void )if (lpc_bridge)else static int mlxplat_platdevs_init(struct mlxplat_priv *priv)int i = 0 , err;/* Add hotplug driver */ if (mlxplat_hotplug) {if (priv->irq_fpga)"mlxreg-hotplug" , PLATFORM_DEVID_NONE,sizeof (*mlxplat_hotplug));if (IS_ERR(priv->pdev_hotplug)) {goto fail_platform_hotplug_register;/* Add LED driver. */ if (mlxplat_led) {"leds-mlxreg" ,0 , mlxplat_led,sizeof (*mlxplat_led));if (IS_ERR(priv->pdev_led)) {goto fail_platform_leds_register;/* Add registers io access driver. */ if (mlxplat_regs_io) {"mlxreg-io" ,0 , mlxplat_regs_io,sizeof (*mlxplat_regs_io));if (IS_ERR(priv->pdev_io_regs)) {goto fail_platform_io_register;/* Add FAN driver. */ if (mlxplat_fan) {"mlxreg-fan" ,0 ,sizeof (*mlxplat_fan));if (IS_ERR(priv->pdev_fan)) {goto fail_platform_fan_register;/* Add WD drivers. */ if (err)goto fail_platform_wd_register;for (i = 0 ; i < MLXPLAT_CPLD_WD_MAX_DEVS; i++) {if (mlxplat_wd_data[i]) {"mlx-wdt" , i,0 , mlxplat_wd_data[i],sizeof (*mlxplat_wd_data[i]));if (IS_ERR(priv->pdev_wd[i])) {goto fail_platform_wd_register;/* Add DPU drivers. */ for (i = 0 ; i < MLXPLAT_CPLD_DPU_MAX_DEVS; i++) {if (!mlxplat_dpu_data[i])continue ;"mlxreg-dpu" ,0 , mlxplat_dpu_data[i],sizeof (*mlxplat_dpu_data[i]));if (IS_ERR(priv->pdev_dpu[i])) {goto fail_platform_dpu_register;return 0 ;while (i--)while (i--)if (mlxplat_regs_io)if (mlxplat_led)if (mlxplat_hotplug)return err;static void mlxplat_platdevs_exit(struct mlxplat_priv *priv)int i;for (i = MLXPLAT_CPLD_DPU_MAX_DEVS - 1 ; i >= 0 ; i--)for (i = MLXPLAT_CPLD_WD_MAX_DEVS - 1 ; i >= 0 ; i--)if (priv->pdev_fan)if (priv->pdev_io_regs)if (priv->pdev_led)if (priv->pdev_hotplug)static int void *handle, struct i2c_adapter *parent,struct i2c_adapter *adapters[])struct mlxplat_priv *priv = handle;return mlxplat_platdevs_init(priv);static int mlxplat_i2c_mux_topology_init(struct mlxplat_priv *priv)int i, err;if (!priv->pdev_i2c) {return 0 ;for (i = 0 ; i < mlxplat_mux_num; i++) {"i2c-mux-reg" , i, NULL, 0 ,sizeof (mlxplat_mux_data[i]));if (IS_ERR(priv->pdev_mux[i])) {goto fail_platform_mux_register;return mlxplat_i2c_mux_complition_notify(priv, NULL, NULL);while (i--)return err;static void mlxplat_i2c_mux_topology_exit(struct mlxplat_priv *priv)int i;for (i = mlxplat_mux_num - 1 ; i >= 0 ; i--) {if (priv->pdev_mux[i])static int mlxplat_i2c_main_completion_notify(void *handle, int id)struct mlxplat_priv *priv = handle;return mlxplat_i2c_mux_topology_init(priv);static int mlxplat_i2c_main_init(struct mlxplat_priv *priv)int nr, err;if (!mlxplat_i2c)return 0 ;if (nr < 0 )goto fail_mlxplat_mlxcpld_verify_bus_topology;1 : nr;/* Set mapped base address of I2C-LPC bridge over PCIe */ if (lpc_bridge)"i2c_mlxcpld" ,sizeof (*mlxplat_i2c));if (IS_ERR(priv->pdev_i2c)) {goto fail_platform_i2c_register;if (priv->i2c_main_init_status == MLXPLAT_I2C_MAIN_BUS_NOTIFIED) {if (err)goto fail_mlxplat_i2c_mux_topology_init;return 0 ;return err;static void mlxplat_i2c_main_exit(struct mlxplat_priv *priv)if (priv->pdev_i2c)static int mlxplat_probe(struct platform_device *pdev)unsigned int hotplug_resources_size = 0 ;struct resource *hotplug_resources = NULL;struct acpi_device *acpi_dev;struct mlxplat_priv *priv;int irq_fpga = 0 , i, err;if (acpi_dev) {0 );if (irq_fpga < 0 )return -ENODEV;if (err)return err;sizeof (struct mlxplat_priv),if (!priv) {goto fail_alloc;if (!mlxplat_regmap_config)if (IS_ERR(priv->regmap)) {goto fail_alloc;/* Set default registers. */ for (i = 0 ; i < mlxplat_regmap_config->num_reg_defaults; i++) {if (err)goto fail_regmap_write;if (err)goto fail_mlxplat_i2c_main_init;/* Sync registers with hardware. */ if (err)goto fail_regcache_sync;if (mlxplat_reboot_nb) {if (err)goto fail_register_reboot_notifier;return 0 ;return err;static void mlxplat_remove(struct platform_device *pdev)struct mlxplat_priv *priv = platform_get_drvdata(mlxplat_dev);if (pm_power_off)if (mlxplat_reboot_nb)static const struct acpi_device_id mlxplat_acpi_table[] = {"MLNXBF49" , 0 },static struct platform_driver mlxplat_driver = {"mlxplat" ,static int __init mlxplat_init(void )int err;if (!dmi_check_system(mlxplat_dmi_table))return -ENODEV;if (err)return err;return 0 ;static void __exit mlxplat_exit(void )if (mlxplat_dev)"Vadim Pasternak <vadimp@mellanox.com>" );"Mellanox platform driver" );"Dual BSD/GPL" );
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