// SPDX-License-Identifier: GPL-2.0-only /* * Pinctrl data for the NVIDIA Tegra20 pinmux * * Author: Stephen Warren <swarren@nvidia.com> * * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. * * Derived from code: * Copyright (C) 2010 Google, Inc. * Copyright (C) 2010 NVIDIA Corporation #include <linux/clk-provider.h>#include <linux/init.h>#include <linux/of.h>#include <linux/platform_device.h>#include <linux/pinctrl/pinctrl.h>#include <linux/pinctrl/pinmux.h>#include "pinctrl-tegra.h" /* * Most pins affected by the pinmux can also be GPIOs. Define these first. * These must match how the GPIO driver names/numbers its pins. #define _GPIO(offset) (offset)#define TEGRA_PIN_VI_GP6_PA0 _GPIO(0 )#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1 )#define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2 )#define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3 )#define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4 )#define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5 )#define TEGRA_PIN_SDIO3_CLK_PA6 _GPIO(6 )#define TEGRA_PIN_SDIO3_CMD_PA7 _GPIO(7 )#define TEGRA_PIN_GMI_AD17_PB0 _GPIO(8 )#define TEGRA_PIN_GMI_AD18_PB1 _GPIO(9 )#define TEGRA_PIN_LCD_PWR0_PB2 _GPIO(10 )#define TEGRA_PIN_LCD_PCLK_PB3 _GPIO(11 )#define TEGRA_PIN_SDIO3_DAT3_PB4 _GPIO(12 )#define TEGRA_PIN_SDIO3_DAT2_PB5 _GPIO(13 )#define TEGRA_PIN_SDIO3_DAT1_PB6 _GPIO(14 )#define TEGRA_PIN_SDIO3_DAT0_PB7 _GPIO(15 )#define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16 )#define TEGRA_PIN_LCD_PWR1_PC1 _GPIO(17 )#define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18 )#define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19 )#define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20 )#define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21 )#define TEGRA_PIN_LCD_PWR2_PC6 _GPIO(22 )#define TEGRA_PIN_GMI_WP_N_PC7 _GPIO(23 )#define TEGRA_PIN_SDIO3_DAT5_PD0 _GPIO(24 )#define TEGRA_PIN_SDIO3_DAT4_PD1 _GPIO(25 )#define TEGRA_PIN_VI_GP5_PD2 _GPIO(26 )#define TEGRA_PIN_SDIO3_DAT6_PD3 _GPIO(27 )#define TEGRA_PIN_SDIO3_DAT7_PD4 _GPIO(28 )#define TEGRA_PIN_VI_D1_PD5 _GPIO(29 )#define TEGRA_PIN_VI_VSYNC_PD6 _GPIO(30 )#define TEGRA_PIN_VI_HSYNC_PD7 _GPIO(31 )#define TEGRA_PIN_LCD_D0_PE0 _GPIO(32 )#define TEGRA_PIN_LCD_D1_PE1 _GPIO(33 )#define TEGRA_PIN_LCD_D2_PE2 _GPIO(34 )#define TEGRA_PIN_LCD_D3_PE3 _GPIO(35 )#define TEGRA_PIN_LCD_D4_PE4 _GPIO(36 )#define TEGRA_PIN_LCD_D5_PE5 _GPIO(37 )#define TEGRA_PIN_LCD_D6_PE6 _GPIO(38 )#define TEGRA_PIN_LCD_D7_PE7 _GPIO(39 )#define TEGRA_PIN_LCD_D8_PF0 _GPIO(40 )#define TEGRA_PIN_LCD_D9_PF1 _GPIO(41 )#define TEGRA_PIN_LCD_D10_PF2 _GPIO(42 )#define TEGRA_PIN_LCD_D11_PF3 _GPIO(43 )#define TEGRA_PIN_LCD_D12_PF4 _GPIO(44 )#define TEGRA_PIN_LCD_D13_PF5 _GPIO(45 )#define TEGRA_PIN_LCD_D14_PF6 _GPIO(46 )#define TEGRA_PIN_LCD_D15_PF7 _GPIO(47 )#define TEGRA_PIN_GMI_AD0_PG0 _GPIO(48 )#define TEGRA_PIN_GMI_AD1_PG1 _GPIO(49 )#define TEGRA_PIN_GMI_AD2_PG2 _GPIO(50 )#define TEGRA_PIN_GMI_AD3_PG3 _GPIO(51 )#define TEGRA_PIN_GMI_AD4_PG4 _GPIO(52 )#define TEGRA_PIN_GMI_AD5_PG5 _GPIO(53 )#define TEGRA_PIN_GMI_AD6_PG6 _GPIO(54 )#define TEGRA_PIN_GMI_AD7_PG7 _GPIO(55 )#define TEGRA_PIN_GMI_AD8_PH0 _GPIO(56 )#define TEGRA_PIN_GMI_AD9_PH1 _GPIO(57 )#define TEGRA_PIN_GMI_AD10_PH2 _GPIO(58 )#define TEGRA_PIN_GMI_AD11_PH3 _GPIO(59 )#define TEGRA_PIN_GMI_AD12_PH4 _GPIO(60 )#define TEGRA_PIN_GMI_AD13_PH5 _GPIO(61 )#define TEGRA_PIN_GMI_AD14_PH6 _GPIO(62 )#define TEGRA_PIN_GMI_AD15_PH7 _GPIO(63 )#define TEGRA_PIN_GMI_HIOW_N_PI0 _GPIO(64 )#define TEGRA_PIN_GMI_HIOR_N_PI1 _GPIO(65 )#define TEGRA_PIN_GMI_CS5_N_PI2 _GPIO(66 )#define TEGRA_PIN_GMI_CS6_N_PI3 _GPIO(67 )#define TEGRA_PIN_GMI_RST_N_PI4 _GPIO(68 )#define TEGRA_PIN_GMI_IORDY_PI5 _GPIO(69 )#define TEGRA_PIN_GMI_CS7_N_PI6 _GPIO(70 )#define TEGRA_PIN_GMI_WAIT_PI7 _GPIO(71 )#define TEGRA_PIN_GMI_CS0_N_PJ0 _GPIO(72 )#define TEGRA_PIN_LCD_DE_PJ1 _GPIO(73 )#define TEGRA_PIN_GMI_CS1_N_PJ2 _GPIO(74 )#define TEGRA_PIN_LCD_HSYNC_PJ3 _GPIO(75 )#define TEGRA_PIN_LCD_VSYNC_PJ4 _GPIO(76 )#define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77 )#define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78 )#define TEGRA_PIN_GMI_AD16_PJ7 _GPIO(79 )#define TEGRA_PIN_GMI_ADV_N_PK0 _GPIO(80 )#define TEGRA_PIN_GMI_CLK_PK1 _GPIO(81 )#define TEGRA_PIN_GMI_CS4_N_PK2 _GPIO(82 )#define TEGRA_PIN_GMI_CS2_N_PK3 _GPIO(83 )#define TEGRA_PIN_GMI_CS3_N_PK4 _GPIO(84 )#define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85 )#define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86 )#define TEGRA_PIN_GMI_AD19_PK7 _GPIO(87 )#define TEGRA_PIN_VI_D2_PL0 _GPIO(88 )#define TEGRA_PIN_VI_D3_PL1 _GPIO(89 )#define TEGRA_PIN_VI_D4_PL2 _GPIO(90 )#define TEGRA_PIN_VI_D5_PL3 _GPIO(91 )#define TEGRA_PIN_VI_D6_PL4 _GPIO(92 )#define TEGRA_PIN_VI_D7_PL5 _GPIO(93 )#define TEGRA_PIN_VI_D8_PL6 _GPIO(94 )#define TEGRA_PIN_VI_D9_PL7 _GPIO(95 )#define TEGRA_PIN_LCD_D16_PM0 _GPIO(96 )#define TEGRA_PIN_LCD_D17_PM1 _GPIO(97 )#define TEGRA_PIN_LCD_D18_PM2 _GPIO(98 )#define TEGRA_PIN_LCD_D19_PM3 _GPIO(99 )#define TEGRA_PIN_LCD_D20_PM4 _GPIO(100 )#define TEGRA_PIN_LCD_D21_PM5 _GPIO(101 )#define TEGRA_PIN_LCD_D22_PM6 _GPIO(102 )#define TEGRA_PIN_LCD_D23_PM7 _GPIO(103 )#define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104 )#define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105 )#define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106 )#define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107 )#define TEGRA_PIN_LCD_CS0_N_PN4 _GPIO(108 )#define TEGRA_PIN_LCD_SDOUT_PN5 _GPIO(109 )#define TEGRA_PIN_LCD_DC0_PN6 _GPIO(110 )#define TEGRA_PIN_HDMI_INT_N_PN7 _GPIO(111 )#define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112 )#define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113 )#define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114 )#define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115 )#define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116 )#define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117 )#define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118 )#define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119 )#define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120 )#define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121 )#define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122 )#define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123 )#define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124 )#define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125 )#define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126 )#define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127 )#define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128 )#define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129 )#define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130 )#define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131 )#define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132 )#define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133 )#define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134 )#define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135 )#define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136 )#define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137 )#define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138 )#define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139 )#define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140 )#define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141 )#define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142 )#define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143 )#define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144 )#define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145 )#define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146 )#define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147 )#define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148 )#define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149 )#define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150 )#define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151 )#define TEGRA_PIN_VI_PCLK_PT0 _GPIO(152 )#define TEGRA_PIN_VI_MCLK_PT1 _GPIO(153 )#define TEGRA_PIN_VI_D10_PT2 _GPIO(154 )#define TEGRA_PIN_VI_D11_PT3 _GPIO(155 )#define TEGRA_PIN_VI_D0_PT4 _GPIO(156 )#define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157 )#define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158 )#define TEGRA_PIN_GMI_DPD_PT7 _GPIO(159 )#define TEGRA_PIN_PU0 _GPIO(160 )#define TEGRA_PIN_PU1 _GPIO(161 )#define TEGRA_PIN_PU2 _GPIO(162 )#define TEGRA_PIN_PU3 _GPIO(163 )#define TEGRA_PIN_PU4 _GPIO(164 )#define TEGRA_PIN_PU5 _GPIO(165 )#define TEGRA_PIN_PU6 _GPIO(166 )#define TEGRA_PIN_JTAG_RTCK_PU7 _GPIO(167 )#define TEGRA_PIN_PV0 _GPIO(168 )#define TEGRA_PIN_PV1 _GPIO(169 )#define TEGRA_PIN_PV2 _GPIO(170 )#define TEGRA_PIN_PV3 _GPIO(171 )#define TEGRA_PIN_PV4 _GPIO(172 )#define TEGRA_PIN_PV5 _GPIO(173 )#define TEGRA_PIN_PV6 _GPIO(174 )#define TEGRA_PIN_LCD_DC1_PV7 _GPIO(175 )#define TEGRA_PIN_LCD_CS1_N_PW0 _GPIO(176 )#define TEGRA_PIN_LCD_M1_PW1 _GPIO(177 )#define TEGRA_PIN_SPI2_CS1_N_PW2 _GPIO(178 )#define TEGRA_PIN_SPI2_CS2_N_PW3 _GPIO(179 )#define TEGRA_PIN_DAP_MCLK1_PW4 _GPIO(180 )#define TEGRA_PIN_DAP_MCLK2_PW5 _GPIO(181 )#define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182 )#define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183 )#define TEGRA_PIN_SPI2_MOSI_PX0 _GPIO(184 )#define TEGRA_PIN_SPI2_MISO_PX1 _GPIO(185 )#define TEGRA_PIN_SPI2_SCK_PX2 _GPIO(186 )#define TEGRA_PIN_SPI2_CS0_N_PX3 _GPIO(187 )#define TEGRA_PIN_SPI1_MOSI_PX4 _GPIO(188 )#define TEGRA_PIN_SPI1_SCK_PX5 _GPIO(189 )#define TEGRA_PIN_SPI1_CS0_N_PX6 _GPIO(190 )#define TEGRA_PIN_SPI1_MISO_PX7 _GPIO(191 )#define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192 )#define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193 )#define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194 )#define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195 )#define TEGRA_PIN_SDIO1_DAT3_PY4 _GPIO(196 )#define TEGRA_PIN_SDIO1_DAT2_PY5 _GPIO(197 )#define TEGRA_PIN_SDIO1_DAT1_PY6 _GPIO(198 )#define TEGRA_PIN_SDIO1_DAT0_PY7 _GPIO(199 )#define TEGRA_PIN_SDIO1_CLK_PZ0 _GPIO(200 )#define TEGRA_PIN_SDIO1_CMD_PZ1 _GPIO(201 )#define TEGRA_PIN_LCD_SDIN_PZ2 _GPIO(202 )#define TEGRA_PIN_LCD_WR_N_PZ3 _GPIO(203 )#define TEGRA_PIN_LCD_SCK_PZ4 _GPIO(204 )#define TEGRA_PIN_SYS_CLK_REQ_PZ5 _GPIO(205 )#define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206 )#define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207 )#define TEGRA_PIN_GMI_AD20_PAA0 _GPIO(208 )#define TEGRA_PIN_GMI_AD21_PAA1 _GPIO(209 )#define TEGRA_PIN_GMI_AD22_PAA2 _GPIO(210 )#define TEGRA_PIN_GMI_AD23_PAA3 _GPIO(211 )#define TEGRA_PIN_GMI_AD24_PAA4 _GPIO(212 )#define TEGRA_PIN_GMI_AD25_PAA5 _GPIO(213 )#define TEGRA_PIN_GMI_AD26_PAA6 _GPIO(214 )#define TEGRA_PIN_GMI_AD27_PAA7 _GPIO(215 )#define TEGRA_PIN_LED_BLINK_PBB0 _GPIO(216 )#define TEGRA_PIN_VI_GP0_PBB1 _GPIO(217 )#define TEGRA_PIN_CAM_I2C_SCL_PBB2 _GPIO(218 )#define TEGRA_PIN_CAM_I2C_SDA_PBB3 _GPIO(219 )#define TEGRA_PIN_VI_GP3_PBB4 _GPIO(220 )#define TEGRA_PIN_VI_GP4_PBB5 _GPIO(221 )#define TEGRA_PIN_PBB6 _GPIO(222 )#define TEGRA_PIN_PBB7 _GPIO(223 )/* All non-GPIO pins follow */ #define NUM_GPIOS (TEGRA_PIN_PBB7 + 1 )#define _PIN(offset) (NUM_GPIOS + (offset))#define TEGRA_PIN_CRT_HSYNC _PIN(30 )#define TEGRA_PIN_CRT_VSYNC _PIN(31 )#define TEGRA_PIN_DDC_SCL _PIN(32 )#define TEGRA_PIN_DDC_SDA _PIN(33 )#define TEGRA_PIN_OWC _PIN(34 )#define TEGRA_PIN_CORE_PWR_REQ _PIN(35 )#define TEGRA_PIN_CPU_PWR_REQ _PIN(36 )#define TEGRA_PIN_PWR_INT_N _PIN(37 )#define TEGRA_PIN_CLK_32_K_IN _PIN(38 )#define TEGRA_PIN_DDR_COMP_PD _PIN(39 )#define TEGRA_PIN_DDR_COMP_PU _PIN(40 )#define TEGRA_PIN_DDR_A0 _PIN(41 )#define TEGRA_PIN_DDR_A1 _PIN(42 )#define TEGRA_PIN_DDR_A2 _PIN(43 )#define TEGRA_PIN_DDR_A3 _PIN(44 )#define TEGRA_PIN_DDR_A4 _PIN(45 )#define TEGRA_PIN_DDR_A5 _PIN(46 )#define TEGRA_PIN_DDR_A6 _PIN(47 )#define TEGRA_PIN_DDR_A7 _PIN(48 )#define TEGRA_PIN_DDR_A8 _PIN(49 )#define TEGRA_PIN_DDR_A9 _PIN(50 )#define TEGRA_PIN_DDR_A10 _PIN(51 )#define TEGRA_PIN_DDR_A11 _PIN(52 )#define TEGRA_PIN_DDR_A12 _PIN(53 )#define TEGRA_PIN_DDR_A13 _PIN(54 )#define TEGRA_PIN_DDR_A14 _PIN(55 )#define TEGRA_PIN_DDR_CAS_N _PIN(56 )#define TEGRA_PIN_DDR_BA0 _PIN(57 )#define TEGRA_PIN_DDR_BA1 _PIN(58 )#define TEGRA_PIN_DDR_BA2 _PIN(59 )#define TEGRA_PIN_DDR_DQS0P _PIN(60 )#define TEGRA_PIN_DDR_DQS0N _PIN(61 )#define TEGRA_PIN_DDR_DQS1P _PIN(62 )#define TEGRA_PIN_DDR_DQS1N _PIN(63 )#define TEGRA_PIN_DDR_DQS2P _PIN(64 )#define TEGRA_PIN_DDR_DQS2N _PIN(65 )#define TEGRA_PIN_DDR_DQS3P _PIN(66 )#define TEGRA_PIN_DDR_DQS3N _PIN(67 )#define TEGRA_PIN_DDR_CKE0 _PIN(68 )#define TEGRA_PIN_DDR_CKE1 _PIN(69 )#define TEGRA_PIN_DDR_CLK _PIN(70 )#define TEGRA_PIN_DDR_CLK_N _PIN(71 )#define TEGRA_PIN_DDR_DM0 _PIN(72 )#define TEGRA_PIN_DDR_DM1 _PIN(73 )#define TEGRA_PIN_DDR_DM2 _PIN(74 )#define TEGRA_PIN_DDR_DM3 _PIN(75 )#define TEGRA_PIN_DDR_ODT _PIN(76 )#define TEGRA_PIN_DDR_QUSE0 _PIN(77 )#define TEGRA_PIN_DDR_QUSE1 _PIN(78 )#define TEGRA_PIN_DDR_QUSE2 _PIN(79 )#define TEGRA_PIN_DDR_QUSE3 _PIN(80 )#define TEGRA_PIN_DDR_RAS_N _PIN(81 )#define TEGRA_PIN_DDR_WE_N _PIN(82 )#define TEGRA_PIN_DDR_DQ0 _PIN(83 )#define TEGRA_PIN_DDR_DQ1 _PIN(84 )#define TEGRA_PIN_DDR_DQ2 _PIN(85 )#define TEGRA_PIN_DDR_DQ3 _PIN(86 )#define TEGRA_PIN_DDR_DQ4 _PIN(87 )#define TEGRA_PIN_DDR_DQ5 _PIN(88 )#define TEGRA_PIN_DDR_DQ6 _PIN(89 )#define TEGRA_PIN_DDR_DQ7 _PIN(90 )#define TEGRA_PIN_DDR_DQ8 _PIN(91 )#define TEGRA_PIN_DDR_DQ9 _PIN(92 )#define TEGRA_PIN_DDR_DQ10 _PIN(93 )#define TEGRA_PIN_DDR_DQ11 _PIN(94 )#define TEGRA_PIN_DDR_DQ12 _PIN(95 )#define TEGRA_PIN_DDR_DQ13 _PIN(96 )#define TEGRA_PIN_DDR_DQ14 _PIN(97 )#define TEGRA_PIN_DDR_DQ15 _PIN(98 )#define TEGRA_PIN_DDR_DQ16 _PIN(99 )#define TEGRA_PIN_DDR_DQ17 _PIN(100 )#define TEGRA_PIN_DDR_DQ18 _PIN(101 )#define TEGRA_PIN_DDR_DQ19 _PIN(102 )#define TEGRA_PIN_DDR_DQ20 _PIN(103 )#define TEGRA_PIN_DDR_DQ21 _PIN(104 )#define TEGRA_PIN_DDR_DQ22 _PIN(105 )#define TEGRA_PIN_DDR_DQ23 _PIN(106 )#define TEGRA_PIN_DDR_DQ24 _PIN(107 )#define TEGRA_PIN_DDR_DQ25 _PIN(108 )#define TEGRA_PIN_DDR_DQ26 _PIN(109 )#define TEGRA_PIN_DDR_DQ27 _PIN(110 )#define TEGRA_PIN_DDR_DQ28 _PIN(111 )#define TEGRA_PIN_DDR_DQ29 _PIN(112 )#define TEGRA_PIN_DDR_DQ30 _PIN(113 )#define TEGRA_PIN_DDR_DQ31 _PIN(114 )#define TEGRA_PIN_DDR_CS0_N _PIN(115 )#define TEGRA_PIN_DDR_CS1_N _PIN(116 )#define TEGRA_PIN_SYS_RESET _PIN(117 )#define TEGRA_PIN_JTAG_TRST_N _PIN(118 )#define TEGRA_PIN_JTAG_TDO _PIN(119 )#define TEGRA_PIN_JTAG_TMS _PIN(120 )#define TEGRA_PIN_JTAG_TCK _PIN(121 )#define TEGRA_PIN_JTAG_TDI _PIN(122 )#define TEGRA_PIN_TEST_MODE_EN _PIN(123 )static const struct pinctrl_pin_desc tegra20_pins[] = {"VI_GP6 PA0" ),"UART3_CTS_N PA1" ),"DAP2_FS PA2" ),"DAP2_SCLK PA3" ),"DAP2_DIN PA4" ),"DAP2_DOUT PA5" ),"SDIO3_CLK PA6" ),"SDIO3_CMD PA7" ),"GMI_AD17 PB0" ),"GMI_AD18 PB1" ),"LCD_PWR0 PB2" ),"LCD_PCLK PB3" ),"SDIO3_DAT3 PB4" ),"SDIO3_DAT2 PB5" ),"SDIO3_DAT1 PB6" ),"SDIO3_DAT0 PB7" ),"UART3_RTS_N PC0" ),"LCD_PWR1 PC1" ),"UART2_TXD PC2" ),"UART2_RXD PC3" ),"GEN1_I2C_SCL PC4" ),"GEN1_I2C_SDA PC5" ),"LCD_PWR2 PC6" ),"GMI_WP_N PC7" ),"SDIO3_DAT5 PD0" ),"SDIO3_DAT4 PD1" ),"VI_GP5 PD2" ),"SDIO3_DAT6 PD3" ),"SDIO3_DAT7 PD4" ),"VI_D1 PD5" ),"VI_VSYNC PD6" ),"VI_HSYNC PD7" ),"LCD_D0 PE0" ),"LCD_D1 PE1" ),"LCD_D2 PE2" ),"LCD_D3 PE3" ),"LCD_D4 PE4" ),"LCD_D5 PE5" ),"LCD_D6 PE6" ),"LCD_D7 PE7" ),"LCD_D8 PF0" ),"LCD_D9 PF1" ),"LCD_D10 PF2" ),"LCD_D11 PF3" ),"LCD_D12 PF4" ),"LCD_D13 PF5" ),"LCD_D14 PF6" ),"LCD_D15 PF7" ),"GMI_AD0 PG0" ),"GMI_AD1 PG1" ),"GMI_AD2 PG2" ),"GMI_AD3 PG3" ),"GMI_AD4 PG4" ),"GMI_AD5 PG5" ),"GMI_AD6 PG6" ),"GMI_AD7 PG7" ),"GMI_AD8 PH0" ),"GMI_AD9 PH1" ),"GMI_AD10 PH2" ),"GMI_AD11 PH3" ),"GMI_AD12 PH4" ),"GMI_AD13 PH5" ),"GMI_AD14 PH6" ),"GMI_AD15 PH7" ),"GMI_HIOW_N PI0" ),"GMI_HIOR_N PI1" ),"GMI_CS5_N PI2" ),"GMI_CS6_N PI3" ),"GMI_RST_N PI4" ),"GMI_IORDY PI5" ),"GMI_CS7_N PI6" ),"GMI_WAIT PI7" ),"GMI_CS0_N PJ0" ),"LCD_DE PJ1" ),"GMI_CS1_N PJ2" ),"LCD_HSYNC PJ3" ),"LCD_VSYNC PJ4" ),"UART2_CTS_N PJ5" ),"UART2_RTS_N PJ6" ),"GMI_AD16 PJ7" ),"GMI_ADV_N PK0" ),"GMI_CLK PK1" ),"GMI_CS4_N PK2" ),"GMI_CS2_N PK3" ),"GMI_CS3_N PK4" ),"SPDIF_OUT PK5" ),"SPDIF_IN PK6" ),"GMI_AD19 PK7" ),"VI_D2 PL0" ),"VI_D3 PL1" ),"VI_D4 PL2" ),"VI_D5 PL3" ),"VI_D6 PL4" ),"VI_D7 PL5" ),"VI_D8 PL6" ),"VI_D9 PL7" ),"LCD_D16 PM0" ),"LCD_D17 PM1" ),"LCD_D18 PM2" ),"LCD_D19 PM3" ),"LCD_D20 PM4" ),"LCD_D21 PM5" ),"LCD_D22 PM6" ),"LCD_D23 PM7" ),"DAP1_FS PN0" ),"DAP1_DIN PN1" ),"DAP1_DOUT PN2" ),"DAP1_SCLK PN3" ),"LCD_CS0_N PN4" ),"LCD_SDOUT PN5" ),"LCD_DC0 PN6" ),"HDMI_INT_N PN7" ),"ULPI_DATA7 PO0" ),"ULPI_DATA0 PO1" ),"ULPI_DATA1 PO2" ),"ULPI_DATA2 PO3" ),"ULPI_DATA3 PO4" ),"ULPI_DATA4 PO5" ),"ULPI_DATA5 PO6" ),"ULPI_DATA6 PO7" ),"DAP3_FS PP0" ),"DAP3_DIN PP1" ),"DAP3_DOUT PP2" ),"DAP3_SCLK PP3" ),"DAP4_FS PP4" ),"DAP4_DIN PP5" ),"DAP4_DOUT PP6" ),"DAP4_SCLK PP7" ),"KB_COL0 PQ0" ),"KB_COL1 PQ1" ),"KB_COL2 PQ2" ),"KB_COL3 PQ3" ),"KB_COL4 PQ4" ),"KB_COL5 PQ5" ),"KB_COL6 PQ6" ),"KB_COL7 PQ7" ),"KB_ROW0 PR0" ),"KB_ROW1 PR1" ),"KB_ROW2 PR2" ),"KB_ROW3 PR3" ),"KB_ROW4 PR4" ),"KB_ROW5 PR5" ),"KB_ROW6 PR6" ),"KB_ROW7 PR7" ),"KB_ROW8 PS0" ),"KB_ROW9 PS1" ),"KB_ROW10 PS2" ),"KB_ROW11 PS3" ),"KB_ROW12 PS4" ),"KB_ROW13 PS5" ),"KB_ROW14 PS6" ),"KB_ROW15 PS7" ),"VI_PCLK PT0" ),"VI_MCLK PT1" ),"VD_D10 PT2" ),"VI_D11 PT3" ),"VI_D0 PT4" ),"GEN2_I2C_SCL PT5" ),"GEN2_I2C_SDA PT6" ),"GMI_DPD PT7" ),/* PU0..6: GPIO only */ "PU0" ),"PU1" ),"PU2" ),"PU3" ),"PU4" ),"PU5" ),"PU6" ),"JTAG_RTCK PU7" ),/* PV0..1: GPIO only */ "PV0" ),"PV1" ),/* PV2..3: Balls are named after GPIO not function */ "PV2" ),"PV3" ),/* PV4..6: GPIO only */ "PV4" ),"PV5" ),"PV6" ),"LCD_DC1 PV7" ),"LCD_CS1_N PW0" ),"LCD_M1 PW1" ),"SPI2_CS1_N PW2" ),"SPI2_CS2_N PW3" ),"DAP_MCLK1 PW4" ),"DAP_MCLK2 PW5" ),"UART3_TXD PW6" ),"UART3_RXD PW7" ),"SPI2_MOSI PX0" ),"SPI2_MISO PX1" ),"SPI2_SCK PX2" ),"SPI2_CS0_N PX3" ),"SPI1_MOSI PX4" ),"SPI1_SCK PX5" ),"SPI1_CS0_N PX6" ),"SPI1_MISO PX7" ),"ULPI_CLK PY0" ),"ULPI_DIR PY1" ),"ULPI_NXT PY2" ),"ULPI_STP PY3" ),"SDIO1_DAT3 PY4" ),"SDIO1_DAT2 PY5" ),"SDIO1_DAT1 PY6" ),"SDIO1_DAT0 PY7" ),"SDIO1_CLK PZ0" ),"SDIO1_CMD PZ1" ),"LCD_SDIN PZ2" ),"LCD_WR_N PZ3" ),"LCD_SCK PZ4" ),"SYS_CLK_REQ PZ5" ),"PWR_I2C_SCL PZ6" ),"PWR_I2C_SDA PZ7" ),"GMI_AD20 PAA0" ),"GMI_AD21 PAA1" ),"GMI_AD22 PAA2" ),"GMI_AD23 PAA3" ),"GMI_AD24 PAA4" ),"GMI_AD25 PAA5" ),"GMI_AD26 PAA6" ),"GMI_AD27 PAA7" ),"LED_BLINK PBB0" ),"VI_GP0 PBB1" ),"CAM_I2C_SCL PBB2" ),"CAM_I2C_SDA PBB3" ),"VI_GP3 PBB4" ),"VI_GP4 PBB5" ),"PBB6" ),"PBB7" ),"CRT_HSYNC" ),"CRT_VSYNC" ),"DDC_SCL" ),"DDC_SDA" ),"OWC" ),"CORE_PWR_REQ" ),"CPU_PWR_REQ" ),"PWR_INT_N" ),"CLK_32_K_IN" ),"DDR_COMP_PD" ),"DDR_COMP_PU" ),"DDR_A0" ),"DDR_A1" ),"DDR_A2" ),"DDR_A3" ),"DDR_A4" ),"DDR_A5" ),"DDR_A6" ),"DDR_A7" ),"DDR_A8" ),"DDR_A9" ),"DDR_A10" ),"DDR_A11" ),"DDR_A12" ),"DDR_A13" ),"DDR_A14" ),"DDR_CAS_N" ),"DDR_BA0" ),"DDR_BA1" ),"DDR_BA2" ),"DDR_DQS0P" ),"DDR_DQS0N" ),"DDR_DQS1P" ),"DDR_DQS1N" ),"DDR_DQS2P" ),"DDR_DQS2N" ),"DDR_DQS3P" ),"DDR_DQS3N" ),"DDR_CKE0" ),"DDR_CKE1" ),"DDR_CLK" ),"DDR_CLK_N" ),"DDR_DM0" ),"DDR_DM1" ),"DDR_DM2" ),"DDR_DM3" ),"DDR_ODT" ),"DDR_QUSE0" ),"DDR_QUSE1" ),"DDR_QUSE2" ),"DDR_QUSE3" ),"DDR_RAS_N" ),"DDR_WE_N" ),"DDR_DQ0" ),"DDR_DQ1" ),"DDR_DQ2" ),"DDR_DQ3" ),"DDR_DQ4" ),"DDR_DQ5" ),"DDR_DQ6" ),"DDR_DQ7" ),"DDR_DQ8" ),"DDR_DQ9" ),"DDR_DQ10" ),"DDR_DQ11" ),"DDR_DQ12" ),"DDR_DQ13" ),"DDR_DQ14" ),"DDR_DQ15" ),"DDR_DQ16" ),"DDR_DQ17" ),"DDR_DQ18" ),"DDR_DQ19" ),"DDR_DQ20" ),"DDR_DQ21" ),"DDR_DQ22" ),"DDR_DQ23" ),"DDR_DQ24" ),"DDR_DQ25" ),"DDR_DQ26" ),"DDR_DQ27" ),"DDR_DQ28" ),"DDR_DQ29" ),"DDR_DQ30" ),"DDR_DQ31" ),"DDR_CS0_N" ),"DDR_CS1_N" ),"SYS_RESET" ),"JTAG_TRST_N" ),"JTAG_TDO" ),"JTAG_TMS" ),"JTAG_TCK" ),"JTAG_TDI" ),"TEST_MODE_EN" ),static const unsigned ata_pins[] = {static const unsigned atb_pins[] = {static const unsigned atc_pins[] = {static const unsigned atd_pins[] = {static const unsigned ate_pins[] = {static const unsigned cdev1_pins[] = {static const unsigned cdev2_pins[] = {static const unsigned crtp_pins[] = {static const unsigned csus_pins[] = {static const unsigned dap1_pins[] = {static const unsigned dap2_pins[] = {static const unsigned dap3_pins[] = {static const unsigned dap4_pins[] = {static const unsigned ddc_pins[] = {static const unsigned dta_pins[] = {static const unsigned dtb_pins[] = {static const unsigned dtc_pins[] = {static const unsigned dtd_pins[] = {static const unsigned dte_pins[] = {static const unsigned dtf_pins[] = {static const unsigned gma_pins[] = {static const unsigned gmb_pins[] = {static const unsigned gmc_pins[] = {static const unsigned gmd_pins[] = {static const unsigned gme_pins[] = {static const unsigned gpu_pins[] = {static const unsigned gpu7_pins[] = {static const unsigned gpv_pins[] = {static const unsigned hdint_pins[] = {static const unsigned i2cp_pins[] = {static const unsigned irrx_pins[] = {static const unsigned irtx_pins[] = {static const unsigned kbca_pins[] = {static const unsigned kbcb_pins[] = {static const unsigned kbcc_pins[] = {static const unsigned kbcd_pins[] = {static const unsigned kbce_pins[] = {static const unsigned kbcf_pins[] = {static const unsigned lcsn_pins[] = {static const unsigned ld0_pins[] = {static const unsigned ld1_pins[] = {static const unsigned ld2_pins[] = {static const unsigned ld3_pins[] = {static const unsigned ld4_pins[] = {static const unsigned ld5_pins[] = {static const unsigned ld6_pins[] = {static const unsigned ld7_pins[] = {static const unsigned ld8_pins[] = {static const unsigned ld9_pins[] = {static const unsigned ld10_pins[] = {static const unsigned ld11_pins[] = {static const unsigned ld12_pins[] = {static const unsigned ld13_pins[] = {static const unsigned ld14_pins[] = {static const unsigned ld15_pins[] = {static const unsigned ld16_pins[] = {static const unsigned ld17_pins[] = {static const unsigned ldc_pins[] = {static const unsigned ldi_pins[] = {static const unsigned lhp0_pins[] = {static const unsigned lhp1_pins[] = {static const unsigned lhp2_pins[] = {static const unsigned lhs_pins[] = {static const unsigned lm0_pins[] = {static const unsigned lm1_pins[] = {static const unsigned lpp_pins[] = {static const unsigned lpw0_pins[] = {static const unsigned lpw1_pins[] = {static const unsigned lpw2_pins[] = {static const unsigned lsc0_pins[] = {static const unsigned lsc1_pins[] = {static const unsigned lsck_pins[] = {static const unsigned lsda_pins[] = {static const unsigned lsdi_pins[] = {static const unsigned lspi_pins[] = {static const unsigned lvp0_pins[] = {static const unsigned lvp1_pins[] = {static const unsigned lvs_pins[] = {static const unsigned ls_pins[] = {static const unsigned lc_pins[] = {static const unsigned ld17_0_pins[] = {static const unsigned ld19_18_pins[] = {static const unsigned ld21_20_pins[] = {static const unsigned ld23_22_pins[] = {static const unsigned owc_pins[] = {static const unsigned pmc_pins[] = {static const unsigned pta_pins[] = {static const unsigned rm_pins[] = {static const unsigned sdb_pins[] = {static const unsigned sdc_pins[] = {static const unsigned sdd_pins[] = {static const unsigned sdio1_pins[] = {static const unsigned slxa_pins[] = {static const unsigned slxc_pins[] = {static const unsigned slxd_pins[] = {static const unsigned slxk_pins[] = {static const unsigned spdi_pins[] = {static const unsigned spdo_pins[] = {static const unsigned spia_pins[] = {static const unsigned spib_pins[] = {static const unsigned spic_pins[] = {static const unsigned spid_pins[] = {static const unsigned spie_pins[] = {static const unsigned spif_pins[] = {static const unsigned spig_pins[] = {static const unsigned spih_pins[] = {static const unsigned uaa_pins[] = {static const unsigned uab_pins[] = {static const unsigned uac_pins[] = {static const unsigned ck32_pins[] = {static const unsigned uad_pins[] = {static const unsigned uca_pins[] = {static const unsigned ucb_pins[] = {static const unsigned uda_pins[] = {static const unsigned ddrc_pins[] = {static const unsigned pmca_pins[] = {static const unsigned pmcb_pins[] = {static const unsigned pmcc_pins[] = {static const unsigned pmcd_pins[] = {static const unsigned pmce_pins[] = {static const unsigned xm2c_pins[] = {static const unsigned xm2d_pins[] = {static const unsigned drive_ao1_pins[] = {static const unsigned drive_ao2_pins[] = {static const unsigned drive_at1_pins[] = {static const unsigned drive_at2_pins[] = {static const unsigned drive_cdev1_pins[] = {static const unsigned drive_cdev2_pins[] = {static const unsigned drive_csus_pins[] = {static const unsigned drive_dap1_pins[] = {static const unsigned drive_dap2_pins[] = {static const unsigned drive_dap3_pins[] = {static const unsigned drive_dap4_pins[] = {static const unsigned drive_dbg_pins[] = {static const unsigned drive_lcd1_pins[] = {static const unsigned drive_lcd2_pins[] = {static const unsigned drive_sdmmc2_pins[] = {static const unsigned drive_sdmmc3_pins[] = {static const unsigned drive_spi_pins[] = {static const unsigned drive_uaa_pins[] = {static const unsigned drive_uab_pins[] = {static const unsigned drive_uart2_pins[] = {static const unsigned drive_uart3_pins[] = {static const unsigned drive_vi1_pins[] = {static const unsigned drive_vi2_pins[] = {static const unsigned drive_xm2a_pins[] = {static const unsigned drive_xm2c_pins[] = {static const unsigned drive_xm2d_pins[] = {static const unsigned drive_xm2clk_pins[] = {static const unsigned drive_sdio1_pins[] = {static const unsigned drive_crt_pins[] = {static const unsigned drive_ddc_pins[] = {static const unsigned drive_gma_pins[] = {static const unsigned drive_gmb_pins[] = {static const unsigned drive_gmc_pins[] = {static const unsigned drive_gmd_pins[] = {static const unsigned drive_gme_pins[] = {static const unsigned drive_owr_pins[] = {static const unsigned drive_uda_pins[] = {enum tegra_mux {#define FUNCTION(fname) #fname static const char * const tegra20_functions[] = {#define TRISTATE_REG_A 0 x14#define PIN_MUX_CTL_REG_A 0 x80#define PULLUPDOWN_REG_A 0 xa0#define PINGROUP_REG_A 0 x868/* Pin group with mux control, and typically tri-state and pull-up/down too */ #define MUX_PG(pg_name, f0, f1, f2, f3, \#pg_name , \## _pins, \## _pins), \## f0, \## f1, \## f2, \## f3, \1 , \2 , \0 , \1 , \1 , \1 , \1 , \1 , \1 , \0 , \/* Pin groups with only pull up and pull down control */ #define PULL_PG(pg_name, pupd_r, pupd_b) \#pg_name , \## _pins, \## _pins), \1 , \2 , \1 , \0 , \/* Pin groups for drive strength registers (configurable version) */ #define DRV_PG_EXT(pg_name, r, hsm_b, schmitt_b, lpmd_b, \"drive_" #pg_name , \## pg_name## _pins, \## pg_name## _pins), \1 , \1 , \1 , \3 , \0 , \5 , \5 , \1 , \/* Pin groups for drive strength registers (simple version) */ #define DRV_PG(pg_name, r) \2 , 3 , 4 , 12 , 20 , 28 , 2 , 30 , 2 )static const struct tegra_pingroup tegra20_groups[] = {/* name, f0, f1, f2, f3, tri r/b, mux r/b, pupd r/b */ 0 x14, 0 , 0 x80, 24 , 0 xa0, 0 ),0 x14, 1 , 0 x80, 16 , 0 xa0, 2 ),0 x14, 2 , 0 x80, 22 , 0 xa0, 4 ),0 x14, 3 , 0 x80, 20 , 0 xa0, 6 ),0 x18, 25 , 0 x80, 12 , 0 xa0, 8 ),0 x14, 4 , 0 x88, 2 , 0 xa8, 0 ),0 x14, 5 , 0 x88, 4 , 0 xa8, 2 ),0 x20, 14 , 0 x98, 20 , 0 xa4, 24 ),0 x14, 6 , 0 x88, 6 , 0 xac, 24 ),0 x14, 7 , 0 x88, 20 , 0 xa0, 10 ),0 x14, 8 , 0 x88, 22 , 0 xa0, 12 ),0 x14, 9 , 0 x88, 24 , 0 xa0, 14 ),0 x14, 10 , 0 x88, 26 , 0 xa0, 16 ),0 x18, 31 , 0 x88, 0 , 0 xb0, 28 ),0 x14, 11 , 0 x84, 20 , 0 xa0, 18 ),0 x14, 12 , 0 x84, 22 , 0 xa0, 20 ),0 x14, 13 , 0 x84, 26 , 0 xa0, 22 ),0 x14, 14 , 0 x84, 28 , 0 xa0, 24 ),0 x14, 15 , 0 x84, 30 , 0 xa0, 26 ),0 x20, 12 , 0 x98, 30 , 0 xa0, 28 ),0 x14, 28 , 0 x84, 0 , 0 xb0, 20 ),0 x18, 29 , 0 x88, 28 , 0 xb0, 22 ),0 x14, 29 , 0 x84, 2 , 0 xb0, 24 ),0 x18, 30 , 0 x88, 30 , 0 xb0, 26 ),0 x18, 0 , 0 x8c, 0 , 0 xa8, 24 ),0 x14, 16 , 0 x8c, 4 , 0 xa4, 20 ),0 x20, 11 , 0 x98, 28 , 0 xa4, 6 ),0 x14, 17 , 0 x8c, 2 , 0 xa0, 30 ),0 x1c, 23 , 0 x84, 4 , -1 , -1 ),0 x14, 18 , 0 x88, 8 , 0 xa4, 2 ),0 x14, 20 , 0 x88, 18 , 0 xa8, 22 ),0 x14, 19 , 0 x88, 16 , 0 xa8, 20 ),0 x14, 22 , 0 x88, 10 , 0 xa4, 8 ),0 x14, 21 , 0 x88, 12 , 0 xa4, 10 ),0 x18, 26 , 0 x88, 14 , 0 xa4, 12 ),0 x20, 10 , 0 x98, 26 , 0 xa4, 14 ),0 x14, 26 , 0 x80, 28 , 0 xb0, 2 ),0 x14, 27 , 0 x80, 26 , 0 xb0, 0 ),0 x1c, 31 , 0 x90, 12 , -1 , -1 ),0 x1c, 0 , 0 x94, 0 , -1 , -1 ),0 x1c, 1 , 0 x94, 2 , -1 , -1 ),0 x1c, 2 , 0 x94, 4 , -1 , -1 ),0 x1c, 3 , 0 x94, 6 , -1 , -1 ),0 x1c, 4 , 0 x94, 8 , -1 , -1 ),0 x1c, 5 , 0 x94, 10 , -1 , -1 ),0 x1c, 6 , 0 x94, 12 , -1 , -1 ),0 x1c, 7 , 0 x94, 14 , -1 , -1 ),0 x1c, 8 , 0 x94, 16 , -1 , -1 ),0 x1c, 9 , 0 x94, 18 , -1 , -1 ),0 x1c, 10 , 0 x94, 20 , -1 , -1 ),0 x1c, 11 , 0 x94, 22 , -1 , -1 ),0 x1c, 12 , 0 x94, 24 , -1 , -1 ),0 x1c, 13 , 0 x94, 26 , -1 , -1 ),0 x1c, 14 , 0 x94, 28 , -1 , -1 ),0 x1c, 15 , 0 x94, 30 , -1 , -1 ),0 x1c, 16 , 0 x98, 0 , -1 , -1 ),0 x1c, 17 , 0 x98, 2 , -1 , -1 ),0 x1c, 30 , 0 x90, 14 , -1 , -1 ),0 x20, 6 , 0 x98, 16 , -1 , -1 ),0 x1c, 18 , 0 x98, 10 , -1 , -1 ),0 x1c, 19 , 0 x98, 4 , -1 , -1 ),0 x1c, 20 , 0 x98, 6 , -1 , -1 ),0 x20, 7 , 0 x90, 22 , -1 , -1 ),0 x1c, 24 , 0 x90, 26 , -1 , -1 ),0 x1c, 25 , 0 x90, 28 , -1 , -1 ),0 x20, 8 , 0 x98, 14 , -1 , -1 ),0 x20, 3 , 0 x90, 0 , -1 , -1 ),0 x20, 4 , 0 x90, 2 , -1 , -1 ),0 x20, 5 , 0 x90, 4 , -1 , -1 ),0 x1c, 27 , 0 x90, 18 , -1 , -1 ),0 x1c, 28 , 0 x90, 20 , -1 , -1 ),0 x1c, 29 , 0 x90, 16 , -1 , -1 ),0 x20, 1 , 0 x90, 8 , -1 , -1 ),0 x20, 2 , 0 x90, 6 , -1 , -1 ),0 x20, 0 , 0 x90, 10 , -1 , -1 ),0 x1c, 21 , 0 x90, 30 , -1 , -1 ),0 x1c, 22 , 0 x98, 8 , -1 , -1 ),0 x1c, 26 , 0 x90, 24 , -1 , -1 ),0 x14, 31 , 0 x84, 8 , 0 xb0, 30 ),0 x14, 23 , 0 x98, 18 , -1 , -1 ),0 x14, 24 , 0 x98, 22 , 0 xa4, 4 ),0 x14, 25 , 0 x80, 14 , 0 xa4, 0 ),0 x20, 15 , 0 x8c, 10 , -1 , -1 ),0 x18, 1 , 0 x8c, 12 , 0 xac, 28 ),0 x18, 2 , 0 x8c, 14 , 0 xac, 30 ),0 x14, 30 , 0 x80, 30 , 0 xb0, 18 ),0 x18, 3 , 0 x84, 6 , 0 xa4, 22 ),0 x18, 5 , 0 x84, 10 , 0 xa4, 26 ),0 x18, 6 , 0 x84, 12 , 0 xa4, 28 ),0 x18, 7 , 0 x84, 14 , 0 xa4, 30 ),0 x18, 8 , 0 x8c, 8 , 0 xa4, 16 ),0 x18, 9 , 0 x8c, 6 , 0 xa4, 18 ),0 x18, 10 , 0 x8c, 30 , 0 xa8, 4 ),0 x18, 11 , 0 x8c, 28 , 0 xa8, 6 ),0 x18, 12 , 0 x8c, 26 , 0 xa8, 8 ),0 x18, 13 , 0 x8c, 24 , 0 xa8, 10 ),0 x18, 14 , 0 x8c, 22 , 0 xa8, 12 ),0 x18, 15 , 0 x8c, 20 , 0 xa8, 14 ),0 x18, 16 , 0 x8c, 18 , 0 xa8, 16 ),0 x18, 17 , 0 x8c, 16 , 0 xa8, 18 ),0 x18, 18 , 0 x80, 0 , 0 xac, 0 ),0 x18, 19 , 0 x80, 2 , 0 xac, 2 ),0 x18, 20 , 0 x80, 4 , 0 xac, 4 ),0 x18, 21 , 0 x80, 6 , 0 xac, 6 ),0 x18, 22 , 0 x84, 16 , 0 xac, 8 ),0 x18, 23 , 0 x84, 18 , 0 xac, 10 ),0 x20, 13 , 0 x80, 8 , 0 xb0, 16 ),/* pg_name, pupd_r/b */ 0 xb0, 14 ),0 xac, 26 ),0 xb0, 4 ),0 xb0, 6 ),0 xb0, 8 ),0 xb0, 10 ),0 xb0, 12 ),0 xa8, 30 ),0 xa8, 28 ),0 xac, 20 ),0 xac, 22 ),0 xac, 12 ),0 xac, 14 ),0 xac, 16 ),0 xac, 18 ),/* pg_name, r */ 0 x868),0 x86c),0 x870),0 x874),0 x878),0 x87c),0 x880),0 x884),0 x888),0 x88c),0 x890),0 x894),0 x898),0 x89c),0 x8a0),0 x8a4),0 x8a8),0 x8ac),0 x8b0),0 x8b4),0 x8b8),0 x8bc),0 x8c0),/* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvup_b, slwr_b, slwr_w, slwf_b, slwf_w */ 0 x8c4, -1 , -1 , 4 , 14 , 19 , 24 , 4 , 28 , 4 ),0 x8c8, -1 , 3 , -1 , 14 , 19 , 24 , 4 , 28 , 4 ),0 x8cc, -1 , 3 , -1 , 14 , 19 , 24 , 4 , 28 , 4 ),0 x8d0, -1 , -1 , -1 , 14 , 19 , 24 , 4 , 28 , 4 ),/* pg_name, r */ 0 x8e0),0 x8ec),0 x8f0),0 x8f4),0 x8f8),0 x8fc),0 x900),0 x904),0 x908),0 x90c),static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {"nvidia,tegra20-gpio" ,false ,false ,false ,static const char *cdev1_parents[] = {"dev1_osc_div" , "pll_a_out0" , "pll_m_out1" , "audio" ,static const char *cdev2_parents[] = {"dev2_osc_div" , "hclk" , "pclk" , "pll_p_out4" ,static void tegra20_pinctrl_register_clock_muxes(struct platform_device *pdev)struct tegra_pmx *pmx = platform_get_drvdata(pdev);"cdev1_mux" , cdev1_parents, 4 , 0 ,1 ] + 0 x8, 2 , 2 , CLK_MUX_READ_ONLY, NULL);"cdev2_mux" , cdev2_parents, 4 , 0 ,1 ] + 0 x8, 4 , 2 , CLK_MUX_READ_ONLY, NULL);static int tegra20_pinctrl_probe(struct platform_device *pdev)int err;if (err)return err;return 0 ;static const struct of_device_id tegra20_pinctrl_of_match[] = {"nvidia,tegra20-pinmux" , },static struct platform_driver tegra20_pinctrl_driver = {"tegra20-pinctrl" ,static int __init tegra20_pinctrl_init(void )return platform_driver_register(&tegra20_pinctrl_driver);
Messung V0.5 in Prozent C=98 H=100 G=98
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