/* * Allwinner new F-series F1C100s SoC (suniv) pinctrl driver. * * Copyright (C) 2018 Icenowy Zheng * * Icenowy Zheng <icenowy@aosc.io> * * Copyright (C) 2014 Jackie Hwang * * Jackie Hwang <huangshr@allwinnertech.com> * * Copyright (C) 2014 Chen-Yu Tsai * * Chen-Yu Tsai <wens@csie.org> * * Copyright (C) 2014 Maxime Ripard * * Maxime Ripard <maxime.ripard@free-electrons.com> * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. #include <linux/module.h>#include <linux/platform_device.h>#include <linux/of.h>#include <linux/pinctrl/pinctrl.h>#include "pinctrl-sunxi.h" static const struct sunxi_desc_pin suniv_f1c100s_pins[] = {0 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "rtp" ), /* X1 */ 0 x4, "i2s" ), /* BCLK */ 0 x5, "uart1" ), /* RTS */ 0 x6, "spi1" )), /* CS */ 1 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "rtp" ), /* X2 */ 0 x4, "i2s" ), /* LRCK */ 0 x5, "uart1" ), /* CTS */ 0 x6, "spi1" )), /* MOSI */ 2 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "rtp" ), /* Y1 */ 0 x3, "pwm0" ), /* PWM0 */ 0 x4, "i2s" ), /* IN */ 0 x5, "uart1" ), /* RX */ 0 x6, "spi1" )), /* CLK */ 3 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "rtp" ), /* Y2 */ 0 x3, "ir0" ), /* RX */ 0 x4, "i2s" ), /* OUT */ 0 x5, "uart1" ), /* TX */ 0 x6, "spi1" )), /* MISO */ /* Hole */ 0 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "dram" ), /* DQS0 */ 0 x3, "i2c1" ), /* SCK */ 0 x4, "i2s" ), /* BCLK */ 0 x5, "uart1" ), /* RTS */ 0 x6, "spi1" )), /* CS */ 1 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "dram" ), /* DQS1 */ 0 x3, "i2c1" ), /* SDA */ 0 x4, "i2s" ), /* LRCK */ 0 x5, "uart1" ), /* CTS */ 0 x6, "spi1" )), /* MOSI */ 2 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "dram" ), /* CKE */ 0 x3, "pwm0" ), /* PWM0 */ 0 x4, "i2s" ), /* IN */ 0 x5, "uart1" ), /* RX */ 0 x6, "spi1" )), /* CLK */ 3 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "dram" ), /* DDR_REF_D */ 0 x3, "ir0" ), /* RX */ 0 x4, "i2s" ), /* OUT */ 0 x5, "uart1" ), /* TX */ 0 x6, "spi1" )), /* MISO */ /* Hole */ 0 ),0 x1, "gpio_out" ),0 x2, "spi0" ), /* CLK */ 0 x3, "mmc1" )), /* CLK */ 1 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "spi0" ), /* CS */ 0 x3, "mmc1" )), /* CMD */ 2 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "spi0" ), /* MISO */ 0 x3, "mmc1" )), /* D0 */ 3 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "spi0" ), /* MOSI */ 0 x3, "uart0" )), /* TX */ /* Hole */ 0 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* D2 */ 0 x3, "i2c0" ), /* SDA */ 0 x4, "rsb" ), /* SDA */ 0 x6, 0 , 0 )),1 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* D3 */ 0 x3, "uart1" ), /* RTS */ 0 x6, 0 , 1 )),2 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* D4*/ 0 x3, "uart1" ), /* CTS */ 0 x6, 0 , 2 )),3 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* D5 */ 0 x3, "uart1" ), /* RX */ 0 x6, 0 , 3 )),4 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* D6 */ 0 x3, "uart1" ), /* TX */ 0 x6, 0 , 4 )),5 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* D7 */ 0 x3, "i2c1" ), /* SCK */ 0 x6, 0 , 5 )),6 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* D10 */ 0 x3, "i2c1" ), /* SDA */ 0 x6, 0 , 6 )),7 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* D11 */ 0 x3, "i2s" ), /* MCLK */ 0 x6, 0 , 7 )),8 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* D12 */ 0 x3, "i2s" ), /* BCLK */ 0 x6, 0 , 8 )),9 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* D13 */ 0 x3, "i2s" ), /* LRCK */ 0 x6, 0 , 9 )),10 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* D14 */ 0 x3, "i2s" ), /* IN */ 0 x6, 0 , 10 )),11 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* D15 */ 0 x3, "i2s" ), /* OUT */ 0 x6, 0 , 11 )),12 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* D18 */ 0 x3, "i2c0" ), /* SCK */ 0 x4, "rsb" ), /* SCK */ 0 x6, 0 , 12 )),13 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* D19 */ 0 x3, "uart2" ), /* TX */ 0 x6, 0 , 13 )),14 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* D20 */ 0 x3, "uart2" ), /* RX */ 0 x6, 0 , 14 )),15 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* D21 */ 0 x3, "uart2" ), /* RTS */ 0 x4, "i2c2" ), /* SCK */ 0 x6, 0 , 15 )),16 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* D22 */ 0 x3, "uart2" ), /* CTS */ 0 x4, "i2c2" ), /* SDA */ 0 x6, 0 , 16 )),17 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* D23 */ 0 x3, "spdif" ), /* OUT */ 0 x6, 0 , 17 )),18 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* CLK */ 0 x3, "spi0" ), /* CS */ 0 x6, 0 , 18 )),19 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* DE */ 0 x3, "spi0" ), /* MOSI */ 0 x6, 0 , 19 )),20 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* HYSNC */ 0 x3, "spi0" ), /* CLK */ 0 x6, 0 , 20 )),21 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "lcd" ), /* VSYNC */ 0 x3, "spi0" ), /* MISO */ 0 x6, 0 , 21 )),/* Hole */ 0 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "csi" ), /* HSYNC */ 0 x3, "lcd" ), /* D0 */ 0 x4, "i2c2" ), /* SCK */ 0 x5, "uart0" ), /* RX */ 0 x6, 1 , 0 )),1 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "csi" ), /* VSYNC */ 0 x3, "lcd" ), /* D1 */ 0 x4, "i2c2" ), /* SDA */ 0 x5, "uart0" ), /* TX */ 0 x6, 1 , 1 )),2 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "csi" ), /* PCLK */ 0 x3, "lcd" ), /* D8 */ 0 x4, "clk" ), /* OUT */ 0 x6, 1 , 2 )),3 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "csi" ), /* D0 */ 0 x3, "lcd" ), /* D9 */ 0 x4, "i2s" ), /* BCLK */ 0 x5, "rsb" ), /* SCK */ 0 x6, 1 , 3 )),4 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "csi" ), /* D1 */ 0 x3, "lcd" ), /* D16 */ 0 x4, "i2s" ), /* LRCK */ 0 x5, "rsb" ), /* SDA */ 0 x6, 1 , 4 )),5 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "csi" ), /* D2 */ 0 x3, "lcd" ), /* D17 */ 0 x4, "i2s" ), /* IN */ 0 x6, 1 , 5 )),6 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "csi" ), /* D3 */ 0 x3, "pwm1" ), /* PWM1 */ 0 x4, "i2s" ), /* OUT */ 0 x5, "spdif" ), /* OUT */ 0 x6, 1 , 6 )),7 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "csi" ), /* D4 */ 0 x3, "uart2" ), /* TX */ 0 x4, "spi1" ), /* CS */ 0 x6, 1 , 7 )),8 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "csi" ), /* D5 */ 0 x3, "uart2" ), /* RX */ 0 x4, "spi1" ), /* MOSI */ 0 x6, 1 , 8 )),9 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "csi" ), /* D6 */ 0 x3, "uart2" ), /* RTS */ 0 x4, "spi1" ), /* CLK */ 0 x6, 1 , 9 )),10 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "csi" ), /* D7 */ 0 x3, "uart2" ), /* CTS */ 0 x4, "spi1" ), /* MISO */ 0 x6, 1 , 10 )),11 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "clk0" ), /* OUT */ 0 x3, "i2c0" ), /* SCK */ 0 x4, "ir" ), /* RX */ 0 x6, 1 , 11 )),12 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "i2s" ), /* MCLK */ 0 x3, "i2c0" ), /* SDA */ 0 x4, "pwm0" ), /* PWM0 */ 0 x6, 1 , 12 )),/* Hole */ 0 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "mmc0" ), /* D1 */ 0 x3, "jtag" ), /* MS */ 0 x4, "ir0" ), /* MS */ 0 x6, 2 , 0 )),1 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "mmc0" ), /* D0 */ 0 x3, "dgb0" ), /* DI */ 0 x6, 2 , 1 )),2 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "mmc0" ), /* CLK */ 0 x3, "uart0" ), /* TX */ 0 x6, 2 , 2 )),3 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "mmc0" ), /* CMD */ 0 x3, "jtag" ), /* DO */ 0 x6, 2 , 3 )),4 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "mmc0" ), /* D3 */ 0 x3, "uart0" ), /* TX */ 0 x6, 2 , 4 )),5 ),0 x0, "gpio_in" ),0 x1, "gpio_out" ),0 x2, "mmc0" ), /* D2 */ 0 x3, "jtag" ), /* CK */ 0 x4, "pwm1" ), /* PWM1 */ 0 x6, 2 , 5 )),static const struct sunxi_pinctrl_desc suniv_f1c100s_pinctrl_data = {3 ,static int suniv_pinctrl_probe(struct platform_device *pdev)return sunxi_pinctrl_init(pdev,static const struct of_device_id suniv_f1c100s_pinctrl_match[] = {"allwinner,suniv-f1c100s-pinctrl" , },static struct platform_driver suniv_f1c100s_pinctrl_driver = {"suniv-f1c100s-pinctrl" ,
Messung V0.5 in Prozent C=94 H=96 G=94
¤ Dauer der Verarbeitung: 0.11 Sekunden
(vorverarbeitet am 2026-06-08)
¤ *© Formatika GbR, Deutschland
