// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2012-2013 Renesas Solutions Corp. * Copyright (C) 2013 Magnus Damm * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> #include <linux/io.h>#include <linux/kernel.h>#include <linux/pinctrl/pinconf-generic.h>#include "sh_pfc.h" #define CPU_ALL_PORT(fn, pfx, sfx) \/* Port0 - Port30 */ \ 0 , fn, pfx, sfx), \10 , fn, pfx## 1 , sfx), \20 , fn, pfx## 2 , sfx), \30 , fn, pfx## 30 , sfx), \/* Port32 - Port40 */ \ 32 , fn, pfx## 32 , sfx), PORT_1(33 , fn, pfx## 33 , sfx), \34 , fn, pfx## 34 , sfx), PORT_1(35 , fn, pfx## 35 , sfx), \36 , fn, pfx## 36 , sfx), PORT_1(37 , fn, pfx## 37 , sfx), \38 , fn, pfx## 38 , sfx), PORT_1(39 , fn, pfx## 39 , sfx), \40 , fn, pfx## 40 , sfx), \/* Port64 - Port85 */ \ 64 , fn, pfx## 64 , sfx), PORT_1(65 , fn, pfx## 65 , sfx), \66 , fn, pfx## 66 , sfx), PORT_1(67 , fn, pfx## 67 , sfx), \68 , fn, pfx## 68 , sfx), PORT_1(69 , fn, pfx## 69 , sfx), \70 , fn, pfx## 7 , sfx), \80 , fn, pfx## 80 , sfx), PORT_1(81 , fn, pfx## 81 , sfx), \82 , fn, pfx## 82 , sfx), PORT_1(83 , fn, pfx## 83 , sfx), \84 , fn, pfx## 84 , sfx), PORT_1(85 , fn, pfx## 85 , sfx), \/* Port96 - Port126 */ \ 96 , fn, pfx## 96 , sfx), PORT_1(97 , fn, pfx## 97 , sfx), \98 , fn, pfx## 98 , sfx), PORT_1(99 , fn, pfx## 99 , sfx), \100 , fn, pfx## 10 , sfx), \110 , fn, pfx## 11 , sfx), \120 , fn, pfx## 120 , sfx), PORT_1(121 , fn, pfx## 121 , sfx), \122 , fn, pfx## 122 , sfx), PORT_1(123 , fn, pfx## 123 , sfx), \124 , fn, pfx## 124 , sfx), PORT_1(125 , fn, pfx## 125 , sfx), \126 , fn, pfx## 126 , sfx), \/* Port128 - Port134 */ \ 128 , fn, pfx## 128 , sfx), PORT_1(129 , fn, pfx## 129 , sfx), \130 , fn, pfx## 130 , sfx), PORT_1(131 , fn, pfx## 131 , sfx), \132 , fn, pfx## 132 , sfx), PORT_1(133 , fn, pfx## 133 , sfx), \134 , fn, pfx## 134 , sfx), \/* Port160 - Port178 */ \ 160 , fn, pfx## 16 , sfx), \170 , fn, pfx## 170 , sfx), PORT_1(171 , fn, pfx## 171 , sfx), \172 , fn, pfx## 172 , sfx), PORT_1(173 , fn, pfx## 173 , sfx), \174 , fn, pfx## 174 , sfx), PORT_1(175 , fn, pfx## 175 , sfx), \176 , fn, pfx## 176 , sfx), PORT_1(177 , fn, pfx## 177 , sfx), \178 , fn, pfx## 178 , sfx), \/* Port192 - Port222 */ \ 192 , fn, pfx## 192 , sfx), PORT_1(193 , fn, pfx## 193 , sfx), \194 , fn, pfx## 194 , sfx), PORT_1(195 , fn, pfx## 195 , sfx), \196 , fn, pfx## 196 , sfx), PORT_1(197 , fn, pfx## 197 , sfx), \198 , fn, pfx## 198 , sfx), PORT_1(199 , fn, pfx## 199 , sfx), \200 , fn, pfx## 20 , sfx), \210 , fn, pfx## 21 , sfx), \220 , fn, pfx## 220 , sfx), PORT_1(221 , fn, pfx## 221 , sfx), \222 , fn, pfx## 222 , sfx), \/* Port224 - Port250 */ \ 224 , fn, pfx## 224 , sfx), PORT_1(225 , fn, pfx## 225 , sfx), \226 , fn, pfx## 226 , sfx), PORT_1(227 , fn, pfx## 227 , sfx), \228 , fn, pfx## 228 , sfx), PORT_1(229 , fn, pfx## 229 , sfx), \230 , fn, pfx## 23 , sfx), \240 , fn, pfx## 24 , sfx), \250 , fn, pfx## 250 , sfx), \/* Port256 - Port283 */ \ 256 , fn, pfx## 256 , sfx), PORT_1(257 , fn, pfx## 257 , sfx), \258 , fn, pfx## 258 , sfx), PORT_1(259 , fn, pfx## 259 , sfx), \260 , fn, pfx## 26 , sfx), \270 , fn, pfx## 27 , sfx), \280 , fn, pfx## 280 , sfx), PORT_1(281 , fn, pfx## 281 , sfx), \282 , fn, pfx## 282 , sfx), PORT_1(283 , fn, pfx## 283 , sfx), \/* Port288 - Port308 */ \ 288 , fn, pfx## 288 , sfx), PORT_1(289 , fn, pfx## 289 , sfx), \290 , fn, pfx## 29 , sfx), \300 , fn, pfx## 300 , sfx), PORT_1(301 , fn, pfx## 301 , sfx), \302 , fn, pfx## 302 , sfx), PORT_1(303 , fn, pfx## 303 , sfx), \304 , fn, pfx## 304 , sfx), PORT_1(305 , fn, pfx## 305 , sfx), \306 , fn, pfx## 306 , sfx), PORT_1(307 , fn, pfx## 307 , sfx), \308 , fn, pfx## 308 , sfx), \/* Port320 - Port329 */ \ 320 , fn, pfx## 32 , sfx)enum {0 ,/* PORT0_DATA -> PORT329_DATA */ /* PORT0_IN -> PORT329_IN */ /* PORT0_OUT -> PORT329_OUT */ /* PORT0_FN_IN -> PORT329_FN_IN */ /* PORT0_FN_OUT -> PORT329_FN_OUT */ /* PORT0_FN0 -> PORT329_FN0 */ /* PORT0_FN1 -> PORT329_FN1 */ /* PORT0_FN2 -> PORT329_FN2 */ /* PORT0_FN3 -> PORT329_FN3 */ /* PORT0_FN4 -> PORT329_FN4 */ /* PORT0_FN5 -> PORT329_FN5 */ /* PORT0_FN6 -> PORT329_FN6 */ /* PORT0_FN7 -> PORT329_FN7 */ #define F1(a) a## _MARK#define F2(a) a## _MARK#define F3(a) a## _MARK#define F4(a) a## _MARK#define F5(a) a## _MARK#define F6(a) a## _MARK#define F7(a) a## _MARK#define IRQ(a) IRQ## a## _MARK0 ), /* Port0 */ 1 ),2 ),3 ),4 ),5 ),6 ),7 ),8 ),9 ),10 ), /* Port10 */ 11 ),12 ),13 ),14 ),15 ),/* Port20 */ /* Port30 */ /* Port32 */ /* Port40 */ /* Port64 */ 40 ),/* Port70 */ /* Port80 */ 19 ), IRQ(18 ), /* Port85 */ /* Port96 */ /* Port100 */ 41 ), F1(KEYIN7), IRQ(42 ),43 ), F2(KEYOUT6), IRQ(44 ), /* Port110 */ 45 ),46 ),47 ),48 ),49 ),/* Port120 */ /* Port130 */ 20 ), /* Port160 */ 21 ), IRQ(22 ), IRQ(23 ),/* Port170 */ 24 ), IRQ(25 ), IRQ(26 ), IRQ(27 ),31 ), /* Port192 */ 32 ),33 ),34 ),35 ),36 ),37 ),38 ),39 ), /* Port200 */ /* Port210 */ /* Port220 */ /* Port230 */ /* Port240 */ /* Port250 */ /* Port260 */ /* Port270 */ /* Port280 */ 51 ), /* Port290 */ 52 ),/* Port300 */ 50 ), F1(SDHID0_0), F3(STMDATA0_1),16 ), /* Port320 */ 17 ), IRQ(28 ), IRQ(29 ), IRQ(30 ), IRQ(53 ), IRQ(54 ),55 ), IRQ(56 ), IRQ(57 ),static const u16 pinmux_data[] = {/* specify valid pin states for each pin in GPIO mode */ /* Port0 */ /* Port1 */ /* Port2 */ /* Port3 */ /* Port4 */ /* Port5 */ /* Port6 */ /* Port7 */ /* Port8 */ /* Port9 */ /* Port10 */ /* Port11 */ /* Port12 */ /* Port13 */ /* Port14 */ /* Port15 */ /* Port16 */ /* Port17 */ /* Port18 */ /* Port19 */ /* Port20 */ /* Port21 */ /* Port22 */ /* Port23 */ /* Port24 */ /* Port25 */ /* Port26 */ /* Port27 */ /* Port28 */ /* Port29 */ /* Port30 */ /* Port32 */ /* Port33 */ /* Port34 */ /* Port35 */ /* Port36 */ /* Port37 */ /* Port38 */ /* Port39 */ /* Port40 */ /* Port64 */ /* Port65 */ /* Port66 */ /* Port67 */ /* Port68 */ /* Port69 */ /* Port70 */ /* Port71 */ /* Port72 */ /* Port73 */ /* Port74 - Port85 */ /* Port96 - Port101 */ /* Port102 */ /* Port103 */ /* Port104 - Port108 */ /* Port109 */ /* Port110 */ /* Port111 */ /* Port112 */ /* Port113 */ /* Port114 */ /* Port115 */ /* Port116 */ /* Port117 */ /* Port118 */ /* Port119 */ /* Port120 */ /* Port121 */ /* Port122 */ /* Port123 */ /* Port124 */ /* Port125 */ /* Port126 */ /* Port128 */ /* Port129 */ /* Port130 */ /* Port131 */ /* Port132 */ /* Port133 */ /* Port134 */ /* Port160 - Port178 */ /* Port192 - Port200 FN1 */ /* Port192 - Port200 FN2 */ /* Port192 - Port200 IRQ */ /* Port201 */ /* Port202 */ /* Port203 */ /* Port204 */ /* Port205 */ /* Port206 */ /* Port207 - Port212 FN1 */ /* Port207 - Port212 FN5 */ /* Port213 - Port222 FN1 */ /* Port213 - Port222 FN2 */ /* Port213 - Port222 FN5 */ /* Port224 */ /* Port225 */ /* Port226 */ /* Port227 */ /* Port228 */ /* Port229 */ /* Port230 */ /* Port231 */ /* Port232 */ /* Port233 */ /* Port234 */ /* Port235 */ /* Port236 */ /* Port237 */ /* Port238 */ /* Port239 */ /* Port240 */ /* Port241 */ /* Port242 */ /* Port243 */ /* Port244 */ /* Port245 */ /* Port246 - Port250 FN1 */ /* Port256 - Port258 */ /* Port259 */ /* Port260 */ /* Port261 */ /* Port262 */ /* Port263 - Port266 FN1 */ /* Port263 - Port266 FN4 */ /* Port267 */ /* Port268 */ /* Port269 */ /* Port270 - Port273 FN1 */ /* Port270 - Port273 FN3 */ /* Port274 */ /* Port275 - Port280 */ /* Port281 */ /* Port282 */ /* Port283 */ /* Port289 */ /* Port290 */ /* Port291 - Port294 FN1 */ /* Port291 - Port294 FN3 */ /* Port295 */ /* Port296 */ /* Port297 - Port300 FN1 */ /* Port297 - Port300 FN2 */ /* Port297 - Port300 FN3 */ /* Port297 - Port300 FN4 */ /* Port301 */ /* Port302 - Port306 FN1 */ /* Port302 - Port306 FN3 */ /* Port307 */ /* Port308 */ /* Port320 - Port329 */ #define __O (SH_PFC_PIN_CFG_OUTPUT)#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)#define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN)#define R8A73A4_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)#define R8A73A4_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)static const struct sh_pfc_pin pinmux_pins[] = {0 ), R8A73A4_PIN_IO_PU_PD(1 ),2 ), R8A73A4_PIN_IO_PU_PD(3 ),4 ), R8A73A4_PIN_IO_PU_PD(5 ),6 ), R8A73A4_PIN_IO_PU_PD(7 ),8 ), R8A73A4_PIN_IO_PU_PD(9 ),10 ), R8A73A4_PIN_IO_PU_PD(11 ),12 ), R8A73A4_PIN_IO_PU_PD(13 ),14 ), R8A73A4_PIN_IO_PU_PD(15 ),16 ), R8A73A4_PIN_IO_PU_PD(17 ),18 ), R8A73A4_PIN_IO_PU_PD(19 ),20 ), R8A73A4_PIN_IO_PU_PD(21 ),22 ), R8A73A4_PIN_IO_PU_PD(23 ),24 ), R8A73A4_PIN_IO_PU_PD(25 ),26 ), R8A73A4_PIN_IO_PU_PD(27 ),28 ), R8A73A4_PIN_IO_PU_PD(29 ),30 ),32 ), R8A73A4_PIN_IO_PU_PD(33 ),34 ), R8A73A4_PIN_IO_PU_PD(35 ),36 ), R8A73A4_PIN_IO_PU_PD(37 ),38 ), R8A73A4_PIN_IO_PU_PD(39 ),40 ),64 ), R8A73A4_PIN_IO_PU_PD(65 ),66 ), R8A73A4_PIN_IO_PU_PD(67 ),68 ), R8A73A4_PIN_IO_PU_PD(69 ),70 ), R8A73A4_PIN_IO_PU_PD(71 ),72 ), R8A73A4_PIN_IO_PU_PD(73 ),74 ), R8A73A4_PIN_IO_PU_PD(75 ),76 ), R8A73A4_PIN_IO_PU_PD(77 ),78 ), R8A73A4_PIN_IO_PU_PD(79 ),80 ), R8A73A4_PIN_IO_PU_PD(81 ),82 ), R8A73A4_PIN_IO_PU_PD(83 ),84 ), R8A73A4_PIN_IO_PU_PD(85 ),96 ), R8A73A4_PIN_IO_PU_PD(97 ),98 ), R8A73A4_PIN_IO_PU_PD(99 ),100 ), R8A73A4_PIN_IO_PU_PD(101 ),102 ), R8A73A4_PIN_IO_PU_PD(103 ),104 ), R8A73A4_PIN_IO_PU_PD(105 ),106 ), R8A73A4_PIN_IO_PU_PD(107 ),108 ), R8A73A4_PIN_IO_PU_PD(109 ),110 ), R8A73A4_PIN_IO_PU_PD(111 ),112 ), R8A73A4_PIN_IO_PU_PD(113 ),114 ), R8A73A4_PIN_IO_PU_PD(115 ),116 ), R8A73A4_PIN_IO_PU_PD(117 ),118 ), R8A73A4_PIN_IO_PU_PD(119 ),120 ), R8A73A4_PIN_IO_PU_PD(121 ),122 ), R8A73A4_PIN_IO_PU_PD(123 ),124 ), R8A73A4_PIN_IO_PU_PD(125 ),126 ),128 ), R8A73A4_PIN_IO_PU_PD(129 ),130 ), R8A73A4_PIN_IO_PU_PD(131 ),132 ), R8A73A4_PIN_IO_PU_PD(133 ),134 ),160 ), R8A73A4_PIN_IO_PU_PD(161 ),162 ), R8A73A4_PIN_IO_PU_PD(163 ),164 ), R8A73A4_PIN_IO_PU_PD(165 ),166 ), R8A73A4_PIN_IO_PU_PD(167 ),168 ), R8A73A4_PIN_IO_PU_PD(169 ),170 ), R8A73A4_PIN_IO_PU_PD(171 ),172 ), R8A73A4_PIN_IO_PU_PD(173 ),174 ), R8A73A4_PIN_IO_PU_PD(175 ),176 ), R8A73A4_PIN_IO_PU_PD(177 ),178 ),192 ), R8A73A4_PIN_IO_PU_PD(193 ),194 ), R8A73A4_PIN_IO_PU_PD(195 ),196 ), R8A73A4_PIN_IO_PU_PD(197 ),198 ), R8A73A4_PIN_IO_PU_PD(199 ),200 ), R8A73A4_PIN_IO_PU_PD(201 ),202 ), R8A73A4_PIN_IO_PU_PD(203 ),204 ), R8A73A4_PIN_IO_PU_PD(205 ),206 ), R8A73A4_PIN_IO_PU_PD(207 ),208 ), R8A73A4_PIN_IO_PU_PD(209 ),210 ), R8A73A4_PIN_IO_PU_PD(211 ),212 ), R8A73A4_PIN_IO_PU_PD(213 ),214 ), R8A73A4_PIN_IO_PU_PD(215 ),216 ), R8A73A4_PIN_IO_PU_PD(217 ),218 ), R8A73A4_PIN_IO_PU_PD(219 ),220 ), R8A73A4_PIN_IO_PU_PD(221 ),222 ),224 ), R8A73A4_PIN_IO_PU_PD(225 ),226 ), R8A73A4_PIN_IO_PU_PD(227 ),228 ), R8A73A4_PIN_IO_PU_PD(229 ),230 ), R8A73A4_PIN_IO_PU_PD(231 ),232 ), R8A73A4_PIN_IO_PU_PD(233 ),234 ), R8A73A4_PIN_IO_PU_PD(235 ),236 ), R8A73A4_PIN_IO_PU_PD(237 ),238 ), R8A73A4_PIN_IO_PU_PD(239 ),240 ), R8A73A4_PIN_IO_PU_PD(241 ),242 ), R8A73A4_PIN_IO_PU_PD(243 ),244 ), R8A73A4_PIN_IO_PU_PD(245 ),246 ), R8A73A4_PIN_IO_PU_PD(247 ),248 ), R8A73A4_PIN_IO_PU_PD(249 ),250 ),256 ), R8A73A4_PIN_IO_PU_PD(257 ),258 ), R8A73A4_PIN_IO_PU_PD(259 ),260 ), R8A73A4_PIN_IO_PU_PD(261 ),262 ), R8A73A4_PIN_IO_PU_PD(263 ),264 ), R8A73A4_PIN_IO_PU_PD(265 ),266 ), R8A73A4_PIN_IO_PU_PD(267 ),268 ), R8A73A4_PIN_IO_PU_PD(269 ),270 ), R8A73A4_PIN_IO_PU_PD(271 ),272 ), R8A73A4_PIN_IO_PU_PD(273 ),274 ), R8A73A4_PIN_IO_PU_PD(275 ),276 ), R8A73A4_PIN_IO_PU_PD(277 ),278 ), R8A73A4_PIN_IO_PU_PD(279 ),280 ), R8A73A4_PIN_IO_PU_PD(281 ),282 ), R8A73A4_PIN_IO_PU_PD(283 ),288 ), R8A73A4_PIN_IO_PU_PD(289 ),290 ), R8A73A4_PIN_IO_PU_PD(291 ),292 ), R8A73A4_PIN_IO_PU_PD(293 ),294 ), R8A73A4_PIN_IO_PU_PD(295 ),296 ), R8A73A4_PIN_IO_PU_PD(297 ),298 ), R8A73A4_PIN_IO_PU_PD(299 ),300 ), R8A73A4_PIN_IO_PU_PD(301 ),302 ), R8A73A4_PIN_IO_PU_PD(303 ),304 ), R8A73A4_PIN_IO_PU_PD(305 ),306 ), R8A73A4_PIN_IO_PU_PD(307 ),308 ),320 ), R8A73A4_PIN_IO_PU_PD(321 ),322 ), R8A73A4_PIN_IO_PU_PD(323 ),324 ), R8A73A4_PIN_IO_PU_PD(325 ),326 ), R8A73A4_PIN_IO_PU_PD(327 ),328 ), R8A73A4_PIN_IO_PU_PD(329 ),/* - IRQC ------------------------------------------------------------------- */ #define IRQC_PINS_MUX(pin, irq_mark) \static const unsigned int irqc_irq## irq_mark## _pins[] = { \static const unsigned int irqc_irq## irq_mark## _mux[] = { \## irq_mark## _MARK, \0 , 0 );1 , 1 );2 , 2 );3 , 3 );4 , 4 );5 , 5 );6 , 6 );7 , 7 );8 , 8 );9 , 9 );10 , 10 );11 , 11 );12 , 12 );13 , 13 );14 , 14 );15 , 15 );66 , 40 );84 , 19 );85 , 18 );102 , 41 );103 , 42 );109 , 43 );110 , 44 );111 , 45 );112 , 46 );113 , 47 );114 , 48 );115 , 49 );160 , 20 );161 , 21 );162 , 22 );163 , 23 );175 , 24 );176 , 25 );177 , 26 );178 , 27 );192 , 31 );193 , 32 );194 , 33 );195 , 34 );196 , 35 );197 , 36 );198 , 37 );199 , 38 );200 , 39 );290 , 51 );296 , 52 );301 , 50 );320 , 16 );321 , 17 );322 , 28 );323 , 29 );324 , 30 );325 , 53 );326 , 54 );327 , 55 );328 , 56 );329 , 57 );/* - MMCIF0 ----------------------------------------------------------------- */ static const unsigned int mmc0_data_pins[] = {/* D[0:7] */ 164 , 165 , 166 , 167 , 168 , 169 , 170 , 171 ,static const unsigned int mmc0_data_mux[] = {static const unsigned int mmc0_ctrl_pins[] = {/* CMD, CLK */ 172 , 173 ,static const unsigned int mmc0_ctrl_mux[] = {/* - MMCIF1 ----------------------------------------------------------------- */ static const unsigned int mmc1_data_pins[] = {/* D[0:7] */ 199 , 198 , 197 , 196 , 195 , 194 , 193 , 192 ,static const unsigned int mmc1_data_mux[] = {static const unsigned int mmc1_ctrl_pins[] = {/* CMD, CLK */ 200 , 203 ,static const unsigned int mmc1_ctrl_mux[] = {/* - SCIFA0 ----------------------------------------------------------------- */ static const unsigned int scifa0_data_pins[] = {/* SCIFA0_RXD, SCIFA0_TXD */ 117 , 116 ,static const unsigned int scifa0_data_mux[] = {static const unsigned int scifa0_clk_pins[] = {/* SCIFA0_SCK */ 34 ,static const unsigned int scifa0_clk_mux[] = {static const unsigned int scifa0_ctrl_pins[] = {/* SCIFA0_RTS, SCIFA0_CTS */ 32 , 33 ,static const unsigned int scifa0_ctrl_mux[] = {/* - SCIFA1 ----------------------------------------------------------------- */ static const unsigned int scifa1_data_pins[] = {/* SCIFA1_RXD, SCIFA1_TXD */ 119 , 118 ,static const unsigned int scifa1_data_mux[] = {static const unsigned int scifa1_clk_pins[] = {/* SCIFA1_SCK */ 37 ,static const unsigned int scifa1_clk_mux[] = {static const unsigned int scifa1_ctrl_pins[] = {/* SCIFA1_RTS, SCIFA1_CTS */ 35 , 36 ,static const unsigned int scifa1_ctrl_mux[] = {/* - SCIFB0 ----------------------------------------------------------------- */ static const unsigned int scifb0_data_pins[] = {/* SCIFB0_RXD, SCIFB0_TXD */ 123 , 122 ,static const unsigned int scifb0_data_mux[] = {static const unsigned int scifb0_clk_pins[] = {/* SCIFB0_SCK */ 40 ,static const unsigned int scifb0_clk_mux[] = {static const unsigned int scifb0_ctrl_pins[] = {/* SCIFB0_RTS, SCIFB0_CTS */ 38 , 39 ,static const unsigned int scifb0_ctrl_mux[] = {/* - SCIFB1 ----------------------------------------------------------------- */ static const unsigned int scifb1_data_pins[] = {/* SCIFB1_RXD, SCIFB1_TXD */ 27 , 26 ,static const unsigned int scifb1_data_mux[] = {static const unsigned int scifb1_clk_pins[] = {/* SCIFB1_SCK */ 28 ,static const unsigned int scifb1_clk_mux[] = {static const unsigned int scifb1_ctrl_pins[] = {/* SCIFB1_RTS, SCIFB1_CTS */ 24 , 25 ,static const unsigned int scifb1_ctrl_mux[] = {static const unsigned int scifb1_data_b_pins[] = {/* SCIFB1_RXD, SCIFB1_TXD */ 72 , 67 ,static const unsigned int scifb1_data_b_mux[] = {static const unsigned int scifb1_clk_b_pins[] = {/* SCIFB1_SCK */ 261 ,static const unsigned int scifb1_clk_b_mux[] = {static const unsigned int scifb1_ctrl_b_pins[] = {/* SCIFB1_RTS, SCIFB1_CTS */ 70 , 71 ,static const unsigned int scifb1_ctrl_b_mux[] = {/* - SCIFB2 ----------------------------------------------------------------- */ static const unsigned int scifb2_data_pins[] = {/* SCIFB2_RXD, SCIFB2_TXD */ 69 , 68 ,static const unsigned int scifb2_data_mux[] = {static const unsigned int scifb2_clk_pins[] = {/* SCIFB2_SCK */ 262 ,static const unsigned int scifb2_clk_mux[] = {static const unsigned int scifb2_ctrl_pins[] = {/* SCIFB2_RTS, SCIFB2_CTS */ 73 , 66 ,static const unsigned int scifb2_ctrl_mux[] = {static const unsigned int scifb2_data_b_pins[] = {/* SCIFB2_RXD, SCIFB2_TXD */ 297 , 295 ,static const unsigned int scifb2_data_b_mux[] = {static const unsigned int scifb2_clk_b_pins[] = {/* SCIFB2_SCK */ 299 ,static const unsigned int scifb2_clk_b_mux[] = {static const unsigned int scifb2_ctrl_b_pins[] = {/* SCIFB2_RTS, SCIFB2_CTS */ 300 , 298 ,static const unsigned int scifb2_ctrl_b_mux[] = {/* - SCIFB3 ----------------------------------------------------------------- */ static const unsigned int scifb3_data_pins[] = {/* SCIFB3_RXD, SCIFB3_TXD */ 22 , 21 ,static const unsigned int scifb3_data_mux[] = {static const unsigned int scifb3_clk_pins[] = {/* SCIFB3_SCK */ 23 ,static const unsigned int scifb3_clk_mux[] = {static const unsigned int scifb3_ctrl_pins[] = {/* SCIFB3_RTS, SCIFB3_CTS */ 19 , 20 ,static const unsigned int scifb3_ctrl_mux[] = {static const unsigned int scifb3_data_b_pins[] = {/* SCIFB3_RXD, SCIFB3_TXD */ 120 , 121 ,static const unsigned int scifb3_data_b_mux[] = {static const unsigned int scifb3_clk_b_pins[] = {/* SCIFB3_SCK */ 40 ,static const unsigned int scifb3_clk_b_mux[] = {static const unsigned int scifb3_ctrl_b_pins[] = {/* SCIFB3_RTS, SCIFB3_CTS */ 38 , 39 ,static const unsigned int scifb3_ctrl_b_mux[] = {/* - SDHI0 ------------------------------------------------------------------ */ static const unsigned int sdhi0_data_pins[] = {/* D[0:3] */ 302 , 303 , 304 , 305 ,static const unsigned int sdhi0_data_mux[] = {static const unsigned int sdhi0_ctrl_pins[] = {/* CLK, CMD */ 308 , 306 ,static const unsigned int sdhi0_ctrl_mux[] = {static const unsigned int sdhi0_cd_pins[] = {/* CD */ 301 ,static const unsigned int sdhi0_cd_mux[] = {static const unsigned int sdhi0_wp_pins[] = {/* WP */ 307 ,static const unsigned int sdhi0_wp_mux[] = {/* - SDHI1 ------------------------------------------------------------------ */ static const unsigned int sdhi1_data_pins[] = {/* D[0:3] */ 289 , 290 , 291 , 292 ,static const unsigned int sdhi1_data_mux[] = {static const unsigned int sdhi1_ctrl_pins[] = {/* CLK, CMD */ 293 , 294 ,static const unsigned int sdhi1_ctrl_mux[] = {/* - SDHI2 ------------------------------------------------------------------ */ static const unsigned int sdhi2_data_pins[] = {/* D[0:3] */ 295 , 296 , 297 , 298 ,static const unsigned int sdhi2_data_mux[] = {static const unsigned int sdhi2_ctrl_pins[] = {/* CLK, CMD */ 299 , 300 ,static const unsigned int sdhi2_ctrl_mux[] = {static const struct sh_pfc_pin_group pinmux_groups[] = {1 ),4 ),8 ),1 ),4 ),8 ),1 ),4 ),1 ),4 ),1 ),4 ),static const char * const irqc_groups[] = {"irqc_irq0" ,"irqc_irq1" ,"irqc_irq2" ,"irqc_irq3" ,"irqc_irq4" ,"irqc_irq5" ,"irqc_irq6" ,"irqc_irq7" ,"irqc_irq8" ,"irqc_irq9" ,"irqc_irq10" ,"irqc_irq11" ,"irqc_irq12" ,"irqc_irq13" ,"irqc_irq14" ,"irqc_irq15" ,"irqc_irq16" ,"irqc_irq17" ,"irqc_irq18" ,"irqc_irq19" ,"irqc_irq20" ,"irqc_irq21" ,"irqc_irq22" ,"irqc_irq23" ,"irqc_irq24" ,"irqc_irq25" ,"irqc_irq26" ,"irqc_irq27" ,"irqc_irq28" ,"irqc_irq29" ,"irqc_irq30" ,"irqc_irq31" ,"irqc_irq32" ,"irqc_irq33" ,"irqc_irq34" ,"irqc_irq35" ,"irqc_irq36" ,"irqc_irq37" ,"irqc_irq38" ,"irqc_irq39" ,"irqc_irq40" ,"irqc_irq41" ,"irqc_irq42" ,"irqc_irq43" ,"irqc_irq44" ,"irqc_irq45" ,"irqc_irq46" ,"irqc_irq47" ,"irqc_irq48" ,"irqc_irq49" ,"irqc_irq50" ,"irqc_irq51" ,"irqc_irq52" ,"irqc_irq53" ,"irqc_irq54" ,"irqc_irq55" ,"irqc_irq56" ,"irqc_irq57" ,static const char * const mmc0_groups[] = {"mmc0_data1" ,"mmc0_data4" ,"mmc0_data8" ,"mmc0_ctrl" ,static const char * const mmc1_groups[] = {"mmc1_data1" ,"mmc1_data4" ,"mmc1_data8" ,"mmc1_ctrl" ,static const char * const scifa0_groups[] = {"scifa0_data" ,"scifa0_clk" ,"scifa0_ctrl" ,static const char * const scifa1_groups[] = {"scifa1_data" ,"scifa1_clk" ,"scifa1_ctrl" ,static const char * const scifb0_groups[] = {"scifb0_data" ,"scifb0_clk" ,"scifb0_ctrl" ,static const char * const scifb1_groups[] = {"scifb1_data" ,"scifb1_clk" ,"scifb1_ctrl" ,"scifb1_data_b" ,"scifb1_clk_b" ,"scifb1_ctrl_b" ,static const char * const scifb2_groups[] = {"scifb2_data" ,"scifb2_clk" ,"scifb2_ctrl" ,"scifb2_data_b" ,"scifb2_clk_b" ,"scifb2_ctrl_b" ,static const char * const scifb3_groups[] = {"scifb3_data" ,"scifb3_clk" ,"scifb3_ctrl" ,"scifb3_data_b" ,"scifb3_clk_b" ,"scifb3_ctrl_b" ,static const char * const sdhi0_groups[] = {"sdhi0_data1" ,"sdhi0_data4" ,"sdhi0_ctrl" ,"sdhi0_cd" ,"sdhi0_wp" ,static const char * const sdhi1_groups[] = {"sdhi1_data1" ,"sdhi1_data4" ,"sdhi1_ctrl" ,static const char * const sdhi2_groups[] = {"sdhi2_data1" ,"sdhi2_data4" ,"sdhi2_ctrl" ,static const struct sh_pfc_function pinmux_functions[] = {static const struct pinmux_cfg_reg pinmux_config_regs[] = {0 , 0 xe6050000),1 , 0 xe6050001),2 , 0 xe6050002),3 , 0 xe6050003),4 , 0 xe6050004),5 , 0 xe6050005),6 , 0 xe6050006),7 , 0 xe6050007),8 , 0 xe6050008),9 , 0 xe6050009),10 , 0 xe605000A),11 , 0 xe605000B),12 , 0 xe605000C),13 , 0 xe605000D),14 , 0 xe605000E),15 , 0 xe605000F),16 , 0 xe6050010),17 , 0 xe6050011),18 , 0 xe6050012),19 , 0 xe6050013),20 , 0 xe6050014),21 , 0 xe6050015),22 , 0 xe6050016),23 , 0 xe6050017),24 , 0 xe6050018),25 , 0 xe6050019),26 , 0 xe605001A),27 , 0 xe605001B),28 , 0 xe605001C),29 , 0 xe605001D),30 , 0 xe605001E),32 , 0 xe6051020),33 , 0 xe6051021),34 , 0 xe6051022),35 , 0 xe6051023),36 , 0 xe6051024),37 , 0 xe6051025),38 , 0 xe6051026),39 , 0 xe6051027),40 , 0 xe6051028),64 , 0 xe6050040),65 , 0 xe6050041),66 , 0 xe6050042),67 , 0 xe6050043),68 , 0 xe6050044),69 , 0 xe6050045),70 , 0 xe6050046),71 , 0 xe6050047),72 , 0 xe6050048),73 , 0 xe6050049),74 , 0 xe605004A),75 , 0 xe605004B),76 , 0 xe605004C),77 , 0 xe605004D),78 , 0 xe605004E),79 , 0 xe605004F),80 , 0 xe6050050),81 , 0 xe6050051),82 , 0 xe6050052),83 , 0 xe6050053),84 , 0 xe6050054),85 , 0 xe6050055),96 , 0 xe6051060),97 , 0 xe6051061),98 , 0 xe6051062),99 , 0 xe6051063),100 , 0 xe6051064),101 , 0 xe6051065),102 , 0 xe6051066),103 , 0 xe6051067),104 , 0 xe6051068),105 , 0 xe6051069),106 , 0 xe605106A),107 , 0 xe605106B),108 , 0 xe605106C),109 , 0 xe605106D),110 , 0 xe605106E),111 , 0 xe605106F),112 , 0 xe6051070),113 , 0 xe6051071),114 , 0 xe6051072),115 , 0 xe6051073),116 , 0 xe6051074),117 , 0 xe6051075),118 , 0 xe6051076),119 , 0 xe6051077),120 , 0 xe6051078),121 , 0 xe6051079),122 , 0 xe605107A),123 , 0 xe605107B),124 , 0 xe605107C),125 , 0 xe605107D),126 , 0 xe605107E),128 , 0 xe6051080),129 , 0 xe6051081),130 , 0 xe6051082),131 , 0 xe6051083),132 , 0 xe6051084),133 , 0 xe6051085),134 , 0 xe6051086),160 , 0 xe60520A0),161 , 0 xe60520A1),162 , 0 xe60520A2),163 , 0 xe60520A3),164 , 0 xe60520A4),165 , 0 xe60520A5),166 , 0 xe60520A6),167 , 0 xe60520A7),168 , 0 xe60520A8),169 , 0 xe60520A9),170 , 0 xe60520AA),171 , 0 xe60520AB),172 , 0 xe60520AC),173 , 0 xe60520AD),174 , 0 xe60520AE),175 , 0 xe60520AF),176 , 0 xe60520B0),177 , 0 xe60520B1),178 , 0 xe60520B2),192 , 0 xe60520C0),193 , 0 xe60520C1),194 , 0 xe60520C2),195 , 0 xe60520C3),196 , 0 xe60520C4),197 , 0 xe60520C5),198 , 0 xe60520C6),199 , 0 xe60520C7),200 , 0 xe60520C8),201 , 0 xe60520C9),202 , 0 xe60520CA),203 , 0 xe60520CB),204 , 0 xe60520CC),205 , 0 xe60520CD),206 , 0 xe60520CE),207 , 0 xe60520CF),208 , 0 xe60520D0),209 , 0 xe60520D1),210 , 0 xe60520D2),211 , 0 xe60520D3),212 , 0 xe60520D4),213 , 0 xe60520D5),214 , 0 xe60520D6),215 , 0 xe60520D7),216 , 0 xe60520D8),217 , 0 xe60520D9),218 , 0 xe60520DA),219 , 0 xe60520DB),220 , 0 xe60520DC),221 , 0 xe60520DD),222 , 0 xe60520DE),224 , 0 xe60520E0),225 , 0 xe60520E1),226 , 0 xe60520E2),227 , 0 xe60520E3),228 , 0 xe60520E4),229 , 0 xe60520E5),230 , 0 xe60520e6),231 , 0 xe60520E7),232 , 0 xe60520E8),233 , 0 xe60520E9),234 , 0 xe60520EA),235 , 0 xe60520EB),236 , 0 xe60520EC),237 , 0 xe60520ED),238 , 0 xe60520EE),239 , 0 xe60520EF),240 , 0 xe60520F0),241 , 0 xe60520F1),242 , 0 xe60520F2),243 , 0 xe60520F3),244 , 0 xe60520F4),245 , 0 xe60520F5),246 , 0 xe60520F6),247 , 0 xe60520F7),248 , 0 xe60520F8),249 , 0 xe60520F9),250 , 0 xe60520FA),256 , 0 xe6052100),257 , 0 xe6052101),258 , 0 xe6052102),259 , 0 xe6052103),260 , 0 xe6052104),261 , 0 xe6052105),262 , 0 xe6052106),263 , 0 xe6052107),264 , 0 xe6052108),265 , 0 xe6052109),266 , 0 xe605210A),267 , 0 xe605210B),268 , 0 xe605210C),269 , 0 xe605210D),270 , 0 xe605210E),271 , 0 xe605210F),272 , 0 xe6052110),273 , 0 xe6052111),274 , 0 xe6052112),275 , 0 xe6052113),276 , 0 xe6052114),277 , 0 xe6052115),278 , 0 xe6052116),279 , 0 xe6052117),280 , 0 xe6052118),281 , 0 xe6052119),282 , 0 xe605211A),283 , 0 xe605211B),288 , 0 xe6053120),289 , 0 xe6053121),290 , 0 xe6053122),291 , 0 xe6053123),292 , 0 xe6053124),293 , 0 xe6053125),294 , 0 xe6053126),295 , 0 xe6053127),296 , 0 xe6053128),297 , 0 xe6053129),298 , 0 xe605312A),299 , 0 xe605312B),300 , 0 xe605312C),301 , 0 xe605312D),302 , 0 xe605312E),303 , 0 xe605312F),304 , 0 xe6053130),305 , 0 xe6053131),306 , 0 xe6053132),307 , 0 xe6053133),308 , 0 xe6053134),320 , 0 xe6053140),321 , 0 xe6053141),322 , 0 xe6053142),323 , 0 xe6053143),324 , 0 xe6053144),325 , 0 xe6053145),326 , 0 xe6053146),327 , 0 xe6053147),328 , 0 xe6053148),329 , 0 xe6053149),"MSEL1CR" , 0 xe605800c, 32 , 1 , GROUP(0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,"MSEL3CR" , 0 xe6058020, 32 ,1 , -2 , 1 , 1 , 1 , -2 , 1 , 1 , 1 , 1 , 1 , 1 ,1 , 1 , 1 , -2 , 1 , 1 , 1 , 1 , -2 , 1 , -2 , 1 ,1 , 1 , 1 ),/* RESERVED [2] */ /* RESERVED [2] */ /* RESERVED [2] */ /* RESERVED [2] */ /* RESERVED [2] */ /* RESERVED [1] */ "MSEL4CR" , 0 xe6058024, 32 , 1 , GROUP(0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,"MSEL5CR" , 0 xe6058028, 32 , 1 , GROUP(0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,0 , 0 ,"MSEL8CR" , 0 xe6058034, 32 ,15 , 1 , -14 , 1 , 1 ),/* RESERVED [15] */ /* RESERVED [14] */ /* sentinel */ } static const struct pinmux_data_reg pinmux_data_regs[] = {"PORTL031_000DR" , 0 xe6054000, 32 , GROUP(0 , PORT30_DATA, PORT29_DATA, PORT28_DATA,"PORTD063_032DR" , 0 xe6055000, 32 , GROUP(0 , 0 , 0 , 0 ,0 , 0 , 0 , 0 ,0 , 0 , 0 , 0 ,0 , 0 , 0 , 0 ,0 , 0 , 0 , 0 ,0 , 0 , 0 , PORT40_DATA,"PORTL095_064DR" , 0 xe6054004, 32 , GROUP(0 , 0 , 0 , 0 ,0 , 0 , 0 , 0 ,0 , 0 , PORT85_DATA, PORT84_DATA,"PORTD127_096DR" , 0 xe6055004, 32 , GROUP(0 , PORT126_DATA, PORT125_DATA, PORT124_DATA,"PORTD159_128DR" , 0 xe6055008, 32 , GROUP(0 , 0 , 0 , 0 ,0 , 0 , 0 , 0 ,0 , 0 , 0 , 0 ,0 , 0 , 0 , 0 ,0 , 0 , 0 , 0 ,0 , 0 , 0 , 0 ,0 , PORT134_DATA, PORT133_DATA, PORT132_DATA,"PORTR191_160DR" , 0 xe6056000, 32 , GROUP(0 , 0 , 0 , 0 ,0 , 0 , 0 , 0 ,0 , 0 , 0 , 0 ,0 , PORT178_DATA, PORT177_DATA, PORT176_DATA,"PORTR223_192DR" , 0 xe6056004, 32 , GROUP(0 , PORT222_DATA, PORT221_DATA, PORT220_DATA,"PORTR255_224DR" , 0 xe6056008, 32 , GROUP(0 , 0 , 0 , 0 ,0 , PORT250_DATA, PORT249_DATA, PORT248_DATA,"PORTR287_256DR" , 0 xe605600C, 32 , GROUP(0 , 0 , 0 , 0 ,"PORTU319_288DR" , 0 xe6057000, 32 , GROUP(0 , 0 , 0 , 0 ,0 , 0 , 0 , 0 ,0 , 0 , 0 , PORT308_DATA,"PORTU351_320DR" , 0 xe6057004, 32 , GROUP(0 , 0 , 0 , 0 ,0 , 0 , 0 , 0 ,0 , 0 , 0 , 0 ,0 , 0 , 0 , 0 ,0 , 0 , 0 , 0 ,0 , 0 , PORT329_DATA, PORT328_DATA,/* sentinel */ } static const struct pinmux_irq pinmux_irqs[] = {0 ), /* IRQ0 */ 1 ), /* IRQ1 */ 2 ), /* IRQ2 */ 3 ), /* IRQ3 */ 4 ), /* IRQ4 */ 5 ), /* IRQ5 */ 6 ), /* IRQ6 */ 7 ), /* IRQ7 */ 8 ), /* IRQ8 */ 9 ), /* IRQ9 */ 10 ), /* IRQ10 */ 11 ), /* IRQ11 */ 12 ), /* IRQ12 */ 13 ), /* IRQ13 */ 14 ), /* IRQ14 */ 15 ), /* IRQ15 */ 320 ), /* IRQ16 */ 321 ), /* IRQ17 */ 85 ), /* IRQ18 */ 84 ), /* IRQ19 */ 160 ), /* IRQ20 */ 161 ), /* IRQ21 */ 162 ), /* IRQ22 */ 163 ), /* IRQ23 */ 175 ), /* IRQ24 */ 176 ), /* IRQ25 */ 177 ), /* IRQ26 */ 178 ), /* IRQ27 */ 322 ), /* IRQ28 */ 323 ), /* IRQ29 */ 324 ), /* IRQ30 */ 192 ), /* IRQ31 */ 193 ), /* IRQ32 */ 194 ), /* IRQ33 */ 195 ), /* IRQ34 */ 196 ), /* IRQ35 */ 197 ), /* IRQ36 */ 198 ), /* IRQ37 */ 199 ), /* IRQ38 */ 200 ), /* IRQ39 */ 66 ), /* IRQ40 */ 102 ), /* IRQ41 */ 103 ), /* IRQ42 */ 109 ), /* IRQ43 */ 110 ), /* IRQ44 */ 111 ), /* IRQ45 */ 112 ), /* IRQ46 */ 113 ), /* IRQ47 */ 114 ), /* IRQ48 */ 115 ), /* IRQ49 */ 301 ), /* IRQ50 */ 290 ), /* IRQ51 */ 296 ), /* IRQ52 */ 325 ), /* IRQ53 */ 326 ), /* IRQ54 */ 327 ), /* IRQ55 */ 328 ), /* IRQ56 */ 329 ), /* IRQ57 */ static const unsigned int r8a73a4_portcr_offsets[] = {0 x00000000, 0 x00001000, 0 x00000000, 0 x00001000,0 x00001000, 0 x00002000, 0 x00002000, 0 x00002000,0 x00002000, 0 x00003000, 0 x00003000,static int r8a73a4_pin_to_portcr(unsigned int pin)return r8a73a4_portcr_offsets[pin >> 5 ] + pin;static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = {const struct sh_pfc_soc_info r8a73a4_pinmux_info = {"r8a73a4_pfc" ,
Messung V0.5 in Prozent C=93 H=92 G=92
¤ Dauer der Verarbeitung: 0.26 Sekunden
(vorverarbeitet am 2026-06-08)
¤ *© Formatika GbR, Deutschland
