// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Microsemi SoCs pinctrl driver * * Author: <alexandre.belloni@free-electrons.com> * License: Dual MIT/GPL * Copyright (c) 2017 Microsemi Corporation #include <linux/gpio/driver.h>#include <linux/interrupt.h>#include <linux/io.h>#include <linux/mfd/ocelot.h>#include <linux/of.h>#include <linux/platform_device.h>#include <linux/regmap.h>#include <linux/reset.h>#include <linux/slab.h>#include <linux/pinctrl/consumer.h>#include <linux/pinctrl/pinconf-generic.h>#include <linux/pinctrl/pinconf.h>#include <linux/pinctrl/pinctrl.h>#include <linux/pinctrl/pinmux.h>#include "core.h" #include "pinconf.h" #include "pinmux.h" #define ocelot_clrsetbits(addr, clear, set) \enum {/* GPIO standard registers */ #define OCELOT_GPIO_OUT_SET 0 x0#define OCELOT_GPIO_OUT_CLR 0 x4#define OCELOT_GPIO_OUT 0 x8#define OCELOT_GPIO_IN 0 xc#define OCELOT_GPIO_OE 0 x10#define OCELOT_GPIO_INTR 0 x14#define OCELOT_GPIO_INTR_ENA 0 x18#define OCELOT_GPIO_INTR_IDENT 0 x1c#define OCELOT_GPIO_ALT0 0 x20#define OCELOT_GPIO_ALT1 0 x24#define OCELOT_GPIO_SD_MAP 0 x28#define OCELOT_FUNC_PER_PIN 4 enum {static const char *const ocelot_function_names[] = {"can0_a" ,"can0_b" ,"can1" ,"clkmon" ,"none" ,"fan" ,"fc" ,"fc0_a" ,"fc0_b" ,"fc0_c" ,"fc1_a" ,"fc1_b" ,"fc1_c" ,"fc2_a" ,"fc2_b" ,"fc3_a" ,"fc3_b" ,"fc3_c" ,"fc4_a" ,"fc4_b" ,"fc4_c" ,"fc_shrd" ,"fc_shrd0" ,"fc_shrd1" ,"fc_shrd2" ,"fc_shrd3" ,"fc_shrd4" ,"fc_shrd5" ,"fc_shrd6" ,"fc_shrd7" ,"fc_shrd8" ,"fc_shrd9" ,"fc_shrd10" ,"fc_shrd11" ,"fc_shrd12" ,"fc_shrd13" ,"fc_shrd14" ,"fc_shrd15" ,"fc_shrd16" ,"fc_shrd17" ,"fc_shrd18" ,"fc_shrd19" ,"fc_shrd20" ,"fusa" ,"gpio" ,"ib_trig_a" ,"ib_trig_b" ,"ib_trig_c" ,"irq0" ,"irq_in_a" ,"irq_in_b" ,"irq_in_c" ,"irq0_in" ,"irq_out_a" ,"irq_out_b" ,"irq_out_c" ,"irq0_out" ,"irq1" ,"irq1_in" ,"irq1_out" ,"irq3" ,"irq4" ,"ext_irq" ,"miim" ,"miim_a" ,"miim_b" ,"miim_c" ,"miim_slave_a" ,"miim_slave_b" ,"miim_irq" ,"phy_led" ,"pci_wake" ,"pcie_perst" ,"md" ,"ob_trig" ,"ob_trig_a" ,"ob_trig_b" ,"ptp0" ,"ptp1" ,"ptp2" ,"ptp3" ,"ptpsync_0" ,"ptpsync_1" ,"ptpsync_2" ,"ptpsync_3" ,"ptpsync_4" ,"ptpsync_5" ,"ptpsync_6" ,"ptpsync_7" ,"pwm" ,"pwm_a" ,"pwm_b" ,"qspi1" ,"qspi2" ,"reserved" ,"reco_a" ,"reco_b" ,"reco_clk" ,"sd" ,"sfp" ,"sfp_sd" ,"sg0" ,"sg1" ,"sg2" ,"sgpio_a" ,"sgpio_b" ,"si" ,"si2" ,"synce" ,"tacho" ,"tacho_a" ,"tacho_b" ,"twi" ,"twi2" ,"twi3" ,"twi_scl_m" ,"twi_slc_gate" ,"twi_slc_gate_ad" ,"usb_host_a" ,"usb_host_b" ,"usb_host_c" ,"usb_slave_a" ,"usb_slave_b" ,"usb_slave_c" ,"usb_power" ,"usb2phy_rst" ,"usb_over_detect" ,"usb_ulpi" ,"uart" ,"uart2" ,"uart3" ,"pll_stat" ,"emmc" ,"emmc_sd" ,"ref_clk" ,"rcvrd_clk" ,struct ocelot_pmx_func {const char **groups;unsigned int ngroups;struct ocelot_pin_caps {unsigned int pin;unsigned char functions[OCELOT_FUNC_PER_PIN];unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */ struct ocelot_pincfg_data {struct ocelot_pinctrl {struct device *dev;struct pinctrl_dev *pctl;struct gpio_chip gpio_chip;struct regmap *map;struct regmap *pincfg;struct pinctrl_desc *desc;const struct ocelot_pincfg_data *pincfg_data;struct ocelot_pmx_func func[FUNC_MAX];struct workqueue_struct *wq;struct ocelot_match_data {struct pinctrl_desc desc;struct ocelot_pincfg_data pincfg_data;struct ocelot_irq_work {struct work_struct irq_work;struct irq_desc *irq_desc;#define LUTON_P(p, f0, f1) \static struct ocelot_pin_caps luton_pin_## p = { \## f0, FUNC_## f1, FUNC_NONE, \0 , SG0, NONE);1 , SG0, NONE);2 , SG0, NONE);3 , SG0, NONE);4 , TACHO, NONE);5 , TWI, PHY_LED);6 , TWI, PHY_LED);7 , NONE, PHY_LED);8 , EXT_IRQ, PHY_LED);9 , EXT_IRQ, PHY_LED);10 , SFP, PHY_LED);11 , SFP, PHY_LED);12 , SFP, PHY_LED);13 , SFP, PHY_LED);14 , SI, PHY_LED);15 , SI, PHY_LED);16 , SI, PHY_LED);17 , SFP, PHY_LED);18 , SFP, PHY_LED);19 , SFP, PHY_LED);20 , SFP, PHY_LED);21 , SFP, PHY_LED);22 , SFP, PHY_LED);23 , SFP, PHY_LED);24 , SFP, PHY_LED);25 , SFP, PHY_LED);26 , SFP, PHY_LED);27 , SFP, PHY_LED);28 , SFP, PHY_LED);29 , PWM, NONE);30 , UART, NONE);31 , UART, NONE);#define LUTON_PIN(n) { \"GPIO_" #n , \## n \static const struct pinctrl_pin_desc luton_pins[] = {0 ),1 ),2 ),3 ),4 ),5 ),6 ),7 ),8 ),9 ),10 ),11 ),12 ),13 ),14 ),15 ),16 ),17 ),18 ),19 ),20 ),21 ),22 ),23 ),24 ),25 ),26 ),27 ),28 ),29 ),30 ),31 ),#define SERVAL_P(p, f0, f1, f2) \static struct ocelot_pin_caps serval_pin_## p = { \## f0, FUNC_## f1, FUNC_## f2, \0 , SG0, NONE, NONE);1 , SG0, NONE, NONE);2 , SG0, NONE, NONE);3 , SG0, NONE, NONE);4 , TACHO, NONE, NONE);5 , PWM, NONE, NONE);6 , TWI, NONE, NONE);7 , TWI, NONE, NONE);8 , SI, NONE, NONE);9 , SI, MD, NONE);10 , SI, MD, NONE);11 , SFP, MD, TWI_SCL_M);12 , SFP, MD, TWI_SCL_M);13 , SFP, UART2, TWI_SCL_M);14 , SFP, UART2, TWI_SCL_M);15 , SFP, PTP0, TWI_SCL_M);16 , SFP, PTP0, TWI_SCL_M);17 , SFP, PCI_WAKE, TWI_SCL_M);18 , SFP, NONE, TWI_SCL_M);19 , SFP, NONE, TWI_SCL_M);20 , SFP, NONE, TWI_SCL_M);21 , SFP, NONE, TWI_SCL_M);22 , NONE, NONE, NONE);23 , NONE, NONE, NONE);24 , NONE, NONE, NONE);25 , NONE, NONE, NONE);26 , UART, NONE, NONE);27 , UART, NONE, NONE);28 , IRQ0, NONE, NONE);29 , IRQ1, NONE, NONE);30 , PTP0, NONE, NONE);31 , PTP0, NONE, NONE);#define SERVAL_PIN(n) { \"GPIO_" #n , \## n \static const struct pinctrl_pin_desc serval_pins[] = {0 ),1 ),2 ),3 ),4 ),5 ),6 ),7 ),8 ),9 ),10 ),11 ),12 ),13 ),14 ),15 ),16 ),17 ),18 ),19 ),20 ),21 ),22 ),23 ),24 ),25 ),26 ),27 ),28 ),29 ),30 ),31 ),#define OCELOT_P(p, f0, f1, f2) \static struct ocelot_pin_caps ocelot_pin_## p = { \## f0, FUNC_## f1, FUNC_## f2, \0 , SG0, NONE, NONE);1 , SG0, NONE, NONE);2 , SG0, NONE, NONE);3 , SG0, NONE, NONE);4 , IRQ0_IN, IRQ0_OUT, TWI_SCL_M);5 , IRQ1_IN, IRQ1_OUT, PCI_WAKE);6 , UART, TWI_SCL_M, NONE);7 , UART, TWI_SCL_M, NONE);8 , SI, TWI_SCL_M, IRQ0_OUT);9 , SI, TWI_SCL_M, IRQ1_OUT);10 , PTP2, TWI_SCL_M, SFP);11 , PTP3, TWI_SCL_M, SFP);12 , UART2, TWI_SCL_M, SFP);13 , UART2, TWI_SCL_M, SFP);14 , MIIM, TWI_SCL_M, SFP);15 , MIIM, TWI_SCL_M, SFP);16 , TWI, NONE, SI);17 , TWI, TWI_SCL_M, SI);18 , PTP0, TWI_SCL_M, NONE);19 , PTP1, TWI_SCL_M, NONE);20 , RECO_CLK, TACHO, TWI_SCL_M);21 , RECO_CLK, PWM, TWI_SCL_M);#define OCELOT_PIN(n) { \"GPIO_" #n , \## n \static const struct pinctrl_pin_desc ocelot_pins[] = {0 ),1 ),2 ),3 ),4 ),5 ),6 ),7 ),8 ),9 ),10 ),11 ),12 ),13 ),14 ),15 ),16 ),17 ),18 ),19 ),20 ),21 ),#define JAGUAR2_P(p, f0, f1) \static struct ocelot_pin_caps jaguar2_pin_## p = { \## f0, FUNC_## f1, FUNC_NONE \0 , SG0, NONE);1 , SG0, NONE);2 , SG0, NONE);3 , SG0, NONE);4 , SG1, NONE);5 , SG1, NONE);6 , IRQ0_IN, IRQ0_OUT);7 , IRQ1_IN, IRQ1_OUT);8 , PTP0, NONE);9 , PTP1, NONE);10 , UART, NONE);11 , UART, NONE);12 , SG1, NONE);13 , SG1, NONE);14 , TWI, TWI_SCL_M);15 , TWI, NONE);16 , SI, TWI_SCL_M);17 , SI, TWI_SCL_M);18 , SI, TWI_SCL_M);19 , PCI_WAKE, NONE);20 , IRQ0_OUT, TWI_SCL_M);21 , IRQ1_OUT, TWI_SCL_M);22 , TACHO, NONE);23 , PWM, NONE);24 , UART2, NONE);25 , UART2, SI);26 , PTP2, SI);27 , PTP3, SI);28 , TWI2, SI);29 , TWI2, SI);30 , SG2, SI);31 , SG2, SI);32 , SG2, SI);33 , SG2, SI);34 , NONE, TWI_SCL_M);35 , NONE, TWI_SCL_M);36 , NONE, TWI_SCL_M);37 , NONE, TWI_SCL_M);38 , NONE, TWI_SCL_M);39 , NONE, TWI_SCL_M);40 , NONE, TWI_SCL_M);41 , NONE, TWI_SCL_M);42 , NONE, TWI_SCL_M);43 , NONE, TWI_SCL_M);44 , NONE, SFP);45 , NONE, SFP);46 , NONE, SFP);47 , NONE, SFP);48 , SFP, NONE);49 , SFP, SI);50 , SFP, SI);51 , SFP, SI);52 , SFP, NONE);53 , SFP, NONE);54 , SFP, NONE);55 , SFP, NONE);56 , MIIM, SFP);57 , MIIM, SFP);58 , MIIM, SFP);59 , MIIM, SFP);60 , NONE, NONE);61 , NONE, NONE);62 , NONE, NONE);63 , NONE, NONE);#define JAGUAR2_PIN(n) { \"GPIO_" #n , \## n \static const struct pinctrl_pin_desc jaguar2_pins[] = {0 ),1 ),2 ),3 ),4 ),5 ),6 ),7 ),8 ),9 ),10 ),11 ),12 ),13 ),14 ),15 ),16 ),17 ),18 ),19 ),20 ),21 ),22 ),23 ),24 ),25 ),26 ),27 ),28 ),29 ),30 ),31 ),32 ),33 ),34 ),35 ),36 ),37 ),38 ),39 ),40 ),41 ),42 ),43 ),44 ),45 ),46 ),47 ),48 ),49 ),50 ),51 ),52 ),53 ),54 ),55 ),56 ),57 ),58 ),59 ),60 ),61 ),62 ),63 ),#define SERVALT_P(p, f0, f1, f2) \static struct ocelot_pin_caps servalt_pin_## p = { \## f0, FUNC_## f1, FUNC_## f2 \0 , SG0, NONE, NONE);1 , SG0, NONE, NONE);2 , SG0, NONE, NONE);3 , SG0, NONE, NONE);4 , IRQ0_IN, IRQ0_OUT, TWI_SCL_M);5 , IRQ1_IN, IRQ1_OUT, TWI_SCL_M);6 , UART, NONE, NONE);7 , UART, NONE, NONE);8 , SI, SFP, TWI_SCL_M);9 , PCI_WAKE, SFP, SI);10 , PTP0, SFP, TWI_SCL_M);11 , PTP1, SFP, TWI_SCL_M);12 , REF_CLK, SFP, TWI_SCL_M);13 , REF_CLK, SFP, TWI_SCL_M);14 , REF_CLK, IRQ0_OUT, SI);15 , REF_CLK, IRQ1_OUT, SI);16 , TACHO, SFP, SI);17 , PWM, NONE, TWI_SCL_M);18 , PTP2, SFP, SI);19 , PTP3, SFP, SI);20 , UART2, SFP, SI);21 , UART2, NONE, NONE);22 , MIIM, SFP, TWI2);23 , MIIM, SFP, TWI2);24 , TWI, NONE, NONE);25 , TWI, SFP, TWI_SCL_M);26 , TWI_SCL_M, SFP, SI);27 , TWI_SCL_M, SFP, SI);28 , TWI_SCL_M, SFP, SI);29 , TWI_SCL_M, NONE, NONE);30 , TWI_SCL_M, NONE, NONE);31 , TWI_SCL_M, NONE, NONE);32 , TWI_SCL_M, NONE, NONE);33 , RCVRD_CLK, NONE, NONE);34 , RCVRD_CLK, NONE, NONE);35 , RCVRD_CLK, NONE, NONE);36 , RCVRD_CLK, NONE, NONE);#define SERVALT_PIN(n) { \"GPIO_" #n , \## n \static const struct pinctrl_pin_desc servalt_pins[] = {0 ),1 ),2 ),3 ),4 ),5 ),6 ),7 ),8 ),9 ),10 ),11 ),12 ),13 ),14 ),15 ),16 ),17 ),18 ),19 ),20 ),21 ),22 ),23 ),24 ),25 ),26 ),27 ),28 ),29 ),30 ),31 ),32 ),33 ),34 ),35 ),36 ),#define SPARX5_P(p, f0, f1, f2) \static struct ocelot_pin_caps sparx5_pin_## p = { \## f0, FUNC_## f1, FUNC_## f2 \0 , SG0, PLL_STAT, NONE);1 , SG0, NONE, NONE);2 , SG0, NONE, NONE);3 , SG0, NONE, NONE);4 , SG1, NONE, NONE);5 , SG1, NONE, NONE);6 , IRQ0_IN, IRQ0_OUT, SFP);7 , IRQ1_IN, IRQ1_OUT, SFP);8 , PTP0, NONE, SFP);9 , PTP1, SFP, TWI_SCL_M);10 , UART, NONE, NONE);11 , UART, NONE, NONE);12 , SG1, NONE, NONE);13 , SG1, NONE, NONE);14 , TWI, TWI_SCL_M, NONE);15 , TWI, NONE, NONE);16 , SI, TWI_SCL_M, SFP);17 , SI, TWI_SCL_M, SFP);18 , SI, TWI_SCL_M, SFP);19 , PCI_WAKE, TWI_SCL_M, SFP);20 , IRQ0_OUT, TWI_SCL_M, SFP);21 , IRQ1_OUT, TACHO, SFP);22 , TACHO, IRQ0_OUT, TWI_SCL_M);23 , PWM, UART3, TWI_SCL_M);24 , PTP2, UART3, TWI_SCL_M);25 , PTP3, SI, TWI_SCL_M);26 , UART2, SI, TWI_SCL_M);27 , UART2, SI, TWI_SCL_M);28 , TWI2, SI, SFP);29 , TWI2, SI, SFP);30 , SG2, SI, PWM);31 , SG2, SI, TWI_SCL_M);32 , SG2, SI, TWI_SCL_M);33 , SG2, SI, SFP);34 , NONE, TWI_SCL_M, EMMC);35 , SFP, TWI_SCL_M, EMMC);36 , SFP, TWI_SCL_M, EMMC);37 , SFP, NONE, EMMC);38 , NONE, TWI_SCL_M, EMMC);39 , SI2, TWI_SCL_M, EMMC);40 , SI2, TWI_SCL_M, EMMC);41 , SI2, TWI_SCL_M, EMMC);42 , SI2, TWI_SCL_M, EMMC);43 , SI2, TWI_SCL_M, EMMC);44 , SI, SFP, EMMC);45 , SI, SFP, EMMC);46 , NONE, SFP, EMMC);47 , NONE, SFP, EMMC);48 , TWI3, SI, SFP);49 , TWI3, NONE, SFP);50 , SFP, NONE, TWI_SCL_M);51 , SFP, SI, TWI_SCL_M);52 , SFP, MIIM, TWI_SCL_M);53 , SFP, MIIM, TWI_SCL_M);54 , SFP, PTP2, TWI_SCL_M);55 , SFP, PTP3, PCI_WAKE);56 , MIIM, SFP, TWI_SCL_M);57 , MIIM, SFP, TWI_SCL_M);58 , MIIM, SFP, TWI_SCL_M);59 , MIIM, SFP, NONE);60 , RECO_CLK, NONE, NONE);61 , RECO_CLK, NONE, NONE);62 , RECO_CLK, PLL_STAT, NONE);63 , RECO_CLK, NONE, NONE);#define SPARX5_PIN(n) { \"GPIO_" #n , \## n \static const struct pinctrl_pin_desc sparx5_pins[] = {0 ),1 ),2 ),3 ),4 ),5 ),6 ),7 ),8 ),9 ),10 ),11 ),12 ),13 ),14 ),15 ),16 ),17 ),18 ),19 ),20 ),21 ),22 ),23 ),24 ),25 ),26 ),27 ),28 ),29 ),30 ),31 ),32 ),33 ),34 ),35 ),36 ),37 ),38 ),39 ),40 ),41 ),42 ),43 ),44 ),45 ),46 ),47 ),48 ),49 ),50 ),51 ),52 ),53 ),54 ),55 ),56 ),57 ),58 ),59 ),60 ),61 ),62 ),63 ),#define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \static struct ocelot_pin_caps lan966x_pin_## p = { \## f0, FUNC_## f1, FUNC_## f2, \## f3 \## f4, FUNC_## f5, FUNC_## f6, \## f7 \/* Pinmuxing table taken from data sheet */ /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ 0 , GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);1 , GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);2 , GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);3 , GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);4 , GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);5 , GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);6 , GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);7 , GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);8 , GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R);9 , GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R);10 , GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R);11 , GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R);12 , GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R);13 , GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R);14 , GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R);15 , GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R);16 , GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);17 , GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);18 , GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);19 , GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);20 , GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R);21 , GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R);22 , GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R);23 , GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R);24 , GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R);25 , GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R);26 , GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R);27 , GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, PWM_a, R);28 , GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R);29 , GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R);30 , GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R);31 , GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R);32 , GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R);33 , GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R);34 , GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R);35 , GPIO, FC1_b, PTPSYNC_0, SGPIO_a, CAN0_b, NONE, NONE, R);36 , GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R);37 , GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R);38 , GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R);39 , GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R);40 , GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R);41 , GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R);42 , GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R);43 , GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R);44 , GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R);45 , GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R);46 , GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R);47 , GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R);48 , GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R);49 , GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R);50 , GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R);51 , GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, PWM_b, IRQ_IN_b, R);52 , GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R);53 , GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R);54 , GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R);55 , GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R);56 , GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R);57 , GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R);58 , GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R);59 , GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R);60 , GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R);61 , GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R);62 , GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R);63 , GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R);64 , GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R);65 , GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R);66 , GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R);67 , GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);68 , GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);69 , GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);70 , GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);71 , GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);72 , GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);73 , GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R);74 , GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R);75 , GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R);76 , GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R);77 , GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R);#define LAN966X_PIN(n) { \"GPIO_" #n , \## n \static const struct pinctrl_pin_desc lan966x_pins[] = {0 ),1 ),2 ),3 ),4 ),5 ),6 ),7 ),8 ),9 ),10 ),11 ),12 ),13 ),14 ),15 ),16 ),17 ),18 ),19 ),20 ),21 ),22 ),23 ),24 ),25 ),26 ),27 ),28 ),29 ),30 ),31 ),32 ),33 ),34 ),35 ),36 ),37 ),38 ),39 ),40 ),41 ),42 ),43 ),44 ),45 ),46 ),47 ),48 ),49 ),50 ),51 ),52 ),53 ),54 ),55 ),56 ),57 ),58 ),59 ),60 ),61 ),62 ),63 ),64 ),65 ),66 ),67 ),68 ),69 ),70 ),71 ),72 ),73 ),74 ),75 ),76 ),77 ),#define LAN969X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \static struct ocelot_pin_caps lan969x_pin_## p = { \## f0, FUNC_## f1, FUNC_## f2, \## f3 \## f4, FUNC_## f5, FUNC_## f6, \## f7 \/* Pinmuxing table taken from data sheet */ /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ 0 , GPIO, IRQ0, FC_SHRD, PCIE_PERST, NONE, NONE, NONE, R);1 , GPIO, IRQ1, FC_SHRD, USB_POWER, NONE, NONE, NONE, R);2 , GPIO, FC, NONE, NONE, NONE, NONE, NONE, R);3 , GPIO, FC, NONE, NONE, NONE, NONE, NONE, R);4 , GPIO, FC, NONE, NONE, NONE, NONE, NONE, R);5 , GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R);6 , GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R);7 , GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R);8 , GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R);9 , GPIO, MIIM, MIIM_Sa, CLKMON, NONE, NONE, NONE, R);10 , GPIO, MIIM, MIIM_Sa, CLKMON, NONE, NONE, NONE, R);11 , GPIO, MIIM_IRQ, MIIM_Sa, CLKMON, NONE, NONE, NONE, R);12 , GPIO, IRQ3, FC_SHRD, USB2PHY_RST, NONE, NONE, NONE, R);13 , GPIO, IRQ4, FC_SHRD, USB_OVER_DETECT, NONE, NONE, NONE, R);14 , GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R);15 , GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R);16 , GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R);17 , GPIO, EMMC_SD, QSPI1, PTPSYNC_0, USB_POWER, NONE, NONE, R);18 , GPIO, EMMC_SD, QSPI1, PTPSYNC_1, USB2PHY_RST, NONE, NONE, R);19 , GPIO, EMMC_SD, QSPI1, PTPSYNC_2, USB_OVER_DETECT, NONE, NONE, R);20 , GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R);21 , GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R);22 , GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R);23 , GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R);24 , GPIO, EMMC_SD, NONE, NONE, NONE, NONE, NONE, R);25 , GPIO, FAN, FUSA, CAN0_a, QSPI1, NONE, NONE, R);26 , GPIO, FAN, FUSA, CAN0_a, QSPI1, NONE, NONE, R);27 , GPIO, SYNCE, FC, MIIM, QSPI1, NONE, NONE, R);28 , GPIO, SYNCE, FC, MIIM, QSPI1, NONE, NONE, R);29 , GPIO, SYNCE, FC, MIIM_IRQ, QSPI1, NONE, NONE, R);30 , GPIO, PTPSYNC_0, USB_ULPI, FC_SHRD, QSPI1, NONE, NONE, R);31 , GPIO, PTPSYNC_1, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R);32 , GPIO, PTPSYNC_2, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R);33 , GPIO, SD, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R);34 , GPIO, SD, USB_ULPI, CAN1, FC_SHRD, NONE, NONE, R);35 , GPIO, SD, USB_ULPI, CAN1, FC_SHRD, NONE, NONE, R);36 , GPIO, SD, USB_ULPI, PCIE_PERST, FC_SHRD, NONE, NONE, R);37 , GPIO, SD, USB_ULPI, CAN0_b, NONE, NONE, NONE, R);38 , GPIO, SD, USB_ULPI, CAN0_b, NONE, NONE, NONE, R);39 , GPIO, SD, USB_ULPI, MIIM, NONE, NONE, NONE, R);40 , GPIO, SD, USB_ULPI, MIIM, NONE, NONE, NONE, R);41 , GPIO, SD, USB_ULPI, MIIM_IRQ, NONE, NONE, NONE, R);42 , GPIO, PTPSYNC_3, CAN1, NONE, NONE, NONE, NONE, R);43 , GPIO, PTPSYNC_4, CAN1, NONE, NONE, NONE, NONE, R);44 , GPIO, PTPSYNC_5, SFP_SD, NONE, NONE, NONE, NONE, R);45 , GPIO, PTPSYNC_6, SFP_SD, NONE, NONE, NONE, NONE, R);46 , GPIO, PTPSYNC_7, SFP_SD, NONE, NONE, NONE, NONE, R);47 , GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R);48 , GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R);49 , GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R);50 , GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R);51 , GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R);52 , GPIO, FAN, SFP_SD, NONE, NONE, NONE, NONE, R);53 , GPIO, FAN, SFP_SD, NONE, NONE, NONE, NONE, R);54 , GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R);55 , GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R);56 , GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R);57 , GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_3, NONE, NONE, R);58 , GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_4, NONE, NONE, R);59 , GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_5, NONE, NONE, R);60 , GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_6, NONE, NONE, R);61 , GPIO, MIIM, FC_SHRD, TWI, NONE, NONE, NONE, R);62 , GPIO, MIIM, FC_SHRD, TWI, NONE, NONE, NONE, R);63 , GPIO, MIIM_IRQ, FC_SHRD, TWI, NONE, NONE, NONE, R);64 , GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R);65 , GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R);66 , GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R);#define LAN969X_PIN(n) { \"GPIO_" #n , \## n \static const struct pinctrl_pin_desc lan969x_pins[] = {0 ),1 ),2 ),3 ),4 ),5 ),6 ),7 ),8 ),9 ),10 ),11 ),12 ),13 ),14 ),15 ),16 ),17 ),18 ),19 ),20 ),21 ),22 ),23 ),24 ),25 ),26 ),27 ),28 ),29 ),30 ),31 ),32 ),33 ),34 ),35 ),36 ),37 ),38 ),39 ),40 ),41 ),42 ),43 ),44 ),45 ),46 ),47 ),48 ),49 ),50 ),51 ),52 ),53 ),54 ),55 ),56 ),57 ),58 ),59 ),60 ),61 ),62 ),63 ),64 ),65 ),66 ),static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)return ARRAY_SIZE(ocelot_function_names);static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev,unsigned int function)return ocelot_function_names[function];static int ocelot_get_function_groups(struct pinctrl_dev *pctldev,unsigned int function,const char *const **groups,unsigned *const num_groups)struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);return 0 ;static int ocelot_pin_function_idx(struct ocelot_pinctrl *info,unsigned int pin, unsigned int function)struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data;int i;for (i = 0 ; i < OCELOT_FUNC_PER_PIN; i++) {if (function == p->functions[i])return i;if (function == p->a_functions[i])return i + OCELOT_FUNC_PER_PIN;return -1 ;#define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32 ))))static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,unsigned int selector, unsigned int group)struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;unsigned int p = pin->pin % 32 ;int f;if (f < 0 )return -EINVAL;/* * f is encoded on two bits. * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of * ALT[1] * This is racy because both registers can't be updated at the same time * but it doesn't matter much for now. * Note: ALT0/ALT1 are organized specially for 64 gpio targets 0 , info, pin->pin),1 , info, pin->pin),1 ) << p);return 0 ;static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev,unsigned int selector, unsigned int group)struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;unsigned int p = pin->pin % 32 ;int f;if (f < 0 )return -EINVAL;/* * f is encoded on three bits. * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2] * This is racy because three registers can't be updated at the same time * but it doesn't matter much for now. * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets 0 , info, pin->pin),1 , info, pin->pin),1 ) << p);2 , info, pin->pin),2 ) << p);return 0 ;#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32 )))static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,struct pinctrl_gpio_range *range,unsigned int pin, bool input)struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);unsigned int p = pin % 32 ;0 : BIT(p));return 0 ;static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev,struct pinctrl_gpio_range *range,unsigned int offset)struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);unsigned int p = offset % 32 ;0 , info, offset),0 );1 , info, offset),0 );return 0 ;static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev,struct pinctrl_gpio_range *range,unsigned int offset)struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);unsigned int p = offset % 32 ;0 , info, offset),0 );1 , info, offset),0 );2 , info, offset),0 );return 0 ;static const struct pinmux_ops ocelot_pmx_ops = {static const struct pinmux_ops lan966x_pmx_ops = {static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);return info->desc->npins;static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev,unsigned int group)struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);return info->desc->pins[group].name;static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,unsigned int group,const unsigned int **pins,unsigned int *num_pins)struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);1 ;return 0 ;static int ocelot_hw_get_value(struct ocelot_pinctrl *info,unsigned int pin,unsigned int reg,int *val)int ret = -EOPNOTSUPP;if (info->pincfg) {const struct ocelot_pincfg_data *opd = info->pincfg_data;if (ret)return ret;0 ;switch (reg) {case PINCONF_BIAS:break ;case PINCONF_SCHMITT:break ;case PINCONF_DRIVE_STRENGTH:break ;default :break ;return ret;static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr,int ret;if (ret)return ret;return ret;static int ocelot_hw_set_value(struct ocelot_pinctrl *info,unsigned int pin,unsigned int reg,int val)int ret = -EOPNOTSUPP;if (info->pincfg) {const struct ocelot_pincfg_data *opd = info->pincfg_data;switch (reg) {case PINCONF_BIAS:break ;case PINCONF_SCHMITT:break ;case PINCONF_DRIVE_STRENGTH:if (val <= 3 )else break ;default :break ;return ret;static int ocelot_pinconf_get(struct pinctrl_dev *pctldev,unsigned int pin, unsigned long *config)struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);int val, err;switch (param) {case PIN_CONFIG_BIAS_DISABLE:case PIN_CONFIG_BIAS_PULL_UP:case PIN_CONFIG_BIAS_PULL_DOWN:if (err)return err;if (param == PIN_CONFIG_BIAS_DISABLE)0 );else if (param == PIN_CONFIG_BIAS_PULL_DOWN)else /* PIN_CONFIG_BIAS_PULL_UP */ break ;case PIN_CONFIG_INPUT_SCHMITT_ENABLE:if (!info->pincfg_data->schmitt_bit)return -EOPNOTSUPP;if (err)return err;break ;case PIN_CONFIG_DRIVE_STRENGTH:if (err)return err;break ;case PIN_CONFIG_OUTPUT:if (err)return err;32 ));break ;case PIN_CONFIG_INPUT_ENABLE:case PIN_CONFIG_OUTPUT_ENABLE:if (err)return err;32 );if (param == PIN_CONFIG_OUTPUT_ENABLE)else break ;default :return -EOPNOTSUPP;return 0 ;static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,unsigned long *configs, unsigned int num_configs)struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);const struct ocelot_pincfg_data *opd = info->pincfg_data;int cfg, err = 0 ;for (cfg = 0 ; cfg < num_configs; cfg++) {switch (param) {case PIN_CONFIG_BIAS_DISABLE:case PIN_CONFIG_BIAS_PULL_UP:case PIN_CONFIG_BIAS_PULL_DOWN:0 :if (err)goto err;break ;case PIN_CONFIG_INPUT_SCHMITT_ENABLE:if (!opd->schmitt_bit)return -EOPNOTSUPP;0 ;if (err)goto err;break ;case PIN_CONFIG_DRIVE_STRENGTH:if (err)goto err;break ;case PIN_CONFIG_OUTPUT_ENABLE:case PIN_CONFIG_INPUT_ENABLE:case PIN_CONFIG_OUTPUT:32 ;if (arg)else 0 : BIT(p));break ;default :return err;static const struct pinconf_ops ocelot_confops = {true ,static const struct pinctrl_ops ocelot_pctl_ops = {static const struct ocelot_match_data luton_desc = {"luton-pinctrl" ,static const struct ocelot_match_data serval_desc = {"serval-pinctrl" ,static const struct ocelot_match_data ocelot_desc = {"ocelot-pinctrl" ,static const struct ocelot_match_data jaguar2_desc = {"jaguar2-pinctrl" ,static const struct ocelot_match_data servalt_desc = {"servalt-pinctrl" ,static const struct ocelot_match_data sparx5_desc = {"sparx5-pinctrl" ,4 ),3 ),1 , 0 ),2 ),static const struct ocelot_match_data lan966x_desc = {"lan966x-pinctrl" ,3 ),2 ),1 , 0 ),static const struct ocelot_match_data lan969x_desc = {"lan969x-pinctrl" ,3 ),2 ),1 , 0 ),static int ocelot_create_group_func_map(struct device *dev,struct ocelot_pinctrl *info)int f, npins, i;sizeof (u8), GFP_KERNEL);if (!pins)return -ENOMEM;for (f = 0 ; f < FUNC_MAX; f++) {for (npins = 0 , i = 0 ; i < info->desc->npins; i++) {if (ocelot_pin_function_idx(info, i, f) >= 0 )if (!npins)continue ;sizeof (char *),if (!info->func[f].groups) {return -ENOMEM;for (i = 0 ; i < npins; i++)return 0 ;static int ocelot_pinctrl_register(struct platform_device *pdev,struct ocelot_pinctrl *info)int ret;if (ret) {"Unable to create group func map.\n" );return ret;if (IS_ERR(info->pctl)) {"Failed to register pinctrl\n" );return PTR_ERR(info->pctl);return 0 ;static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset)struct ocelot_pinctrl *info = gpiochip_get_data(chip);unsigned int val;return !!(val & BIT(offset % 32 ));static int ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,int value)struct ocelot_pinctrl *info = gpiochip_get_data(chip);if (value)return regmap_write(info->map,32 ));return regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),32 ));static int ocelot_gpio_get_direction(struct gpio_chip *chip,unsigned int offset)struct ocelot_pinctrl *info = gpiochip_get_data(chip);unsigned int val;if (val & BIT(offset % 32 ))return GPIO_LINE_DIRECTION_OUT;return GPIO_LINE_DIRECTION_IN;static int ocelot_gpio_direction_output(struct gpio_chip *chip,unsigned int offset, int value)struct ocelot_pinctrl *info = gpiochip_get_data(chip);unsigned int pin = BIT(offset % 32 );if (value)else return pinctrl_gpio_direction_output(chip, offset);static const struct gpio_chip ocelot_gpiolib_chip = {static void ocelot_irq_mask(struct irq_data *data)struct gpio_chip *chip = irq_data_get_irq_chip_data(data);struct ocelot_pinctrl *info = gpiochip_get_data(chip);unsigned int gpio = irqd_to_hwirq(data);32 ), 0 );static void ocelot_irq_work(struct work_struct *work)struct ocelot_irq_work *w = container_of(work, struct ocelot_irq_work, irq_work);struct irq_chip *parent_chip = irq_desc_get_chip(w->irq_desc);struct gpio_chip *chip = irq_desc_get_chip_data(w->irq_desc);struct irq_data *data = irq_desc_get_irq_data(w->irq_desc);unsigned int gpio = irqd_to_hwirq(data);static void ocelot_irq_unmask_level(struct irq_data *data)struct gpio_chip *chip = irq_data_get_irq_chip_data(data);struct ocelot_pinctrl *info = gpiochip_get_data(chip);struct irq_desc *desc = irq_data_to_desc(data);unsigned int gpio = irqd_to_hwirq(data);unsigned int bit = BIT(gpio % 32 );bool ack = false , active = false ;int val;/* Check if the interrupt line is still active. */ if ((!(val & bit) && trigger_level == IRQ_TYPE_LEVEL_LOW) ||true ;/* * Check if the interrupt controller has seen any changes in the * interrupt line. if (val & bit)true ;/* Try to clear any rising edges */ if (!active && ack)/* Enable the interrupt now */ /* * In case the interrupt line is still active then it means that * there happen another interrupt while the line was active. * So we missed that one, so we need to kick the interrupt again * handler. if ((!(val & bit) && trigger_level == IRQ_TYPE_LEVEL_LOW) ||true ;if (active) {struct ocelot_irq_work *work;sizeof (*work), GFP_ATOMIC);if (!work)return ;static void ocelot_irq_unmask(struct irq_data *data)struct gpio_chip *chip = irq_data_get_irq_chip_data(data);struct ocelot_pinctrl *info = gpiochip_get_data(chip);unsigned int gpio = irqd_to_hwirq(data);32 ), BIT(gpio % 32 ));static void ocelot_irq_ack(struct irq_data *data)struct gpio_chip *chip = irq_data_get_irq_chip_data(data);struct ocelot_pinctrl *info = gpiochip_get_data(chip);unsigned int gpio = irqd_to_hwirq(data);32 ), BIT(gpio % 32 ));static int ocelot_irq_set_type(struct irq_data *data, unsigned int type);static const struct irq_chip ocelot_level_irqchip = {"gpio" ,static const struct irq_chip ocelot_irqchip = {"gpio" ,static int ocelot_irq_set_type(struct irq_data *data, unsigned int type)if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))if (type & IRQ_TYPE_EDGE_BOTH)return 0 ;static void ocelot_irq_handler(struct irq_desc *desc)struct irq_chip *parent_chip = irq_desc_get_chip(desc);struct gpio_chip *chip = irq_desc_get_handler_data(desc);struct ocelot_pinctrl *info = gpiochip_get_data(chip);unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride;unsigned int reg = 0 , irq, i;unsigned long irqs;for (i = 0 ; i < info->stride; i++) {4 * i, ®);if (!reg)continue ;32 U, info->desc->npins - 32 * i))32 * i);static int ocelot_gpiochip_register(struct platform_device *pdev,struct ocelot_pinctrl *info)struct gpio_chip *gc;struct gpio_irq_chip *girq;int irq;1 ;"ocelot-gpio" ;0 );if (irq > 0 ) {1 ;1 ,sizeof (*girq->parents),if (!girq->parents)return -ENOMEM;0 ] = irq;return devm_gpiochip_add_data(&pdev->dev, gc, info);static const struct of_device_id ocelot_pinctrl_of_match[] = {"mscc,luton-pinctrl" , .data = &luton_desc },"mscc,serval-pinctrl" , .data = &serval_desc },"mscc,ocelot-pinctrl" , .data = &ocelot_desc },"mscc,jaguar2-pinctrl" , .data = &jaguar2_desc },"mscc,servalt-pinctrl" , .data = &servalt_desc },"microchip,sparx5-pinctrl" , .data = &sparx5_desc },"microchip,lan966x-pinctrl" , .data = &lan966x_desc },"microchip,lan9691-pinctrl" , .data = &lan969x_desc },static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev,const struct ocelot_pinctrl *info)void __iomem *base;const struct regmap_config regmap_config = {32 ,32 ,4 ,4 ,"pincfg" ,1 );if (IS_ERR(base)) {"Failed to ioremap config registers (no extended pinconf)\n" );return NULL;return devm_regmap_init_mmio(&pdev->dev, base, ®map_config);static void ocelot_destroy_workqueue(void *data)static int ocelot_pinctrl_probe(struct platform_device *pdev)const struct ocelot_match_data *data;struct device *dev = &pdev->dev;struct ocelot_pinctrl *info;struct reset_control *reset;struct regmap *pincfg;int ret;struct regmap_config regmap_config = {32 ,32 ,4 ,sizeof (*info), GFP_KERNEL);if (!info)return -ENOMEM;if (!data)return -EINVAL;sizeof (*info->desc),if (!info->desc)return -ENOMEM;"ocelot_ordered" , 0 );if (!info->wq)return -ENOMEM;if (ret)return ret;"switch" );if (IS_ERR(reset))return dev_err_probe(dev, PTR_ERR(reset),"Failed to get reset\n" );1 + (info->desc->npins - 1 ) / 32 ;15 * 4 ;0 , ®map_config);if (IS_ERR(info->map))return dev_err_probe(dev, PTR_ERR(info->map),"Failed to create regmap\n" );/* Pinconf registers */ if (info->desc->confops) {if (IS_ERR(pincfg))"Failed to create pincfg regmap\n" );else if (ret)return ret;if (ret)return ret;"driver registered\n" );return 0 ;static struct platform_driver ocelot_pinctrl_driver = {"pinctrl-ocelot" ,true ,"Ocelot Chip Pinctrl Driver" );"Dual MIT/GPL" );
Messung V0.5 in Prozent C=95 H=96 G=95
¤ Dauer der Verarbeitung: 0.29 Sekunden
(vorverarbeitet am 2026-06-07)
¤ *© Formatika GbR, Deutschland
