/* * Driver for the Gemini pin controller * * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> * * This is a group-only pin controller. #include <linux/err.h>#include <linux/init.h>#include <linux/io.h>#include <linux/mfd/syscon.h>#include <linux/of.h>#include <linux/platform_device.h>#include <linux/regmap.h>#include <linux/seq_file.h>#include <linux/slab.h>#include <linux/string_choices.h>#include <linux/pinctrl/machine.h>#include <linux/pinctrl/pinconf-generic.h>#include <linux/pinctrl/pinconf.h>#include <linux/pinctrl/pinctrl.h>#include <linux/pinctrl/pinmux.h>#include "pinctrl-utils.h" #define DRIVER_NAME "pinctrl-gemini" /** * struct gemini_pin_conf - information about configuring a pin * @pin: the pin number * @reg: config register * @mask: the bits affecting the configuration of the pin struct gemini_pin_conf {unsigned int pin;/** * struct gemini_pmx - state holder for the gemini pin controller * @dev: a pointer back to containing device * @virtbase: the offset to the controller in virtual memory * @map: regmap to access registers * @is_3512: whether the SoC/package is the 3512 variant * @is_3516: whether the SoC/package is the 3516 variant * @flash_pin: whether the flash pin (extended pins for parallel * flash) is set * @confs: pin config information * @nconfs: number of pin config information items struct gemini_pmx {struct device *dev;struct pinctrl_dev *pctl;struct regmap *map;bool is_3512;bool is_3516;bool flash_pin;const struct gemini_pin_conf *confs;unsigned int nconfs;/** * struct gemini_pin_group - describes a Gemini pin group * @name: the name of this specific pin group * @pins: an array of discrete physical pins used in this group, taken * from the driver-local pin enumeration space * @num_pins: the number of pins in this group array, i.e. the number of * elements in .pins so we can iterate over that array * @mask: bits to clear to enable this when doing pin muxing * @value: bits to set to enable this when doing pin muxing * @driving_mask: bitmask for the IO Pad driving register for this * group, if it supports altering the driving strength of * its lines. struct gemini_pin_group {const char *name;const unsigned int *pins;const unsigned int num_pins;/* Some straight-forward control registers */ #define GLOBAL_WORD_ID 0 x00#define GLOBAL_STATUS 0 x04#define GLOBAL_STATUS_FLPIN BIT(20 )#define GLOBAL_IODRIVE 0 x10#define GLOBAL_GMAC_CTRL_SKEW 0 x1c#define GLOBAL_GMAC0_DATA_SKEW 0 x20#define GLOBAL_GMAC1_DATA_SKEW 0 x24/* * Global Miscellaneous Control Register * This register controls all Gemini pad/pin multiplexing * * It is a tricky register though: * - For the bits named *_ENABLE, once you DISABLE something, it simply cannot * be brought back online, so it means permanent disablement of the * corresponding pads. * - For the bits named *_DISABLE, once you enable something, it cannot be * DISABLED again. So you select a flash configuration once, and then * you are stuck with it. #define GLOBAL_MISC_CTRL 0 x30#define GEMINI_GMAC_IOSEL_MASK GENMASK(28 , 27 )/* Not really used */ #define GEMINI_GMAC_IOSEL_GMAC0_GMII BIT(28 )/* Activated with GMAC1 */ #define GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII BIT(27 )/* This will be the default */ #define GEMINI_GMAC_IOSEL_GMAC0_RGMII_GMAC1_GPIO2 0 #define TVC_CLK_PAD_ENABLE BIT(20 )#define PCI_CLK_PAD_ENABLE BIT(17 )#define LPC_CLK_PAD_ENABLE BIT(16 )#define TVC_PADS_ENABLE BIT(9 )#define SSP_PADS_ENABLE BIT(8 )#define LCD_PADS_ENABLE BIT(7 )#define LPC_PADS_ENABLE BIT(6 )#define PCI_PADS_ENABLE BIT(5 )#define IDE_PADS_ENABLE BIT(4 )#define DRAM_PADS_POWERDOWN BIT(3 )#define NAND_PADS_DISABLE BIT(2 )#define PFLASH_PADS_DISABLE BIT(1 )#define SFLASH_PADS_DISABLE BIT(0 )#define PADS_MASK (GENMASK(9 , 0 ) | BIT(16 ) | BIT(17 ) | BIT(20 ) | BIT(27 ))#define PADS_MAXBIT 27 /* Ordered by bit index */ static const char * const gemini_padgroups[] = {"serial flash" ,"parallel flash" ,"NAND flash" ,"DRAM" ,"IDE" ,"PCI" ,"LPC" ,"LCD" ,"SSP" ,"TVC" ,"LPC CLK" ,"PCI CLK" ,"TVC CLK" ,"GMAC1" ,static const struct pinctrl_pin_desc gemini_3512_pins[] = {/* Row A */ 0 , "A1 VREF CTRL" ),1 , "A2 VCC2IO CTRL" ),2 , "A3 DRAM CK" ),3 , "A4 DRAM CK N" ),4 , "A5 DRAM A5" ),5 , "A6 DRAM CKE" ),6 , "A7 DRAM DQ11" ),7 , "A8 DRAM DQ0" ),8 , "A9 DRAM DQ5" ),9 , "A10 DRAM DQ6" ),10 , "A11 DRAM DRAM VREF" ),11 , "A12 DRAM BA1" ),12 , "A13 DRAM A2" ),13 , "A14 PCI GNT1 N" ),14 , "A15 PCI REQ9 N" ),15 , "A16 PCI REQ2 N" ),16 , "A17 PCI REQ3 N" ),17 , "A18 PCI AD31" ),/* Row B */ 18 , "B1 VCCK CTRL" ),19 , "B2 PWR EN" ),20 , "B3 RTC CLKI" ),21 , "B4 DRAM A4" ),22 , "B5 DRAM A6" ),23 , "B6 DRAM A12" ),24 , "B7 DRAM DQS1" ),25 , "B8 DRAM DQ15" ),26 , "B9 DRAM DQ4" ),27 , "B10 DRAM DQS0" ),28 , "B11 DRAM WE N" ),29 , "B12 DRAM A10" ),30 , "B13 DRAM A3" ),31 , "B14 PCI GNT0 N" ),32 , "B15 PCI GNT3 N" ),33 , "B16 PCI REQ1 N" ),34 , "B17 PCI AD30" ),35 , "B18 PCI AD29" ),/* Row C */ 36 , "C1 CIR RST N" ), /* REALLY? CIR is not in 3512... */ 37 , "C2 XTALI" ),38 , "C3 PWR BTN" ),39 , "C4 RTC CLKO" ),40 , "C5 DRAM A7" ),41 , "C6 DRAM A11" ),42 , "C7 DRAM DQ10" ),43 , "C8 DRAM DQ14" ),44 , "C9 DRAM DQ3" ),45 , "C10 DRAM DQ7" ),46 , "C11 DRAM CAS N" ),47 , "C12 DRAM A0" ),48 , "C13 PCI INT0 N" ),49 , "C14 EXT RESET N" ),50 , "C15 PCI GNT2 N" ),51 , "C16 PCI AD28" ),52 , "C17 PCI AD27" ),53 , "C18 PCI AD26" ),/* Row D */ 54 , "D1 AVCCKHA" ),55 , "D2 AGNDIOHA" ),56 , "D3 XTALO" ),57 , "D4 AVCC3IOHA" ),58 , "D5 DRAM A8" ),59 , "D6 DRAM A9" ),60 , "D7 DRAM DQ9" ),61 , "D8 DRAM DQ13" ),62 , "D9 DRAM DQ2" ),63 , "D10 DRAM A13" ),64 , "D11 DRAM RAS N" ),65 , "D12 DRAM A1" ),66 , "D13 PCI INTC N" ),67 , "D14 PCI CLK" ),68 , "D15 PCI AD25" ),69 , "D16 PCI AD24" ),70 , "D17 PCI CBE3 N" ),71 , "D18 PCI AD23" ),/* Row E */ 72 , "E1 AVCC3IOHA" ),73 , "E2 EBG" ),74 , "E3 AVCC3IOHB" ),75 , "E4 REXT" ),76 , "E5 GND" ),77 , "E6 DRAM DQM1" ),78 , "E7 DRAM DQ8" ),79 , "E8 DRAM DQ12" ),80 , "E9 DRAM DQ1" ),81 , "E10 DRAM DQM0" ),82 , "E11 DRAM BA0" ),83 , "E12 PCI INTA N" ),84 , "E13 PCI INTB N" ),85 , "E14 GND" ),86 , "E15 PCI AD22" ),87 , "E16 PCI AD21" ),88 , "E17 PCI AD20" ),89 , "E18 PCI AD19" ),/* Row F */ 90 , "F1 SATA0 RXDP" ),91 , "F2 SATA0 RXDN" ),92 , "F3 AGNDK 0" ),93 , "F4 AVCC3 S" ),94 , "F5 AVCCK P" ),95 , "F6 GND" ),96 , "F7 VCC2IOHA 2" ),97 , "F8 VCC2IOHA 2" ),98 , "F9 V1" ),99 , "F10 V1" ),100 , "F11 VCC2IOHA 2" ),101 , "F12 VCC2IOHA 2" ),102 , "F13 GND" ),103 , "F14 PCI AD18" ),104 , "F15 PCI AD17" ),105 , "F16 PCI AD16" ),106 , "F17 PCI CBE2 N" ),107 , "F18 PCI FRAME N" ),/* Row G */ 108 , "G1 SATA0 TXDP" ),109 , "G2 SATA0 TXDN" ),110 , "G3 AGNDK 1" ),111 , "G4 AVCCK 0" ),112 , "G5 TEST CLKOUT" ),113 , "G6 AGND" ),114 , "G7 GND" ),115 , "G8 VCC2IOHA 2" ),116 , "G9 V1" ),117 , "G10 V1" ),118 , "G11 VCC2IOHA 2" ),119 , "G12 GND" ),120 , "G13 VCC3IOHA" ),121 , "G14 PCI IRDY N" ),122 , "G15 PCI TRDY N" ),123 , "G16 PCI DEVSEL N" ),124 , "G17 PCI STOP N" ),125 , "G18 PCI PAR" ),/* Row H */ 126 , "H1 SATA1 TXDP" ),127 , "H2 SATA1 TXDN" ),128 , "H3 AGNDK 2" ),129 , "H4 AVCCK 1" ),130 , "H5 AVCCK S" ),131 , "H6 AVCCKHB" ),132 , "H7 AGND" ),133 , "H8 GND" ),134 , "H9 GND" ),135 , "H10 GND" ),136 , "H11 GND" ),137 , "H12 VCC3IOHA" ),138 , "H13 VCC3IOHA" ),139 , "H14 PCI CBE1 N" ),140 , "H15 PCI AD15" ),141 , "H16 PCI AD14" ),142 , "H17 PCI AD13" ),143 , "H18 PCI AD12" ),/* Row J (for some reason I is skipped) */ 144 , "J1 SATA1 RXDP" ),145 , "J2 SATA1 RXDN" ),146 , "J3 AGNDK 3" ),147 , "J4 AVCCK 2" ),148 , "J5 IDE DA1" ),149 , "J6 V1" ),150 , "J7 V1" ),151 , "J8 GND" ),152 , "J9 GND" ),153 , "J10 GND" ),154 , "J11 GND" ),155 , "J12 V1" ),156 , "J13 V1" ),157 , "J14 PCI AD11" ),158 , "J15 PCI AD10" ),159 , "J16 PCI AD9" ),160 , "J17 PCI AD8" ),161 , "J18 PCI CBE0 N" ),/* Row K */ 162 , "K1 IDE CS1 N" ),163 , "K2 IDE CS0 N" ),164 , "K3 AVCCK 3" ),165 , "K4 IDE DA2" ),166 , "K5 IDE DA0" ),167 , "K6 V1" ),168 , "K7 V1" ),169 , "K8 GND" ),170 , "K9 GND" ),171 , "K10 GND" ),172 , "K11 GND" ),173 , "K12 V1" ),174 , "K13 V1" ),175 , "K14 PCI AD3" ),176 , "K15 PCI AD4" ),177 , "K16 PCI AD5" ),178 , "K17 PCI AD6" ),179 , "K18 PCI AD7" ),/* Row L */ 180 , "L1 IDE INTRQ" ),181 , "L2 IDE DMACK N" ),182 , "L3 IDE IORDY" ),183 , "L4 IDE DIOR N" ),184 , "L5 IDE DIOW N" ),185 , "L6 VCC3IOHA" ),186 , "L7 VCC3IOHA" ),187 , "L8 GND" ),188 , "L9 GND" ),189 , "L10 GND" ),190 , "L11 GND" ),191 , "L12 VCC3IOHA" ),192 , "L13 VCC3IOHA" ),193 , "L14 GPIO0 30" ),194 , "L15 GPIO0 31" ),195 , "L16 PCI AD0" ),196 , "L17 PCI AD1" ),197 , "L18 PCI AD2" ),/* Row M */ 198 , "M1 IDE DMARQ" ),199 , "M2 IDE DD15" ),200 , "M3 IDE DD0" ),201 , "M4 IDE DD14" ),202 , "M5 IDE DD1" ),203 , "M6 VCC3IOHA" ),204 , "M7 GND" ),205 , "M8 VCC2IOHA 1" ),206 , "M9 V1" ),207 , "M10 V1" ),208 , "M11 VCC3IOHA" ),209 , "M12 GND" ),210 , "M13 VCC3IOHA" ),211 , "M14 GPIO0 25" ),212 , "M15 GPIO0 26" ),213 , "M16 GPIO0 27" ),214 , "M17 GPIO0 28" ),215 , "M18 GPIO0 29" ),/* Row N */ 216 , "N1 IDE DD13" ),217 , "N2 IDE DD2" ),218 , "N3 IDE DD12" ),219 , "N4 IDE DD3" ),220 , "N5 IDE DD11" ),221 , "N6 GND" ),222 , "N7 VCC2IOHA 1" ),223 , "N8 VCC2IOHA 1" ),224 , "N9 V1" ),225 , "N10 V1" ),226 , "N11 VCC3IOHA" ),227 , "N12 VCC3IOHA" ),228 , "N13 GND" ),229 , "N14 GPIO0 20" ),230 , "N15 GPIO0 21" ),231 , "N16 GPIO0 22" ),232 , "N17 GPIO0 23" ),233 , "N18 GPIO0 24" ),/* Row P (for some reason O is skipped) */ 234 , "P1 IDE DD4" ),235 , "P2 IDE DD10" ),236 , "P3 IDE DD5" ),237 , "P4 IDE DD9" ),238 , "P5 GND" ),239 , "P6 USB XSCO" ),240 , "P7 GMAC0 TXD3" ),241 , "P8 GMAC0 TXEN" ),242 , "P9 GMAC0 RXD2" ),243 , "P10 GMAC1 TXC" ),244 , "P11 GMAC1 RXD1" ),245 , "P12 MODE SEL 1" ),246 , "P13 GPIO1 28" ),247 , "P14 GND" ),248 , "P15 GPIO0 5" ),249 , "P16 GPIO0 17" ),250 , "P17 GPIO0 18" ),251 , "P18 GPIO0 19" ),/* Row R (for some reason Q is skipped) */ 252 , "R1 IDE DD6" ),253 , "R2 IDE DD8" ),254 , "R3 IDE DD7" ),255 , "R4 IDE RESET N" ),256 , "R5 ICE0 DBGACK" ),257 , "R6 USB XSCI" ),258 , "R7 GMAC0 TXD2" ),259 , "R8 GMAC0 RXDV" ),260 , "R9 GMAC0 RXD3" ),261 , "R10 GMAC1 TXD0" ),262 , "R11 GMAC1 RXD0" ),263 , "R12 MODE SEL 0" ),264 , "R13 MODE SEL 3" ),265 , "R14 GPIO0 0" ),266 , "R15 GPIO0 4" ),267 , "R16 GPIO0 9" ),268 , "R17 GPIO0 15" ),269 , "R18 GPIO0 16" ),/* Row T (for some reason S is skipped) */ 270 , "T1 ICE0 DBGRQ" ),271 , "T2 ICE0 IDO" ),272 , "T3 ICE0 ICK" ),273 , "T4 ICE0 IMS" ),274 , "T5 ICE0 IDI" ),275 , "T6 USB RREF" ),276 , "T7 GMAC0 TXD1" ),277 , "T8 GMAC0 RXC" ),278 , "T9 GMAC0 CRS" ),279 , "T10 GMAC1 TXD1" ),280 , "T11 GMAC1 RXC" ),281 , "T12 GMAC1 CRS" ),282 , "T13 EXT CLK" ),283 , "T14 GPIO1 31" ),284 , "T15 GPIO0 3" ),285 , "T16 GPIO0 8" ),286 , "T17 GPIO0 12" ),287 , "T18 GPIO0 14" ),/* Row U */ 288 , "U1 ICE0 IRST N" ),289 , "U2 USB0 VCCHSRT" ),290 , "U3 USB0 DP" ),291 , "U4 USB VCCA U20" ),292 , "U5 USB1 DP" ),293 , "U6 USB1 GNDHSRT 1" ),294 , "U7 GMAC0 TXD0" ),295 , "U8 GMAC0 RXD0" ),296 , "U9 GMAC1 COL" ),297 , "U10 GMAC1 TXD2" ),298 , "U11 GMAC1 RXDV" ),299 , "U12 GMAC1 RXD3" ),300 , "U13 MODE SEL 2" ),301 , "U14 GPIO1 30" ),302 , "U15 GPIO0 2" ),303 , "U16 GPIO0 7" ),304 , "U17 GPIO0 11" ),305 , "U18 GPIO0 13" ),/* Row V */ 306 , "V1 USB0 GNDHSRT" ),307 , "V2 USB0 DM" ),308 , "V3 USB GNDA U20" ),309 , "V4 USB1 DM" ),310 , "V5 USB1 VCCHSRT1" ),311 , "V6 GMAC0 COL" ),312 , "V7 GMAC0 TXC" ),313 , "V8 GMAC0 RXD1" ),314 , "V9 REF CLK" ),315 , "V10 GMAC1 TXD3" ),316 , "V11 GMAC1 TXEN" ),317 , "V12 GMAC1 RXD2" ),318 , "V13 M30 CLK" ),319 , "V14 GPIO1 29" ),320 , "V15 GPIO0 1" ),321 , "V16 GPIO0 6" ),322 , "V17 GPIO0 10" ),323 , "V18 SYS RESET N" ),/* Digital ground */ static const unsigned int gnd_3512_pins[] = {76 , 85 , 95 , 102 , 114 , 119 , 133 , 134 , 135 , 136 , 151 , 152 , 153 , 154 , 169 ,170 , 171 , 172 , 187 , 188 , 189 , 190 , 204 , 209 , 221 , 228 , 238 , 247 static const unsigned int dram_3512_pins[] = {2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 21 , 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 ,30 , 40 , 41 , 42 , 43 , 44 , 45 , 46 , 47 , 58 , 59 , 60 , 61 , 62 , 63 , 64 , 65 , 77 ,78 , 79 , 80 , 81 , 82 static const unsigned int rtc_3512_pins[] = { 57 , 20 , 39 };static const unsigned int power_3512_pins[] = { 19 , 38 , 36 , 55 , 37 , 56 , 54 , 72 };static const unsigned int system_3512_pins[] = {318 , 264 , 300 , 245 , 263 , 282 , 314 , 323 , 49 ,static const unsigned int vcontrol_3512_pins[] = { 18 , 0 , 1 };static const unsigned int ice_3512_pins[] = { 256 , 270 , 271 , 272 , 273 , 274 , 288 };static const unsigned int ide_3512_pins[] = {162 , 163 , 165 , 166 , 148 , 180 , 181 , 182 , 183 , 184 , 198 , 199 , 200 , 201 , 202 ,216 , 217 , 218 , 219 , 220 , 234 , 235 , 236 , 237 , 252 , 253 , 254 , 255 static const unsigned int sata_3512_pins[] = {75 , 74 , 73 , 93 , 94 , 131 , 112 , 130 , 92 , 91 , 90 , 111 , 110 , 109 , 108 , 129 ,128 , 127 , 126 , 147 , 146 , 145 , 144 , 164 static const unsigned int usb_3512_pins[] = {306 , 289 , 307 , 290 , 239 , 257 , 275 , 308 , 291 , 309 , 292 , 310 , 293 /* GMII, ethernet pins */ static const unsigned int gmii_gmac0_3512_pins[] = {240 , 241 , 242 , 258 , 259 , 260 , 276 , 277 , 278 , 294 , 295 , 311 , 312 , 313 static const unsigned int gmii_gmac1_3512_pins[] = {243 , 244 , 261 , 262 , 279 , 280 , 281 , 296 , 297 , 298 , 299 , 315 , 316 , 317 static const unsigned int pci_3512_pins[] = {13 , 14 , 15 , 16 , 17 , 31 , 32 , 33 , 34 , 35 , 48 , 50 , 51 , 52 , 53 , 66 , 67 , 68 , 69 ,70 , 71 , 83 , 84 , 86 , 87 , 88 , 89 , 103 , 104 , 105 , 106 , 107 , 121 , 122 , 123 ,124 , 125 , 139 , 140 , 141 , 142 , 143 , 157 , 158 , 159 , 160 , 161 , 175 , 176 , 177 ,178 , 179 , 195 , 196 , 197 /* * Apparently the LPC interface is using the PCICLK for the clocking so * PCI needs to be active at the same time. static const unsigned int lpc_3512_pins[] = {285 , /* LPC_LAD[0] */ 304 , /* LPC_SERIRQ */ 286 , /* LPC_LAD[2] */ 305 , /* LPC_LFRAME# */ 287 , /* LPC_LAD[3] */ 268 , /* LPC_LAD[1] */ /* Character LCD */ static const unsigned int lcd_3512_pins[] = {262 , 244 , 317 , 299 , 246 , 319 , 301 , 283 , 269 , 233 , 211 static const unsigned int ssp_3512_pins[] = {285 , /* SSP_97RST# SSP AC97 Reset, active low */ 304 , /* SSP_FSC */ 286 , /* SSP_ECLK */ 305 , /* SSP_TXD */ 287 , /* SSP_RXD */ 268 , /* SSP_SCLK */ static const unsigned int uart_rxtx_3512_pins[] = {267 , /* UART_SIN serial input, RX */ 322 , /* UART_SOUT serial output, TX */ static const unsigned int uart_modem_3512_pins[] = {285 , /* UART_NDCD DCD carrier detect */ 304 , /* UART_NDTR DTR data terminal ready */ 286 , /* UART_NDSR DSR data set ready */ 305 , /* UART_NRTS RTS request to send */ 287 , /* UART_NCTS CTS clear to send */ 268 , /* UART_NRI RI ring indicator */ static const unsigned int tvc_3512_pins[] = {246 , /* TVC_DATA[0] */ 319 , /* TVC_DATA[1] */ 301 , /* TVC_DATA[2] */ 283 , /* TVC_DATA[3] */ 320 , /* TVC_DATA[4] */ 302 , /* TVC_DATA[5] */ 284 , /* TVC_DATA[6] */ 266 , /* TVC_DATA[7] */ static const unsigned int tvc_clk_3512_pins[] = {265 , /* TVC_CLK */ /* NAND flash pins */ static const unsigned int nflash_3512_pins[] = {199 , 200 , 201 , 202 , 216 , 217 , 218 , 219 , 220 , 234 , 235 , 236 , 237 , 252 ,253 , 254 , 249 , 250 , 232 , 233 , 211 , 193 , 194 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */ static const unsigned int pflash_3512_pins[] = {162 , 163 , 165 , 166 , 148 , 199 , 200 , 201 , 202 , 216 , 217 , 218 , 219 , 220 ,234 , 235 , 236 , 237 , 252 , 253 , 254 , 251 , 229 , 232 , 233 , 211 , 212 , 213 ,214 , 215 , 193 , 194 /* * The parallel flash can be set up in a 26-bit address bus mode exposing * A[0-15] (A[15] takes the place of ALE), but it has the * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be * used at the same time. static const unsigned int pflash_3512_pins_extended[] = {162 , 163 , 165 , 166 , 148 , 199 , 200 , 201 , 202 , 216 , 217 , 218 , 219 , 220 ,234 , 235 , 236 , 237 , 252 , 253 , 254 , 251 , 229 , 232 , 233 , 211 , 212 , 213 ,214 , 215 , 193 , 194 ,/* The extra pins */ 296 , 315 , 297 , 279 , 261 , 243 , 316 , 298 , 280 , 262 , 244 , 317 , 299 , 281 ,265 ,/* Serial flash pins CE0, CE1, DI, DO, CK */ static const unsigned int sflash_3512_pins[] = { 230 , 231 , 232 , 233 , 211 };/* The GPIO0A (0) pin overlap with TVC CLK and extended parallel flash */ static const unsigned int gpio0a_3512_pins[] = { 265 };/* The GPIO0B (1-4) pins overlap with TVC and ICE */ static const unsigned int gpio0b_3512_pins[] = { 320 , 302 , 284 , 266 };/* The GPIO0C (5-7) pins overlap with ICE */ static const unsigned int gpio0c_3512_pins[] = { 248 , 321 , 303 };/* The GPIO0D (9,10) pins overlap with UART RX/TX */ static const unsigned int gpio0d_3512_pins[] = { 267 , 322 };/* The GPIO0E (8,11-15) pins overlap with LPC, UART modem pins, SSP */ static const unsigned int gpio0e_3512_pins[] = { 285 , 304 , 286 , 305 , 287 , 268 };/* The GPIO0F (16) pins overlap with LCD */ static const unsigned int gpio0f_3512_pins[] = { 269 };/* The GPIO0G (17,18) pins overlap with NAND flash CE0, CE1 */ static const unsigned int gpio0g_3512_pins[] = { 249 , 250 };/* The GPIO0H (19,20) pins overlap with parallel flash CE0, CE1 */ static const unsigned int gpio0h_3512_pins[] = { 251 , 229 };/* The GPIO0I (21,22) pins overlap with serial flash CE0, CE1 */ static const unsigned int gpio0i_3512_pins[] = { 230 , 231 };/* The GPIO0J (23) pins overlap with all flash */ static const unsigned int gpio0j_3512_pins[] = { 232 };/* The GPIO0K (24,25) pins overlap with all flash and LCD */ static const unsigned int gpio0k_3512_pins[] = { 233 , 211 };/* The GPIO0L (26-29) pins overlap with parallel flash */ static const unsigned int gpio0l_3512_pins[] = { 212 , 213 , 214 , 215 };/* The GPIO0M (30,31) pins overlap with parallel flash and NAND flash */ static const unsigned int gpio0m_3512_pins[] = { 193 , 194 };/* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */ static const unsigned int gpio1a_3512_pins[] = { 162 , 163 , 165 , 166 , 148 };/* The GPIO1B (5-10, 27) pins overlap with just IDE */ static const unsigned int gpio1b_3512_pins[] = {180 , 181 , 182 , 183 , 184 , 198 , 255 /* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */ static const unsigned int gpio1c_3512_pins[] = {199 , 200 , 201 , 202 , 216 , 217 , 218 , 219 , 220 , 234 , 235 , 236 , 237 ,252 , 253 , 254 /* The GPIO1D (28-31) pins overlap with LCD and TVC */ static const unsigned int gpio1d_3512_pins[] = { 246 , 319 , 301 , 283 };/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */ static const unsigned int gpio2a_3512_pins[] = { 315 , 297 , 279 , 261 };/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */ static const unsigned int gpio2b_3512_pins[] = { 262 , 244 , 317 , 299 };/* The GPIO2C (8-31) pins overlap with PCI */ static const unsigned int gpio2c_3512_pins[] = {17 , 34 , 35 , 51 , 52 , 53 , 68 , 69 , 71 , 86 , 87 , 88 , 89 , 103 , 104 , 105 ,140 , 141 , 142 , 143 , 157 , 158 , 159 , 160 /* Groups for the 3512 SoC/package */ static const struct gemini_pin_group gemini_3512_pin_groups[] = {"gndgrp" ,"dramgrp" ,"rtcgrp" ,"powergrp" ,"systemgrp" ,"vcontrolgrp" ,"icegrp" ,/* Conflict with some GPIO groups */ "idegrp" ,/* Conflict with all flash usage */ 21 , 20 ),"satagrp" ,"usbgrp" ,"gmii_gmac0_grp" ,17 , 16 ),"gmii_gmac1_grp" ,/* Bring out RGMII on the GMAC1 pins */ 19 , 18 ),"pcigrp" ,/* Conflict only with GPIO2 */ 23 , 22 ),"lpcgrp" ,/* Conflict with SSP and UART modem pins */ "lcdgrp" ,/* Conflict with TVC and ICE */ "sspgrp" ,/* Conflict with LPC and UART modem pins */ "uartrxtxgrp" ,/* No conflicts except GPIO */ "uartmodemgrp" ,/* * Conflict with LPC and SSP, * so when those are both disabled, modem UART can thrive. "tvcgrp" ,/* Conflict with character LCD and ICE */ "tvcclkgrp" ,/* * The construction is done such that it is possible to use a serial * flash together with a NAND or parallel (NOR) flash, but it is not * possible to use NAND and parallel flash together. To use serial * flash with one of the two others, the muxbits need to be flipped * around before any access. "nflashgrp" ,/* Conflict with IDE, parallel and serial flash */ "pflashgrp" ,/* Conflict with IDE, NAND and serial flash */ "sflashgrp" ,/* Conflict with IDE, NAND and parallel flash */ "gpio0agrp" ,/* Conflict with TVC CLK */ "gpio0bgrp" ,/* Conflict with TVC and ICE */ "gpio0cgrp" ,/* Conflict with ICE */ "gpio0dgrp" ,/* Conflict with UART RX/TX */ "gpio0egrp" ,/* Conflict with LPC, UART modem pins, SSP */ "gpio0fgrp" ,/* Conflict with LCD */ "gpio0ggrp" ,/* Conflict with NAND flash */ "gpio0hgrp" ,/* Conflict with parallel flash */ "gpio0igrp" ,/* Conflict with serial flash */ "gpio0jgrp" ,/* Conflict with all flash */ "gpio0kgrp" ,/* Conflict with all flash and LCD */ "gpio0lgrp" ,/* Conflict with parallel flash */ "gpio0mgrp" ,/* Conflict with parallel and NAND flash */ "gpio1agrp" ,/* Conflict with IDE and parallel flash */ "gpio1bgrp" ,/* Conflict with IDE only */ "gpio1cgrp" ,/* Conflict with IDE, parallel and NAND flash */ "gpio1dgrp" ,/* Conflict with LCD and TVC */ "gpio2agrp" ,/* Conflict with GMII GMAC1 and extended parallel flash */ "gpio2bgrp" ,/* Conflict with GMII GMAC1, extended parallel flash and LCD */ "gpio2cgrp" ,/* Conflict with PCI */ /* Pin names for the pinmux subsystem, 3516 variant */ static const struct pinctrl_pin_desc gemini_3516_pins[] = {/* Row A */ 0 , "A1 AVCC3IOHA" ),1 , "A2 DRAM CK N" ),2 , "A3 DRAM CK" ),3 , "A4 DRAM DQM1" ),4 , "A5 DRAM DQ9" ),5 , "A6 DRAM DQ13" ),6 , "A7 DRAM DQ1" ),7 , "A8 DRAM DQ2" ),8 , "A9 DRAM DQ4" ),9 , "A10 DRAM VREF" ),10 , "A11 DRAM DQ24" ),11 , "A12 DRAM DQ28" ),12 , "A13 DRAM DQ30" ),13 , "A14 DRAM DQ18" ),14 , "A15 DRAM DQ21" ),15 , "A16 DRAM CAS_N" ),16 , "A17 DRAM BA1" ),17 , "A18 PCI INTA N" ),18 , "A19 PCI INTB N" ),19 , "A20 PCI INTC N" ),/* Row B */ 20 , "B1 PWR EN" ),21 , "B2 GND" ),22 , "B3 RTC CLKO" ),23 , "B4 DRAM A5" ),24 , "B5 DRAM A6" ),25 , "B6 DRAM DQS1" ),26 , "B7 DRAM DQ11" ),27 , "B8 DRAM DQ0" ),28 , "B9 DRAM DQS0" ),29 , "B10 DRAM DQ7" ),30 , "B11 DRAM DQS3" ),31 , "B12 DRAM DQ27" ),32 , "B13 DRAM DQ31" ),33 , "B14 DRAM DQ20" ),34 , "B15 DRAM DQS2" ),35 , "B16 DRAM WE N" ),36 , "B17 DRAM A10" ),37 , "B18 DRAM A2" ),38 , "B19 GND" ),39 , "B20 PCI GNT0 N" ),/* Row C */ 40 , "C1 AGNDIOHA" ),41 , "C2 XTALI" ),42 , "C3 GND" ),43 , "C4 RTC CLKI" ),44 , "C5 DRAM A12" ),45 , "C6 DRAM A11" ),46 , "C7 DRAM DQ8" ),47 , "C8 DRAM DQ10" ),48 , "C9 DRAM DQ3" ),49 , "C10 DRAM DQ6" ),50 , "C11 DRAM DQM0" ),51 , "C12 DRAM DQ26" ),52 , "C13 DRAM DQ16" ),53 , "C14 DRAM DQ22" ),54 , "C15 DRAM DQM2" ),55 , "C16 DRAM BA0" ),56 , "C17 DRAM A3" ),57 , "C18 GND" ),58 , "C19 PCI GNT1 N" ),59 , "C20 PCI REQ2 N" ),/* Row D */ 60 , "D1 AVCC3IOAHA" ),61 , "D2 AVCCKHA" ),62 , "D3 XTALO" ),63 , "D4 GND" ),64 , "D5 CIR RXD" ),65 , "D6 DRAM A7" ),66 , "D7 DRAM A4" ),67 , "D8 DRAM A8" ),68 , "D9 DRAM CKE" ),69 , "D10 DRAM DQ14" ),70 , "D11 DRAM DQ5" ),71 , "D12 DRAM DQ25" ),72 , "D13 DRAM DQ17" ),73 , "D14 DRAM DQ23" ),74 , "D15 DRAM RAS N" ),75 , "D16 DRAM A1" ),76 , "D17 GND" ),77 , "D18 EXT RESET N" ),78 , "D19 PCI REQ1 N" ),79 , "D20 PCI REQ3 N" ),/* Row E */ 80 , "E1 VCC2IO CTRL" ),81 , "E2 VREF CTRL" ),82 , "E3 CIR RST N" ),83 , "E4 PWR BTN" ),84 , "E5 GND" ),85 , "E6 CIR TXD" ),86 , "E7 VCCK CTRL" ),87 , "E8 DRAM A9" ),88 , "E9 DRAM DQ12" ),89 , "E10 DRAM DQ15" ),90 , "E11 DRAM DQM3" ),91 , "E12 DRAM DQ29" ),92 , "E13 DRAM DQ19" ),93 , "E14 DRAM A13" ),94 , "E15 DRAM A0" ),95 , "E16 GND" ),96 , "E17 PCI INTD N" ),97 , "E18 PCI GNT3 N" ),98 , "E19 PCI AD29" ),99 , "E20 PCI AD28" ),/* Row F */ 100 , "F1 AVCCKHB" ),101 , "F2 AVCCK P" ),102 , "F3 EBG" ),103 , "F4 REXT" ),104 , "F5 AVCC3IOHB" ),105 , "F6 GND" ),106 , "F7 VCC2IOHA 2" ),107 , "F8 VCC2IOHA 2" ),108 , "F9 VCC2IOHA 2" ),109 , "F10 V1" ),110 , "F11 V1" ),111 , "F12 VCC2IOHA 2" ),112 , "F13 VCC2IOHA 2" ),113 , "F14 VCC2IOHA 2" ),114 , "F15 GND" ),115 , "F16 PCI CLK" ),116 , "F17 PCI GNT2 N" ),117 , "F18 PCI AD31" ),118 , "F19 PCI AD26" ),119 , "F20 PCI CBE3 N" ),/* Row G */ 120 , "G1 SATA0 RXDP" ),121 , "G2 SATA0 RXDN" ),122 , "G3 AGNDK 0" ),123 , "G4 AVCCK S" ),124 , "G5 AVCC3 S" ),125 , "G6 VCC2IOHA 2" ),126 , "G7 GND" ),127 , "G8 VCC2IOHA 2" ),128 , "G9 V1" ),129 , "G10 V1" ),130 , "G11 V1" ),131 , "G12 V1" ),132 , "G13 VCC2IOHA 2" ),133 , "G14 GND" ),134 , "G15 VCC3IOHA" ),135 , "G16 PCI REQ0 N" ),136 , "G17 PCI AD30" ),137 , "G18 PCI AD24" ),138 , "G19 PCI AD23" ),139 , "G20 PCI AD21" ),/* Row H */ 140 , "H1 SATA0 TXDP" ),141 , "H2 SATA0 TXDN" ),142 , "H3 AGNDK 1" ),143 , "H4 AVCCK 0" ),144 , "H5 TEST CLKOUT" ),145 , "H6 AGND" ),146 , "H7 VCC2IOHA 2" ),147 , "H8 GND" ),148 , "H9 GND" ),149 , "H10 GDN" ),150 , "H11 GND" ),151 , "H12 GND" ),152 , "H13 GND" ),153 , "H14 VCC3IOHA" ),154 , "H15 VCC3IOHA" ),155 , "H16 PCI AD27" ),156 , "H17 PCI AD25" ),157 , "H18 PCI AD22" ),158 , "H19 PCI AD18" ),159 , "H20 PCI AD17" ),/* Row J (for some reason I is skipped) */ 160 , "J1 SATA1 TXDP" ),161 , "J2 SATA1 TXDN" ),162 , "J3 AGNDK 2" ),163 , "J4 AVCCK 1" ),164 , "J5 AGND" ),165 , "J6 AGND" ),166 , "J7 V1" ),167 , "J8 GND" ),168 , "J9 GND" ),169 , "J10 GND" ),170 , "J11 GND" ),171 , "J12 GND" ),172 , "J13 GND" ),173 , "J14 V1" ),174 , "J15 VCC3IOHA" ),175 , "J16 PCI AD19" ),176 , "J17 PCI AD20" ),177 , "J18 PCI AD16" ),178 , "J19 PCI CBE2 N" ),179 , "J20 PCI FRAME N" ),/* Row K */ 180 , "K1 SATA1 RXDP" ),181 , "K2 SATA1 RXDN" ),182 , "K3 AGNDK 3" ),183 , "K4 AVCCK 2" ),184 , "K5 AGND" ),185 , "K6 V1" ),186 , "K7 V1" ),187 , "K8 GND" ),188 , "K9 GND" ),189 , "K10 GND" ),190 , "K11 GND" ),191 , "K12 GND" ),192 , "K13 GND" ),193 , "K14 V1" ),194 , "K15 V1" ),195 , "K16 PCI TRDY N" ),196 , "K17 PCI IRDY N" ),197 , "K18 PCI DEVSEL N" ),198 , "K19 PCI STOP N" ),199 , "K20 PCI PAR" ),/* Row L */ 200 , "L1 IDE CS0 N" ),201 , "L2 IDE DA0" ),202 , "L3 AVCCK 3" ),203 , "L4 AGND" ),204 , "L5 IDE DIOR N" ),205 , "L6 V1" ),206 , "L7 V1" ),207 , "L8 GND" ),208 , "L9 GND" ),209 , "L10 GND" ),210 , "L11 GND" ),211 , "L12 GND" ),212 , "L13 GND" ),213 , "L14 V1" ),214 , "L15 V1" ),215 , "L16 PCI AD12" ),216 , "L17 PCI AD13" ),217 , "L18 PCI AD14" ),218 , "L19 PCI AD15" ),219 , "L20 PCI CBE1 N" ),/* Row M */ 220 , "M1 IDE DA1" ),221 , "M2 IDE CS1 N" ),222 , "M3 IDE DA2" ),223 , "M4 IDE DMACK N" ),224 , "M5 IDE DD1" ),225 , "M6 VCC3IOHA" ),226 , "M7 V1" ),227 , "M8 GND" ),228 , "M9 GND" ),229 , "M10 GND" ),230 , "M11 GND" ),231 , "M12 GND" ),232 , "M13 GND" ),233 , "M14 V1" ),234 , "M15 VCC3IOHA" ),235 , "M16 PCI AD7" ),236 , "M17 PCI AD6" ),237 , "M18 PCI AD9" ),238 , "M19 PCI AD10" ),239 , "M20 PCI AD11" ),/* Row N */ 240 , "N1 IDE IORDY" ),241 , "N2 IDE INTRQ" ),242 , "N3 IDE DIOW N" ),243 , "N4 IDE DD15" ),244 , "N5 IDE DMARQ" ),245 , "N6 VCC3IOHA" ),246 , "N7 VCC3IOHA" ),247 , "N8 GND" ),248 , "N9 GND" ),249 , "N10 GND" ),250 , "N11 GND" ),251 , "N12 GND" ),252 , "N13 GND" ),253 , "N14 VCC3IOHA" ),254 , "N15 VCC3IOHA" ),255 , "N16 PCI CLKRUN N" ),256 , "N17 PCI AD0" ),257 , "N18 PCI AD4" ),258 , "N19 PCI CBE0 N" ),259 , "N20 PCI AD8" ),/* Row P (for some reason O is skipped) */ 260 , "P1 IDE DD0" ),261 , "P2 IDE DD14" ),262 , "P3 IDE DD2" ),263 , "P4 IDE DD4" ),264 , "P5 IDE DD3" ),265 , "P6 VCC3IOHA" ),266 , "P7 GND" ),267 , "P8 VCC2IOHA 1" ),268 , "P9 V1" ),269 , "P10 V1" ),270 , "P11 V1" ),271 , "P12 V1" ),272 , "P13 VCC3IOHA" ),273 , "P14 GND" ),274 , "P15 VCC3IOHA" ),275 , "P16 GPIO0 30" ),276 , "P17 GPIO0 28" ),277 , "P18 PCI AD1" ),278 , "P19 PCI AD3" ),279 , "P20 PCI AD5" ),/* Row R (for some reason Q is skipped) */ 280 , "R1 IDE DD13" ),281 , "R2 IDE DD12" ),282 , "R3 IDE DD10" ),283 , "R4 IDE DD6" ),284 , "R5 ICE0 IDI" ),285 , "R6 GND" ),286 , "R7 VCC2IOHA 1" ),287 , "R8 VCC2IOHA 1" ),288 , "R9 VCC2IOHA 1" ),289 , "R10 V1" ),290 , "R11 V1" ),291 , "R12 VCC3IOHA" ),292 , "R13 VCC3IOHA" ),293 , "R14 VCC3IOHA" ),294 , "R15 GND" ),295 , "R16 GPIO0 23" ),296 , "R17 GPIO0 21" ),297 , "R18 GPIO0 26" ),298 , "R19 GPIO0 31" ),299 , "R20 PCI AD2" ),/* Row T (for some reason S is skipped) */ 300 , "T1 IDE DD11" ),301 , "T2 IDE DD5" ),302 , "T3 IDE DD8" ),303 , "T4 ICE0 IDO" ),304 , "T5 GND" ),305 , "T6 USB GNDA U20" ),306 , "T7 GMAC0 TXD0" ),307 , "T8 GMAC0 TXEN" ),308 , "T9 GMAC1 TXD3" ),309 , "T10 GMAC1 RXDV" ),310 , "T11 GMAC1 RXD2" ),311 , "T12 GPIO1 29" ),312 , "T13 GPIO0 3" ),313 , "T14 GPIO0 9" ),314 , "T15 GPIO0 16" ),315 , "T16 GND" ),316 , "T17 GPIO0 14" ),317 , "T18 GPIO0 19" ),318 , "T19 GPIO0 27" ),319 , "T20 GPIO0 29" ),/* Row U */ 320 , "U1 IDE DD9" ),321 , "U2 IDE DD7" ),322 , "U3 ICE0 ICK" ),323 , "U4 GND" ),324 , "U5 USB XSCO" ),325 , "U6 GMAC0 TXD1" ),326 , "U7 GMAC0 TXD3" ),327 , "U8 GMAC0 TXC" ),328 , "U9 GMAC0 RXD3" ),329 , "U10 GMAC1 TXD0" ),330 , "U11 GMAC1 CRS" ),331 , "U12 EXT CLK" ),332 , "U13 DEV DEF" ),333 , "U14 GPIO0 0" ),334 , "U15 GPIO0 4" ),335 , "U16 GPIO0 10" ),336 , "U17 GND" ),337 , "U18 GPIO0 17" ),338 , "U19 GPIO0 22" ),339 , "U20 GPIO0 25" ),/* Row V */ 340 , "V1 ICE0 DBGACK" ),341 , "V2 ICE0 DBGRQ" ),342 , "V3 GND" ),343 , "V4 ICE0 IRST N" ),344 , "V5 USB XSCI" ),345 , "V6 GMAC0 COL" ),346 , "V7 GMAC0 TXD2" ),347 , "V8 GMAC0 RXDV" ),348 , "V9 GMAC0 RXD1" ),349 , "V10 GMAC1 COL" ),350 , "V11 GMAC1 TXC" ),351 , "V12 GMAC1 RXD1" ),352 , "V13 MODE SEL1" ),353 , "V14 GPIO1 28" ),354 , "V15 GPIO0 1" ),355 , "V16 GPIO0 8" ),356 , "V17 GPIO0 11" ),357 , "V18 GND" ),358 , "V19 GPIO0 18" ),359 , "V20 GPIO0 24" ),/* Row W */ 360 , "W1 IDE RESET N" ),361 , "W2 GND" ),362 , "W3 USB0 VCCHSRT" ),363 , "W4 USB0 DP" ),364 , "W5 USB VCCA U20" ),365 , "W6 USB1 DP" ),366 , "W7 USB1 GNDHSRT" ),367 , "W8 GMAC0 RXD0" ),368 , "W9 GMAC0 CRS" ),369 , "W10 GMAC1 TXD2" ),370 , "W11 GMAC1 TXEN" ),371 , "W12 GMAC1 RXD3" ),372 , "W13 MODE SEL0" ),373 , "W14 MODE SEL3" ),374 , "W15 GPIO1 31" ),375 , "W16 GPIO0 5" ),376 , "W17 GPIO0 7" ),377 , "W18 GPIO0 12" ),378 , "W19 GND" ),379 , "W20 GPIO0 20" ),/* Row Y */ 380 , "Y1 ICE0 IMS" ),381 , "Y2 USB0 GNDHSRT" ),382 , "Y3 USB0 DM" ),383 , "Y4 USB RREF" ),384 , "Y5 USB1 DM" ),385 , "Y6 USB1 VCCHSRT" ),386 , "Y7 GMAC0 RXC" ),387 , "Y8 GMAC0 RXD2" ),388 , "Y9 REF CLK" ),389 , "Y10 GMAC1 TXD1" ),390 , "Y11 GMAC1 RXC" ),391 , "Y12 GMAC1 RXD0" ),392 , "Y13 M30 CLK" ),393 , "Y14 MODE SEL2" ),394 , "Y15 GPIO1 30" ),395 , "Y16 GPIO0 2" ),396 , "Y17 GPIO0 6" ),397 , "Y18 SYS RESET N" ),398 , "Y19 GPIO0 13" ),399 , "Y20 GPIO0 15" ),/* Digital ground */ static const unsigned int gnd_3516_pins[] = {21 , 38 , 42 , 57 , 63 , 76 , 84 , 95 , 105 , 114 , 126 , 133 , 147 , 148 , 149 , 150 ,151 , 152 , 167 , 168 , 169 , 170 , 171 , 172 , 187 , 188 , 189 , 190 , 191 , 192 ,207 , 208 , 209 , 210 , 211 , 212 , 227 , 228 , 229 , 230 , 231 , 232 , 247 , 248 ,249 , 250 , 251 , 252 , 266 , 273 , 285 , 294 , 304 , 315 , 323 , 336 , 342 , 357 ,361 , 378 static const unsigned int dram_3516_pins[] = {1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 23 , 24 , 25 , 26 ,27 , 28 , 29 , 30 , 31 , 32 , 33 , 34 , 35 , 36 , 37 , 44 , 45 , 46 , 47 , 48 , 49 , 50 ,51 , 52 , 53 , 54 , 55 , 56 , 65 , 66 , 67 , 68 , 69 , 70 , 71 , 72 , 73 , 74 , 75 ,87 , 88 , 89 , 90 , 91 , 92 , 93 , 94 static const unsigned int rtc_3516_pins[] = { 0 , 43 , 22 };static const unsigned int power_3516_pins[] = { 20 , 83 , 40 , 41 , 60 , 61 , 62 };static const unsigned int cir_3516_pins[] = { 85 , 64 , 82 };static const unsigned int system_3516_pins[] = {332 , 392 , 372 , 373 , 393 , 352 , 331 , 388 , 397 , 77 static const unsigned int vcontrol_3516_pins[] = { 86 , 81 , 80 };static const unsigned int ice_3516_pins[] = { 340 , 341 , 303 , 322 , 380 , 284 , 343 };static const unsigned int ide_3516_pins[] = {200 , 201 , 204 , 220 , 221 , 222 , 223 , 224 , 240 , 241 , 242 , 243 , 244 , 260 ,261 , 262 , 263 , 264 , 280 , 281 , 282 , 283 , 300 , 301 , 302 , 320 , 321 , 360 static const unsigned int sata_3516_pins[] = {100 , 101 , 102 , 103 , 104 , 120 , 121 , 122 , 123 , 124 , 140 , 141 , 142 , 143 ,144 , 160 , 161 , 162 , 163 , 180 , 181 , 182 , 183 , 202 static const unsigned int usb_3516_pins[] = {305 , 324 , 344 , 362 , 363 , 364 , 365 , 366 , 381 , 382 , 383 , 384 , 385 /* GMII, ethernet pins */ static const unsigned int gmii_gmac0_3516_pins[] = {306 , 307 , 325 , 326 , 327 , 328 , 345 , 346 , 347 , 348 , 367 , 368 , 386 , 387 static const unsigned int gmii_gmac1_3516_pins[] = {308 , 309 , 310 , 329 , 330 , 349 , 350 , 351 , 369 , 370 , 371 , 389 , 390 , 391 static const unsigned int pci_3516_pins[] = {17 , 18 , 19 , 39 , 58 , 59 , 78 , 79 , 96 , 97 , 98 , 99 , 115 , 116 , 117 , 118 ,119 , 135 , 136 , 137 , 138 , 139 , 155 , 156 , 157 , 158 , 159 , 175 , 176 , 177 ,178 , 179 , 195 , 196 , 197 , 198 , 199 , 215 , 216 , 217 , 218 , 219 , 235 , 236 ,237 , 238 , 239 , 255 , 256 , 257 , 258 , 259 , 277 , 278 , 279 , 299 /* * Apparently the LPC interface is using the PCICLK for the clocking so * PCI needs to be active at the same time. static const unsigned int lpc_3516_pins[] = {355 , /* LPC_LAD[0] */ 356 , /* LPC_SERIRQ */ 377 , /* LPC_LAD[2] */ 398 , /* LPC_LFRAME# */ 316 , /* LPC_LAD[3] */ 399 , /* LPC_LAD[1] */ /* Character LCD */ static const unsigned int lcd_3516_pins[] = {391 , 351 , 310 , 371 , 353 , 311 , 394 , 374 , 314 , 359 , 339 static const unsigned int ssp_3516_pins[] = {355 , /* SSP_97RST# SSP AC97 Reset, active low */ 356 , /* SSP_FSC */ 377 , /* SSP_ECLK */ 398 , /* SSP_TXD */ 316 , /* SSP_RXD */ 399 , /* SSP_SCLK */ static const unsigned int uart_rxtx_3516_pins[] = {313 , /* UART_SIN serial input, RX */ 335 , /* UART_SOUT serial output, TX */ static const unsigned int uart_modem_3516_pins[] = {355 , /* UART_NDCD DCD carrier detect */ 356 , /* UART_NDTR DTR data terminal ready */ 377 , /* UART_NDSR DSR data set ready */ 398 , /* UART_NRTS RTS request to send */ 316 , /* UART_NCTS CTS clear to send */ 399 , /* UART_NRI RI ring indicator */ static const unsigned int tvc_3516_pins[] = {353 , /* TVC_DATA[0] */ 311 , /* TVC_DATA[1] */ 394 , /* TVC_DATA[2] */ 374 , /* TVC_DATA[3] */ 354 , /* TVC_DATA[4] */ 395 , /* TVC_DATA[5] */ 312 , /* TVC_DATA[6] */ 334 , /* TVC_DATA[7] */ static const unsigned int tvc_clk_3516_pins[] = {333 , /* TVC_CLK */ /* NAND flash pins */ static const unsigned int nflash_3516_pins[] = {243 , 260 , 261 , 224 , 280 , 262 , 281 , 264 , 300 , 263 , 282 , 301 , 320 , 283 ,302 , 321 , 337 , 358 , 295 , 359 , 339 , 275 , 298 /* Parallel (NOR) flash pins, D[0-15], A[16-25], CE0, CE1, RB, WE, OE, ALE */ static const unsigned int pflash_3516_pins[] = {221 , 200 , 222 , 201 , 220 , 243 , 260 , 261 , 224 , 280 , 262 , 281 , 264 , 300 ,263 , 282 , 301 , 320 , 283 , 302 , 321 , 317 , 379 , 295 , 359 , 339 , 297 , 318 ,276 , 319 , 275 , 298 /* * The parallel flash can be set up in a 26-bit address bus mode exposing * A[0-15] (A[15] takes the place of ALE), but it has the * side effect of stealing pins from GMAC1 and TVC so these blocks cannot be * used at the same time. static const unsigned int pflash_3516_pins_extended[] = {221 , 200 , 222 , 201 , 220 , 243 , 260 , 261 , 224 , 280 , 262 , 281 , 264 , 300 ,263 , 282 , 301 , 320 , 283 , 302 , 321 , 317 , 379 , 295 , 359 , 339 , 297 , 318 ,276 , 319 , 275 , 298 ,/* The extra pins */ 349 , 308 , 369 , 389 , 329 , 350 , 370 , 309 , 390 , 391 , 351 , 310 , 371 , 330 ,333 /* Serial flash pins CE0, CE1, DI, DO, CK */ static const unsigned int sflash_3516_pins[] = { 296 , 338 , 295 , 359 , 339 };/* The GPIO0A (0-4) pins overlap with TVC and extended parallel flash */ static const unsigned int gpio0a_3516_pins[] = { 354 , 395 , 312 , 334 };/* The GPIO0B (5-7) pins overlap with ICE */ static const unsigned int gpio0b_3516_pins[] = { 375 , 396 , 376 };/* The GPIO0C (8,11-15) pins overlap with LPC, UART and SSP */ static const unsigned int gpio0c_3516_pins[] = { 355 , 356 , 377 , 398 , 316 , 399 };/* The GPIO0D (9,10) pins overlap with UART RX/TX */ static const unsigned int gpio0d_3516_pins[] = { 313 , 335 };/* The GPIO0E (16) pins overlap with LCD */ static const unsigned int gpio0e_3516_pins[] = { 314 };/* The GPIO0F (17,18) pins overlap with NAND flash CE0, CE1 */ static const unsigned int gpio0f_3516_pins[] = { 337 , 358 };/* The GPIO0G (19,20,26-29) pins overlap with parallel flash */ static const unsigned int gpio0g_3516_pins[] = { 317 , 379 , 297 , 318 , 276 , 319 };/* The GPIO0H (21,22) pins overlap with serial flash CE0, CE1 */ static const unsigned int gpio0h_3516_pins[] = { 296 , 338 };/* The GPIO0I (23) pins overlap with all flash */ static const unsigned int gpio0i_3516_pins[] = { 295 };/* The GPIO0J (24,25) pins overlap with all flash and LCD */ static const unsigned int gpio0j_3516_pins[] = { 359 , 339 };/* The GPIO0K (30,31) pins overlap with NAND flash */ static const unsigned int gpio0k_3516_pins[] = { 275 , 298 };/* The GPIO0L (0) pins overlap with TVC_CLK */ static const unsigned int gpio0l_3516_pins[] = { 333 };/* The GPIO1A (0-4) pins that overlap with IDE and parallel flash */ static const unsigned int gpio1a_3516_pins[] = { 221 , 200 , 222 , 201 , 220 };/* The GPIO1B (5-10,27) pins overlap with just IDE */ static const unsigned int gpio1b_3516_pins[] = { 241 , 223 , 240 , 204 , 242 , 244 , 360 };/* The GPIO1C (11-26) pins overlap with IDE, parallel flash and NAND flash */ static const unsigned int gpio1c_3516_pins[] = {243 , 260 , 261 , 224 , 280 , 262 , 281 , 264 , 300 , 263 , 282 , 301 , 320 , 283 ,302 , 321 /* The GPIO1D (28-31) pins overlap with TVC */ static const unsigned int gpio1d_3516_pins[] = { 353 , 311 , 394 , 374 };/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */ static const unsigned int gpio2a_3516_pins[] = { 308 , 369 , 389 , 329 };/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */ static const unsigned int gpio2b_3516_pins[] = { 391 , 351 , 310 , 371 };/* The GPIO2C (8-31) pins overlap with PCI */ static const unsigned int gpio2c_3516_pins[] = {259 , 237 , 238 , 239 , 215 , 216 , 217 , 218 , 177 , 159 , 158 , 175 , 176 , 139 ,157 , 138 , 137 , 156 , 118 , 155 , 99 , 98 , 136 , 117 /* Groups for the 3516 SoC/package */ static const struct gemini_pin_group gemini_3516_pin_groups[] = {"gndgrp" ,"dramgrp" ,"rtcgrp" ,"powergrp" ,"cirgrp" ,"systemgrp" ,"vcontrolgrp" ,"icegrp" ,/* Conflict with some GPIO groups */ "idegrp" ,/* Conflict with all flash usage */ 21 , 20 ),"satagrp" ,"usbgrp" ,"gmii_gmac0_grp" ,17 , 16 ),"gmii_gmac1_grp" ,/* Bring out RGMII on the GMAC1 pins */ 19 , 18 ),"pcigrp" ,/* Conflict only with GPIO2 */ 23 , 22 ),"lpcgrp" ,/* Conflict with SSP */ "lcdgrp" ,"sspgrp" ,/* Conflict with LPC */ "uartrxtxgrp" ,/* No conflicts except GPIO */ "uartmodemgrp" ,/* * Conflict with LPC and SSP, * so when those are both disabled, modem UART can thrive. "tvcgrp" ,/* Conflict with character LCD */ "tvcclkgrp" ,/* * The construction is done such that it is possible to use a serial * flash together with a NAND or parallel (NOR) flash, but it is not * possible to use NAND and parallel flash together. To use serial * flash with one of the two others, the muxbits need to be flipped * around before any access. "nflashgrp" ,/* Conflict with IDE, parallel and serial flash */ "pflashgrp" ,/* Conflict with IDE, NAND and serial flash */ "sflashgrp" ,/* Conflict with IDE, NAND and parallel flash */ "gpio0agrp" ,/* Conflict with TVC and ICE */ "gpio0bgrp" ,/* Conflict with ICE */ "gpio0cgrp" ,/* Conflict with LPC, UART and SSP */ "gpio0dgrp" ,/* Conflict with UART */ "gpio0egrp" ,/* Conflict with LCD */ "gpio0fgrp" ,/* Conflict with NAND flash */ "gpio0ggrp" ,/* Conflict with parallel flash */ "gpio0hgrp" ,/* Conflict with serial flash */ "gpio0igrp" ,/* Conflict with all flash */ "gpio0jgrp" ,/* Conflict with all flash and LCD */ "gpio0kgrp" ,/* Conflict with parallel and NAND flash */ "gpio0lgrp" ,/* Conflict with TVE CLK */ "gpio1agrp" ,/* Conflict with IDE and parallel flash */ "gpio1bgrp" ,/* Conflict with IDE only */ "gpio1cgrp" ,/* Conflict with IDE, parallel and NAND flash */ "gpio1dgrp" ,/* Conflict with TVC */ "gpio2agrp" ,/* Conflict with GMII GMAC1 and extended parallel flash */ "gpio2bgrp" ,/* Conflict with GMII GMAC1, extended parallel flash and LCD */ "gpio2cgrp" ,/* Conflict with PCI */ static int gemini_get_groups_count(struct pinctrl_dev *pctldev)struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);if (pmx->is_3512)return ARRAY_SIZE(gemini_3512_pin_groups);if (pmx->is_3516)return ARRAY_SIZE(gemini_3516_pin_groups);return 0 ;static const char *gemini_get_group_name(struct pinctrl_dev *pctldev,unsigned int selector)struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);if (pmx->is_3512)return gemini_3512_pin_groups[selector].name;if (pmx->is_3516)return gemini_3516_pin_groups[selector].name;return NULL;static int gemini_get_group_pins(struct pinctrl_dev *pctldev,unsigned int selector,const unsigned int **pins,unsigned int *num_pins)struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);/* The special case with the 3516 flash pin */ if (pmx->flash_pin &&"pflashgrp" )) {return 0 ;if (pmx->flash_pin &&"pflashgrp" )) {return 0 ;if (pmx->is_3512) {if (pmx->is_3516) {return 0 ;static void gemini_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,unsigned int offset)" " DRIVER_NAME);static const struct pinctrl_ops gemini_pctrl_ops = {/** * struct gemini_pmx_func - describes Gemini pinmux functions * @name: the name of this specific function * @groups: corresponding pin groups struct gemini_pmx_func {const char *name;const char * const *groups;const unsigned int num_groups;static const char * const dramgrps[] = { "dramgrp" };static const char * const rtcgrps[] = { "rtcgrp" };static const char * const powergrps[] = { "powergrp" };static const char * const cirgrps[] = { "cirgrp" };static const char * const systemgrps[] = { "systemgrp" };static const char * const vcontrolgrps[] = { "vcontrolgrp" };static const char * const icegrps[] = { "icegrp" };static const char * const idegrps[] = { "idegrp" };static const char * const satagrps[] = { "satagrp" };static const char * const usbgrps[] = { "usbgrp" };static const char * const gmiigrps[] = { "gmii_gmac0_grp" , "gmii_gmac1_grp" };static const char * const pcigrps[] = { "pcigrp" };static const char * const lpcgrps[] = { "lpcgrp" };static const char * const lcdgrps[] = { "lcdgrp" };static const char * const sspgrps[] = { "sspgrp" };static const char * const uartgrps[] = { "uartrxtxgrp" , "uartmodemgrp" };static const char * const tvcgrps[] = { "tvcgrp" };static const char * const nflashgrps[] = { "nflashgrp" };static const char * const pflashgrps[] = { "pflashgrp" , "pflashextgrp" };static const char * const sflashgrps[] = { "sflashgrp" };static const char * const gpio0grps[] = { "gpio0agrp" , "gpio0bgrp" , "gpio0cgrp" ,"gpio0dgrp" , "gpio0egrp" , "gpio0fgrp" ,"gpio0ggrp" , "gpio0hgrp" , "gpio0igrp" ,"gpio0jgrp" , "gpio0kgrp" , "gpio0lgrp" ,"gpio0mgrp" };static const char * const gpio1grps[] = { "gpio1agrp" , "gpio1bgrp" , "gpio1cgrp" ,"gpio1dgrp" };static const char * const gpio2grps[] = { "gpio2agrp" , "gpio2bgrp" , "gpio2cgrp" };static const struct gemini_pmx_func gemini_pmx_functions[] = {"dram" ,"rtc" ,"power" ,/* This function is strictly unavailable on 3512 */ "cir" ,"system" ,"vcontrol" ,"ice" ,"ide" ,"sata" ,"usb" ,"gmii" ,"pci" ,"lpc" ,"lcd" ,"ssp" ,"uart" ,"tvc" ,"nflash" ,"pflash" ,"sflash" ,"gpio0" ,"gpio1" ,"gpio2" ,static int gemini_pmx_set_mux(struct pinctrl_dev *pctldev,unsigned int selector,unsigned int group)struct gemini_pmx *pmx;const struct gemini_pmx_func *func;const struct gemini_pin_group *grp;unsigned long tmp;int i;if (pmx->is_3512)else if (pmx->is_3516)else {"invalid SoC type\n" );return -ENODEV;"ACTIVATE function \" %s\" with group \" %s\"\n" ,/* Which bits changed */ /* Print changed states */ bool enabled = !(i > 3 );/* Did not go low though it should */ if (after & BIT(i)) {"pin group %s could not be %s: " "probably a hardware limitation\n" ,"GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n" ,else {"padgroup %s %s\n" ,bool enabled = (i > 3 );/* Did not go high though it should */ if (!(after & BIT(i))) {"pin group %s could not be %s: " "probably a hardware limitation\n" ,"GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n" ,else {"padgroup %s %s\n" ,return 0 ;static int gemini_pmx_get_funcs_count(struct pinctrl_dev *pctldev)return ARRAY_SIZE(gemini_pmx_functions);static const char *gemini_pmx_get_func_name(struct pinctrl_dev *pctldev,unsigned int selector)return gemini_pmx_functions[selector].name;static int gemini_pmx_get_groups(struct pinctrl_dev *pctldev,unsigned int selector,const char * const **groups,unsigned int * const num_groups)return 0 ;static const struct pinmux_ops gemini_pmx_ops = {#define GEMINI_CFGPIN(_n, _r, _lb, _hb) { \static const struct gemini_pin_conf gemini_confs_3512[] = {259 , GLOBAL_GMAC_CTRL_SKEW, 0 , 3 ), /* GMAC0 RXDV */ 277 , GLOBAL_GMAC_CTRL_SKEW, 4 , 7 ), /* GMAC0 RXC */ 241 , GLOBAL_GMAC_CTRL_SKEW, 8 , 11 ), /* GMAC0 TXEN */ 312 , GLOBAL_GMAC_CTRL_SKEW, 12 , 15 ), /* GMAC0 TXC */ 298 , GLOBAL_GMAC_CTRL_SKEW, 16 , 19 ), /* GMAC1 RXDV */ 280 , GLOBAL_GMAC_CTRL_SKEW, 20 , 23 ), /* GMAC1 RXC */ 316 , GLOBAL_GMAC_CTRL_SKEW, 24 , 27 ), /* GMAC1 TXEN */ 243 , GLOBAL_GMAC_CTRL_SKEW, 28 , 31 ), /* GMAC1 TXC */ 295 , GLOBAL_GMAC0_DATA_SKEW, 0 , 3 ), /* GMAC0 RXD0 */ 313 , GLOBAL_GMAC0_DATA_SKEW, 4 , 7 ), /* GMAC0 RXD1 */ 242 , GLOBAL_GMAC0_DATA_SKEW, 8 , 11 ), /* GMAC0 RXD2 */ 260 , GLOBAL_GMAC0_DATA_SKEW, 12 , 15 ), /* GMAC0 RXD3 */ 294 , GLOBAL_GMAC0_DATA_SKEW, 16 , 19 ), /* GMAC0 TXD0 */ 276 , GLOBAL_GMAC0_DATA_SKEW, 20 , 23 ), /* GMAC0 TXD1 */ 258 , GLOBAL_GMAC0_DATA_SKEW, 24 , 27 ), /* GMAC0 TXD2 */ 240 , GLOBAL_GMAC0_DATA_SKEW, 28 , 31 ), /* GMAC0 TXD3 */ 262 , GLOBAL_GMAC1_DATA_SKEW, 0 , 3 ), /* GMAC1 RXD0 */ 244 , GLOBAL_GMAC1_DATA_SKEW, 4 , 7 ), /* GMAC1 RXD1 */ 317 , GLOBAL_GMAC1_DATA_SKEW, 8 , 11 ), /* GMAC1 RXD2 */ 299 , GLOBAL_GMAC1_DATA_SKEW, 12 , 15 ), /* GMAC1 RXD3 */ 261 , GLOBAL_GMAC1_DATA_SKEW, 16 , 19 ), /* GMAC1 TXD0 */ 279 , GLOBAL_GMAC1_DATA_SKEW, 20 , 23 ), /* GMAC1 TXD1 */ 297 , GLOBAL_GMAC1_DATA_SKEW, 24 , 27 ), /* GMAC1 TXD2 */ 315 , GLOBAL_GMAC1_DATA_SKEW, 28 , 31 ), /* GMAC1 TXD3 */ static const struct gemini_pin_conf gemini_confs_3516[] = {347 , GLOBAL_GMAC_CTRL_SKEW, 0 , 3 ), /* GMAC0 RXDV */ 386 , GLOBAL_GMAC_CTRL_SKEW, 4 , 7 ), /* GMAC0 RXC */ 307 , GLOBAL_GMAC_CTRL_SKEW, 8 , 11 ), /* GMAC0 TXEN */ 327 , GLOBAL_GMAC_CTRL_SKEW, 12 , 15 ), /* GMAC0 TXC */ 309 , GLOBAL_GMAC_CTRL_SKEW, 16 , 19 ), /* GMAC1 RXDV */ 390 , GLOBAL_GMAC_CTRL_SKEW, 20 , 23 ), /* GMAC1 RXC */ 370 , GLOBAL_GMAC_CTRL_SKEW, 24 , 27 ), /* GMAC1 TXEN */ 350 , GLOBAL_GMAC_CTRL_SKEW, 28 , 31 ), /* GMAC1 TXC */ 367 , GLOBAL_GMAC0_DATA_SKEW, 0 , 3 ), /* GMAC0 RXD0 */ 348 , GLOBAL_GMAC0_DATA_SKEW, 4 , 7 ), /* GMAC0 RXD1 */ 387 , GLOBAL_GMAC0_DATA_SKEW, 8 , 11 ), /* GMAC0 RXD2 */ 328 , GLOBAL_GMAC0_DATA_SKEW, 12 , 15 ), /* GMAC0 RXD3 */ 306 , GLOBAL_GMAC0_DATA_SKEW, 16 , 19 ), /* GMAC0 TXD0 */ 325 , GLOBAL_GMAC0_DATA_SKEW, 20 , 23 ), /* GMAC0 TXD1 */ 346 , GLOBAL_GMAC0_DATA_SKEW, 24 , 27 ), /* GMAC0 TXD2 */ 326 , GLOBAL_GMAC0_DATA_SKEW, 28 , 31 ), /* GMAC0 TXD3 */ 391 , GLOBAL_GMAC1_DATA_SKEW, 0 , 3 ), /* GMAC1 RXD0 */ 351 , GLOBAL_GMAC1_DATA_SKEW, 4 , 7 ), /* GMAC1 RXD1 */ 310 , GLOBAL_GMAC1_DATA_SKEW, 8 , 11 ), /* GMAC1 RXD2 */ 371 , GLOBAL_GMAC1_DATA_SKEW, 12 , 15 ), /* GMAC1 RXD3 */ 329 , GLOBAL_GMAC1_DATA_SKEW, 16 , 19 ), /* GMAC1 TXD0 */ 389 , GLOBAL_GMAC1_DATA_SKEW, 20 , 23 ), /* GMAC1 TXD1 */ 369 , GLOBAL_GMAC1_DATA_SKEW, 24 , 27 ), /* GMAC1 TXD2 */ 308 , GLOBAL_GMAC1_DATA_SKEW, 28 , 31 ), /* GMAC1 TXD3 */ static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx,unsigned int pin)const struct gemini_pin_conf *retconf;int i;for (i = 0 ; i < pmx->nconfs; i++) {if (retconf->pin == pin)return retconf;return NULL;static int gemini_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,unsigned long *config)struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);enum pin_config_param param = pinconf_to_config_param(*config);const struct gemini_pin_conf *conf;switch (param) {case PIN_CONFIG_SKEW_DELAY:if (!conf)return -ENOTSUPP;1 );break ;default :return -ENOTSUPP;return 0 ;static int gemini_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,unsigned long *configs, unsigned int num_configs)struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);const struct gemini_pin_conf *conf;enum pin_config_param param;int ret = 0 ;int i;for (i = 0 ; i < num_configs; i++) {switch (param) {case PIN_CONFIG_SKEW_DELAY:if (arg > 0 xf)return -EINVAL;if (!conf) {"invalid pin for skew delay %d\n" , pin);return -ENOTSUPP;1 );"set pin %d to skew delay mask %08x, val %08x\n" ,break ;default :"Invalid config param %04x\n" , param);return -ENOTSUPP;return ret;static int gemini_pinconf_group_set(struct pinctrl_dev *pctldev,unsigned selector,unsigned long *configs,unsigned num_configs)struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);const struct gemini_pin_group *grp = NULL;enum pin_config_param param;int i;if (pmx->is_3512)if (pmx->is_3516)/* First figure out if this group supports configs */ if (!grp->driving_mask) {"pin config group \" %s\" does " "not support drive strength setting\n" ,return -EINVAL;for (i = 0 ; i < num_configs; i++) {switch (param) {case PIN_CONFIG_DRIVE_STRENGTH:switch (arg) {case 4 :0 ;break ;case 8 :1 ;break ;case 12 :2 ;break ;case 16 :3 ;break ;default :"invalid drive strength %d mA\n" ,return -ENOTSUPP;1 );"set group %s to %d mA drive strength mask %08x val %08x\n" ,break ;default :"invalid config param %04x\n" , param);return -ENOTSUPP;return 0 ;static const struct pinconf_ops gemini_pinconf_ops = {true ,static struct pinctrl_desc gemini_pmx_desc = {static int gemini_pmx_probe(struct platform_device *pdev)struct gemini_pmx *pmx;struct regmap *map;struct device *dev = &pdev->dev;struct device *parent;unsigned long tmp;int ret;int i;/* Create state holders etc for this driver */ sizeof (*pmx), GFP_KERNEL);if (!pmx)return -ENOMEM;if (!parent) {"no parent to pin controller\n" );return -ENODEV;if (IS_ERR(map)) {"no syscon regmap\n" );return PTR_ERR(map);/* Check that regmap works at first call, then no more */ if (ret) {"cannot access regmap\n" );return ret;8 ;0 xffff;if (val == 0 x3512) {true ;"detected 3512 chip variant\n" );else if (val == 0 x3516) {true ;"detected 3516 chip variant\n" );else {"unknown chip ID: %04x\n" , val);return -ENODEV;"GLOBAL MISC CTRL at boot: 0x%08x\n" , val);/* Mask off relevant pads */ /* Invert the meaning of the DRAM+flash pads */ 0 x0f;/* Print initial state */ "pad group %s %s\n" , gemini_padgroups[i],/* Check if flash pin is set */ "flash pin is %s\n" , pmx->flash_pin ? "set" : "not set" );if (IS_ERR(pmx->pctl)) {"could not register pinmux driver\n" );return PTR_ERR(pmx->pctl);"initialized Gemini pin control driver\n" );return 0 ;static const struct of_device_id gemini_pinctrl_match[] = {"cortina,gemini-pinctrl" },static struct platform_driver gemini_pmx_driver = {static int __init gemini_pmx_init(void )return platform_driver_register(&gemini_pmx_driver);
Messung V0.5 in Prozent C=96 H=98 G=96
¤ Dauer der Verarbeitung: 0.33 Sekunden
(vorverarbeitet am 2026-06-07)
¤ *© Formatika GbR, Deutschland
